update

hw/syn/quartus/cache/Makefile

@@ -1,6 +1,6 @@
-PROJECT = VX_d_cache
-TOP_LEVEL_ENTITY = VX_d_cache
-SRC_FILE = ../../../rtl/cache/VX_d_cache.v
+PROJECT = VX_cache
+TOP_LEVEL_ENTITY = VX_cache
+SRC_FILE = ../../../rtl/cache/VX_cache.v
 PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf
 
 # Part, Family

hw/syn/quartus/vx_cache/Makefile

@@ -1,72 +0,0 @@
-PROJECT = VX_cache
-TOP_LEVEL_ENTITY = VX_cache
-SRC_FILE = ../../../rtl/cache/VX_cache.v
-PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf
-
-QUARTUS_ROOT ?= /tools/reconfig/intel/18.0
-
-# Part, Family
-FAMILY = "Arria 10"
-DEVICE = 10AX115N3F40E2SG   
-
-# Executable Configuration
-SYN_ARGS = --parallel --read_settings_files=on
-FIT_ARGS = --part=$(DEVICE) --read_settings_files=on
-ASM_ARGS =
-STA_ARGS = --do_report_timing
-
-# Build targets
-all: $(PROJECT).sta.rpt
-
-syn: $(PROJECT).syn.rpt
-
-fit: $(PROJECT).fit.rpt
-
-asm: $(PROJECT).asm.rpt
-
-sta: $(PROJECT).sta.rpt
-
-smart: smart.log
-
-# Target implementations
-STAMP = echo done >
-
-$(PROJECT).syn.rpt: smart.log syn.chg $(SOURCE_FILES) 
-	quartus_syn $(PROJECT) $(SYN_ARGS)
-	$(STAMP) fit.chg
-
-$(PROJECT).fit.rpt: smart.log fit.chg $(PROJECT).syn.rpt
-	quartus_fit $(PROJECT) $(FIT_ARGS)
-	$(STAMP) asm.chg
-	$(STAMP) sta.chg
-
-$(PROJECT).asm.rpt: smart.log asm.chg $(PROJECT).fit.rpt
-	quartus_asm $(PROJECT) $(ASM_ARGS)
-
-$(PROJECT).sta.rpt: smart.log sta.chg $(PROJECT).fit.rpt
-	quartus_sta $(PROJECT)  $(STA_ARGS) 
-
-smart.log: $(PROJECT_FILES)
-	quartus_sh --determine_smart_action $(PROJECT) > smart.log
-
-# Project initialization
-$(PROJECT_FILES):
-	quartus_sh -t project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src $(SRC_FILE) -sdc project.sdc -inc "../;../../"
-	
-syn.chg:
-	$(STAMP) syn.chg
-
-fit.chg:
-	$(STAMP) fit.chg
-
-sta.chg:
-	$(STAMP) sta.chg
-
-asm.chg:
-	$(STAMP) asm.chg
-
-program: $(PROJECT).sof
-	quartus_pgm --no_banner --mode=jtag -o "P;$(PROJECT).sof"
-	
-clean:
-	rm -rf bin *.rpt *.chg *.qsf *.qpf smart.log *.htm *.eqn *.pin *.sof *.pof qdb incremental_db tmp-clearbox

hw/syn/quartus/vx_cache/project.sdc

@@ -1 +0,0 @@
-create_clock -name {clk} -period "250 MHz" -waveform { 0.0 1.0 } [get_ports {clk}]

hw/syn/quartus/vx_cache/project.tcl

@@ -1,41 +0,0 @@
-load_package flow
-package require cmdline
-
-set options { \
-    { "project.arg" "" "Project name" } \
-    { "family.arg" "" "Device family name" } \
-    { "device.arg" "" "Device name" } \
-    { "top.arg" "" "Top level module" } \
-    { "sdc.arg" "" "Timing Design Constraints file" } \
-    { "src.arg" "" "Verilog source file" } \
-    { "inc.arg" "." "Include path" } \
-}
-
-array set opts [::cmdline::getoptions quartus(args) $options]
-
-project_new $opts(project) -overwrite
-
-set_global_assignment -name FAMILY $opts(family)
-set_global_assignment -name DEVICE $opts(device)
-set_global_assignment -name TOP_LEVEL_ENTITY $opts(top)
-set_global_assignment -name VERILOG_FILE $opts(src)
-set_global_assignment -name SEARCH_PATH $opts(inc)
-set_global_assignment -name SDC_FILE $opts(sdc)
-set_global_assignment -name PROJECT_OUTPUT_DIRECTORY bin
-set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
-set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2009
-
-proc make_all_pins_virtual {} {
-    execute_module -tool map
-    set name_ids [get_names -filter * -node_type pin]
-    foreach_in_collection name_id $name_ids {        
-        set pin_name [get_name_info -info full_path $name_id]
-        post_message "Making VIRTUAL_PIN assignment to $pin_name"
-        set_instance_assignment -to $pin_name -name VIRTUAL_PIN ON
-    }
-    export_assignments
-}
-
-make_all_pins_virtual
-
-project_close