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https://github.com/vortexgpgpu/vortex.git
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opae afu x warning fixes
This commit is contained in:
Blaise Tine
parent
aa1489d8eb
commit
0cbdc3be9e
1 changed files with 83 additions and 77 deletions
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@ -64,6 +64,7 @@ module vortex_afu import ccip_if_pkg::*; import local_mem_cfg_pkg::*; import VX_
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localparam AFU_ID_L = 16'h0002; // AFU ID Lower
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localparam AFU_ID_H = 16'h0004; // AFU ID Higher
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localparam CMD_IDLE = 0;
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localparam CMD_MEM_READ = `AFU_IMAGE_CMD_MEM_READ;
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localparam CMD_MEM_WRITE = `AFU_IMAGE_CMD_MEM_WRITE;
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localparam CMD_DCR_WRITE = `AFU_IMAGE_CMD_DCR_WRITE;
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@ -139,14 +140,12 @@ module vortex_afu import ccip_if_pkg::*; import local_mem_cfg_pkg::*; import VX_
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// MMIO controller ////////////////////////////////////////////////////////////
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t_ccip_c0_ReqMmioHdr mmio_hdr;
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assign mmio_hdr = t_ccip_c0_ReqMmioHdr'(cp2af_sRxPort.c0.hdr);
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`UNUSED_VAR (mmio_hdr)
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t_ccip_c0_ReqMmioHdr mmio_req_hdr;
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assign mmio_req_hdr = t_ccip_c0_ReqMmioHdr'(cp2af_sRxPort.c0.hdr[$bits(t_ccip_c0_ReqMmioHdr)-1:0]);
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`UNUSED_VAR (mmio_req_hdr)
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`STATIC_ASSERT(($bits(t_ccip_c0_ReqMmioHdr)-$bits(mmio_hdr.address)) == 12, ("Oops!"))
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t_if_ccip_c2_Tx mmio_tx;
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assign af2cp_sTxPort.c2 = mmio_tx;
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t_if_ccip_c2_Tx mmio_rsp;
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assign af2cp_sTxPort.c2 = mmio_rsp;
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`ifdef SCOPE
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@ -178,7 +177,7 @@ module vortex_afu import ccip_if_pkg::*; import local_mem_cfg_pkg::*; import VX_
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end
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scope_bus_in <= 0;
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if (cp2af_sRxPort.c0.mmioWrValid
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&& (MMIO_SCOPE_WRITE == mmio_hdr.address)) begin
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&& (MMIO_SCOPE_WRITE == mmio_req_hdr.address)) begin
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cmd_scope_wdata <= 64'(cp2af_sRxPort.c0.data);
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cmd_scope_writing <= 1;
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scope_bus_ctr <= 63;
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@ -206,6 +205,8 @@ module vortex_afu import ccip_if_pkg::*; import local_mem_cfg_pkg::*; import VX_
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wire [COUT_QUEUE_DATAW-1:0] cout_q_dout;
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wire cout_q_full, cout_q_empty;
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wire [COUT_QUEUE_DATAW-1:0] cout_q_dout_s = cout_q_dout & {COUT_QUEUE_DATAW{!cout_q_empty}};
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`ifdef SIMULATION
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`ifndef VERILATOR
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// disable assertions until full reset
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@ -226,17 +227,79 @@ module vortex_afu import ccip_if_pkg::*; import local_mem_cfg_pkg::*; import VX_
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`endif
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`endif
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// MMIO controller ////////////////////////////////////////////////////////////
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// Handle MMIO read requests
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always @(posedge clk) begin
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if (reset) begin
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mmio_tx.mmioRdValid <= 0;
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mmio_tx.hdr <= '0;
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mmio_rsp.mmioRdValid <= 0;
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end else begin
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mmio_tx.mmioRdValid <= cp2af_sRxPort.c0.mmioRdValid;
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mmio_tx.hdr.tid <= mmio_hdr.tid;
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mmio_rsp.mmioRdValid <= cp2af_sRxPort.c0.mmioRdValid;
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end
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// serve MMIO write request
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mmio_rsp.hdr.tid <= mmio_req_hdr.tid;
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if (cp2af_sRxPort.c0.mmioRdValid) begin
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case (mmio_req_hdr.address)
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// AFU header
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16'h0000: mmio_rsp.data <= {
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4'b0001, // Feature type = AFU
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8'b0, // reserved
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4'b0, // afu minor revision = 0
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7'b0, // reserved
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1'b1, // end of DFH list = 1
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24'b0, // next DFH offset = 0
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4'b0, // afu major revision = 0
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12'b0 // feature ID = 0
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};
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AFU_ID_L: mmio_rsp.data <= afu_id[63:0]; // afu id low
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AFU_ID_H: mmio_rsp.data <= afu_id[127:64]; // afu id hi
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16'h0006: mmio_rsp.data <= 64'h0; // next AFU
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16'h0008: mmio_rsp.data <= 64'h0; // reserved
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MMIO_STATUS: begin
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mmio_rsp.data <= 64'({cout_q_dout_s, !cout_q_empty, 8'(state)});
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`ifdef DBG_TRACE_AFU
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if (state != STATE_WIDTH'(mmio_rsp.data)) begin
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`TRACE(2, ("%d: MMIO_STATUS: addr=0x%0h, state=%0d\n", $time, mmio_req_hdr.address, state));
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end
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`endif
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end
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`ifdef SCOPE
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MMIO_SCOPE_READ: begin
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mmio_rsp.data <= cmd_scope_rdata;
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`ifdef DBG_TRACE_AFU
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`TRACE(2, ("%d: MMIO_SCOPE_READ: data=0x%h\n", $time, cmd_scope_rdata));
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`endif
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end
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`endif
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MMIO_DEV_CAPS: begin
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mmio_rsp.data <= dev_caps;
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`ifdef DBG_TRACE_AFU
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`TRACE(2, ("%d: MMIO_DEV_CAPS: data=0x%h\n", $time, dev_caps));
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`endif
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end
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MMIO_ISA_CAPS: begin
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mmio_rsp.data <= isa_caps;
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`ifdef DBG_TRACE_AFU
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if (state != STATE_WIDTH'(mmio_rsp.data)) begin
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`TRACE(2, ("%d: MMIO_ISA_CAPS: data=%0d\n", $time, isa_caps));
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end
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`endif
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end
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default: begin
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mmio_rsp.data <= 64'h0;
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`ifdef DBG_TRACE_AFU
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`TRACE(2, ("%d: Unknown MMIO Rd: addr=0x%0h\n", $time, mmio_req_hdr.address));
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`endif
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end
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endcase
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end
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end
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// Handle MMIO write requests
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always @(posedge clk) begin
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if (cp2af_sRxPort.c0.mmioWrValid) begin
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case (mmio_hdr.address)
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case (mmio_req_hdr.address)
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MMIO_CMD_ARG0: begin
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cmd_args[0] <= 64'(cp2af_sRxPort.c0.data);
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`ifdef DBG_TRACE_AFU
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@ -269,68 +332,11 @@ module vortex_afu import ccip_if_pkg::*; import local_mem_cfg_pkg::*; import VX_
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`endif
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default: begin
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`ifdef DBG_TRACE_AFU
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`TRACE(2, ("%d: Unknown MMIO Wr: addr=0x%0h, data=0x%h\n", $time, mmio_hdr.address, 64'(cp2af_sRxPort.c0.data)));
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`TRACE(2, ("%d: Unknown MMIO Wr: addr=0x%0h, data=0x%h\n", $time, mmio_req_hdr.address, 64'(cp2af_sRxPort.c0.data)));
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`endif
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end
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endcase
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end
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// serve MMIO read requests
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if (cp2af_sRxPort.c0.mmioRdValid) begin
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case (mmio_hdr.address)
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// AFU header
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16'h0000: mmio_tx.data <= {
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4'b0001, // Feature type = AFU
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8'b0, // reserved
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4'b0, // afu minor revision = 0
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7'b0, // reserved
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1'b1, // end of DFH list = 1
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24'b0, // next DFH offset = 0
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4'b0, // afu major revision = 0
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12'b0 // feature ID = 0
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};
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AFU_ID_L: mmio_tx.data <= afu_id[63:0]; // afu id low
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AFU_ID_H: mmio_tx.data <= afu_id[127:64]; // afu id hi
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16'h0006: mmio_tx.data <= 64'h0; // next AFU
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16'h0008: mmio_tx.data <= 64'h0; // reserved
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MMIO_STATUS: begin
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mmio_tx.data <= 64'({cout_q_dout, !cout_q_empty, 8'(state)});
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`ifdef DBG_TRACE_AFU
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if (state != STATE_WIDTH'(mmio_tx.data)) begin
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`TRACE(2, ("%d: MMIO_STATUS: addr=0x%0h, state=%0d\n", $time, mmio_hdr.address, state));
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end
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`endif
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end
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`ifdef SCOPE
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MMIO_SCOPE_READ: begin
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mmio_tx.data <= cmd_scope_rdata;
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`ifdef DBG_TRACE_AFU
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`TRACE(2, ("%d: MMIO_SCOPE_READ: data=0x%h\n", $time, cmd_scope_rdata));
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`endif
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end
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`endif
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MMIO_DEV_CAPS: begin
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mmio_tx.data <= dev_caps;
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`ifdef DBG_TRACE_AFU
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`TRACE(2, ("%d: MMIO_DEV_CAPS: data=0x%h\n", $time, dev_caps));
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`endif
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end
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MMIO_ISA_CAPS: begin
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mmio_tx.data <= isa_caps;
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`ifdef DBG_TRACE_AFU
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if (state != STATE_WIDTH'(mmio_tx.data)) begin
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`TRACE(2, ("%d: MMIO_ISA_CAPS: data=%0d\n", $time, isa_caps));
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end
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`endif
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end
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default: begin
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mmio_tx.data <= 64'h0;
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`ifdef DBG_TRACE_AFU
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`TRACE(2, ("%d: Unknown MMIO Rd: addr=0x%0h\n", $time, mmio_hdr.address));
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`endif
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end
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endcase
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end
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end
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// COMMAND FSM ////////////////////////////////////////////////////////////////
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@ -351,9 +357,9 @@ module vortex_afu import ccip_if_pkg::*; import local_mem_cfg_pkg::*; import VX_
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end
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end
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wire is_mmio_wr_cmd = cp2af_sRxPort.c0.mmioWrValid && (MMIO_CMD_TYPE == mmio_hdr.address);
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wire is_mmio_wr_cmd = cp2af_sRxPort.c0.mmioWrValid && (MMIO_CMD_TYPE == mmio_req_hdr.address);
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wire [CMD_TYPE_WIDTH-1:0] cmd_type = is_mmio_wr_cmd ?
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CMD_TYPE_WIDTH'(cp2af_sRxPort.c0.data) : CMD_TYPE_WIDTH'(0);
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CMD_TYPE_WIDTH'(cp2af_sRxPort.c0.data) : CMD_TYPE_WIDTH'(CMD_IDLE);
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always @(posedge clk) begin
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if (reset) begin
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@ -978,7 +984,7 @@ module vortex_afu import ccip_if_pkg::*; import local_mem_cfg_pkg::*; import VX_
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wire cout_q_push = vx_mem_req_valid && vx_mem_is_cout && ~cout_q_full;
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wire cout_q_pop = cp2af_sRxPort.c0.mmioRdValid
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&& (mmio_hdr.address == MMIO_STATUS)
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&& (mmio_req_hdr.address == MMIO_STATUS)
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&& ~cout_q_empty;
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VX_fifo_queue #(
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@ -1051,8 +1057,8 @@ module vortex_afu import ccip_if_pkg::*; import local_mem_cfg_pkg::*; import VX_
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.probes({
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cmd_type,
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state,
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mmio_hdr.address,
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mmio_hdr.length,
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mmio_req_hdr.address,
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mmio_req_hdr.length,
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cp2af_sRxPort.c0.hdr.mdata,
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af2cp_sTxPort.c0.hdr.address,
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af2cp_sTxPort.c0.hdr.mdata,
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