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https://github.com/vortexgpgpu/vortex.git
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xilixn simulation doesn't support tasks in header files.
This commit is contained in:
Blaise Tine
parent
280a1dfd71
commit
0ce7fadd74
1 changed files with 126 additions and 140 deletions
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@ -13,146 +13,132 @@
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default: `TRACE(level, ("?")); \
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endcase
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task trace_ex_op (
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input int level,
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input [`EX_BITS-1:0] ex_type,
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input [`INST_OP_BITS-1:0] op_type,
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input [`INST_MOD_BITS-1:0] op_mod
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);
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case (ex_type)
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`EX_ALU: begin
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if (`INST_ALU_IS_BR(op_mod)) begin
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case (`INST_BR_BITS'(op_type))
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`INST_BR_EQ: `TRACE(level, ("BEQ"));
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`INST_BR_NE: `TRACE(level, ("BNE"));
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`INST_BR_LT: `TRACE(level, ("BLT"));
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`INST_BR_GE: `TRACE(level, ("BGE"));
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`INST_BR_LTU: `TRACE(level, ("BLTU"));
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`INST_BR_GEU: `TRACE(level, ("BGEU"));
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`INST_BR_JAL: `TRACE(level, ("JAL"));
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`INST_BR_JALR: `TRACE(level, ("JALR"));
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`INST_BR_ECALL: `TRACE(level, ("ECALL"));
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`INST_BR_EBREAK:`TRACE(level, ("EBREAK"));
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`INST_BR_URET: `TRACE(level, ("URET"));
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`INST_BR_SRET: `TRACE(level, ("SRET"));
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`INST_BR_MRET: `TRACE(level, ("MRET"));
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default: `TRACE(level, ("?"));
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endcase
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end else if (`INST_ALU_IS_MUL(op_mod)) begin
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case (`INST_MUL_BITS'(op_type))
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`INST_MUL_MUL: `TRACE(level, ("MUL"));
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`INST_MUL_MULH: `TRACE(level, ("MULH"));
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`INST_MUL_MULHSU:`TRACE(level, ("MULHSU"));
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`INST_MUL_MULHU: `TRACE(level, ("MULHU"));
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`INST_MUL_DIV: `TRACE(level, ("DIV"));
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`INST_MUL_DIVU: `TRACE(level, ("DIVU"));
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`INST_MUL_REM: `TRACE(level, ("REM"));
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`INST_MUL_REMU: `TRACE(level, ("REMU"));
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`INST_MUL_MULW: `TRACE(level, ("MULW"));
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`INST_MUL_DIVW: `TRACE(level, ("DIVW"));
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`INST_MUL_DIVUW: `TRACE(level, ("DIVUW"));
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default: `TRACE(level, ("?"));
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endcase
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end else begin
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case (`INST_ALU_BITS'(op_type))
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`INST_ALU_ADD: `TRACE(level, ("ADD"));
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`INST_ALU_SUB: `TRACE(level, ("SUB"));
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`INST_ALU_SLL: `TRACE(level, ("SLL"));
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`INST_ALU_SRL: `TRACE(level, ("SRL"));
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`INST_ALU_SRA: `TRACE(level, ("SRA"));
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`INST_ALU_SLT: `TRACE(level, ("SLT"));
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`INST_ALU_SLTU: `TRACE(level, ("SLTU"));
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`INST_ALU_XOR: `TRACE(level, ("XOR"));
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`INST_ALU_OR: `TRACE(level, ("OR"));
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`INST_ALU_AND: `TRACE(level, ("AND"));
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`INST_ALU_LUI: `TRACE(level, ("LUI"));
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`INST_ALU_AUIPC: `TRACE(level, ("AUIPC"));
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`INST_ALU_ADD_W: `TRACE(level, ("ADD_W"));
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`INST_ALU_SUB_W: `TRACE(level, ("SUB_W"));
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`INST_ALU_SLL_W: `TRACE(level, ("SLL_W"));
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`INST_ALU_SRL_W: `TRACE(level, ("SRL_W"));
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`INST_ALU_SRA_W: `TRACE(level, ("SRA_W"));
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default: `TRACE(level, ("?"));
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endcase
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end
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end
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`EX_LSU: begin
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if (op_mod == 0) begin
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case (`INST_LSU_BITS'(op_type))
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`INST_LSU_LB: `TRACE(level, ("LB"));
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`INST_LSU_LH: `TRACE(level, ("LH"));
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`INST_LSU_LW: `TRACE(level, ("LW"));
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`INST_LSU_LBU:`TRACE(level, ("LBU"));
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`INST_LSU_LHU:`TRACE(level, ("LHU"));
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`INST_LSU_SB: `TRACE(level, ("SB"));
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`INST_LSU_SH: `TRACE(level, ("SH"));
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`INST_LSU_SW: `TRACE(level, ("SW"));
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default: `TRACE(level, ("?"));
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endcase
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end else if (op_mod == 1) begin
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case (`INST_FENCE_BITS'(op_type))
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`INST_FENCE_D: `TRACE(level, ("DFENCE"));
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`INST_FENCE_I: `TRACE(level, ("IFENCE"));
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default: `TRACE(level, ("?"));
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endcase
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end
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end
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`EX_CSR: begin
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case (`INST_CSR_BITS'(op_type))
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`INST_CSR_RW: `TRACE(level, ("CSRW"));
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`INST_CSR_RS: `TRACE(level, ("CSRS"));
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`INST_CSR_RC: `TRACE(level, ("CSRC"));
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default: `TRACE(level, ("?"));
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endcase
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end
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`EX_FPU: begin
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case (`INST_FPU_BITS'(op_type))
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`INST_FPU_ADD: `TRACE(level, ("ADD"));
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`INST_FPU_SUB: `TRACE(level, ("SUB"));
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`INST_FPU_MUL: `TRACE(level, ("MUL"));
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`INST_FPU_DIV: `TRACE(level, ("DIV"));
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`INST_FPU_SQRT: `TRACE(level, ("SQRT"));
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`INST_FPU_MADD: `TRACE(level, ("MADD"));
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`INST_FPU_NMSUB: `TRACE(level, ("NMSUB"));
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`INST_FPU_NMADD: `TRACE(level, ("NMADD"));
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`INST_FPU_CVTWS: `TRACE(level, ("CVTWS"));
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`INST_FPU_CVTWUS:`TRACE(level, ("CVTWUS"));
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`INST_FPU_CVTSW: `TRACE(level, ("CVTSW"));
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`INST_FPU_CVTSWU:`TRACE(level, ("CVTSWU"));
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`INST_FPU_CLASS: `TRACE(level, ("CLASS"));
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`INST_FPU_CMP: `TRACE(level, ("CMP"));
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`INST_FPU_MISC: begin
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case (op_mod)
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0: `TRACE(level, ("SGNJ"));
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1: `TRACE(level, ("SGNJN"));
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2: `TRACE(level, ("SGNJX"));
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3: `TRACE(level, ("MIN"));
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4: `TRACE(level, ("MAX"));
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5: `TRACE(level, ("MVXW"));
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6: `TRACE(level, ("MVWX"));
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endcase
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end
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default: `TRACE(level, ("?"));
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endcase
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end
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`EX_GPU: begin
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case (`INST_GPU_BITS'(op_type))
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`INST_GPU_TMC: `TRACE(level, ("TMC"));
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`INST_GPU_WSPAWN:`TRACE(level, ("WSPAWN"));
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`INST_GPU_SPLIT: `TRACE(level, ("SPLIT"));
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`INST_GPU_JOIN: `TRACE(level, ("JOIN"));
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`INST_GPU_BAR: `TRACE(level, ("BAR"));
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`INST_GPU_PRED: `TRACE(level, ("PRED"));
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`INST_GPU_TEX: `TRACE(level, ("TEX"));
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`INST_GPU_RASTER:`TRACE(level, ("RASTER"));
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`INST_GPU_ROP: `TRACE(level, ("ROP"));
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`INST_GPU_IMADD: `TRACE(level, ("IMADD"));
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default: `TRACE(level, ("?"));
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endcase
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end
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default: `TRACE(level, ("?"));
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endcase
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endtask
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`define TRACE_EX_OP(level, ex_type, op_type, op_mod) \
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case (ex_type) \
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`EX_ALU: begin \
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if (`INST_ALU_IS_BR(op_mod)) begin \
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case (`INST_BR_BITS'(op_type)) \
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`INST_BR_EQ: `TRACE(level, ("BEQ")); \
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`INST_BR_NE: `TRACE(level, ("BNE")); \
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`INST_BR_LT: `TRACE(level, ("BLT")); \
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`INST_BR_GE: `TRACE(level, ("BGE")); \
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`INST_BR_LTU: `TRACE(level, ("BLTU")); \
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`INST_BR_GEU: `TRACE(level, ("BGEU")); \
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`INST_BR_JAL: `TRACE(level, ("JAL")); \
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`INST_BR_JALR: `TRACE(level, ("JALR")); \
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`INST_BR_ECALL: `TRACE(level, ("ECALL")); \
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`INST_BR_EBREAK:`TRACE(level, ("EBREAK")); \
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`INST_BR_URET: `TRACE(level, ("URET")); \
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`INST_BR_SRET: `TRACE(level, ("SRET")); \
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`INST_BR_MRET: `TRACE(level, ("MRET")); \
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default: `TRACE(level, ("?")); \
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endcase \
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end else if (`INST_ALU_IS_MUL(op_mod)) begin \
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case (`INST_MUL_BITS'(op_type)) \
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`INST_MUL_MUL: `TRACE(level, ("MUL")); \
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`INST_MUL_MULH: `TRACE(level, ("MULH")); \
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`INST_MUL_MULHSU:`TRACE(level, ("MULHSU")); \
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`INST_MUL_MULHU: `TRACE(level, ("MULHU")); \
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`INST_MUL_DIV: `TRACE(level, ("DIV")); \
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`INST_MUL_DIVU: `TRACE(level, ("DIVU")); \
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`INST_MUL_REM: `TRACE(level, ("REM")); \
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`INST_MUL_REMU: `TRACE(level, ("REMU")); \
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default: `TRACE(level, ("?")); \
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endcase \
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end else begin \
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case (`INST_ALU_BITS'(op_type)) \
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`INST_ALU_ADD: `TRACE(level, ("ADD")); \
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`INST_ALU_SUB: `TRACE(level, ("SUB")); \
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`INST_ALU_SLL: `TRACE(level, ("SLL")); \
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`INST_ALU_SRL: `TRACE(level, ("SRL")); \
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`INST_ALU_SRA: `TRACE(level, ("SRA")); \
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`INST_ALU_SLT: `TRACE(level, ("SLT")); \
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`INST_ALU_SLTU: `TRACE(level, ("SLTU")); \
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`INST_ALU_XOR: `TRACE(level, ("XOR")); \
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`INST_ALU_OR: `TRACE(level, ("OR")); \
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`INST_ALU_AND: `TRACE(level, ("AND")); \
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`INST_ALU_LUI: `TRACE(level, ("LUI")); \
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`INST_ALU_AUIPC: `TRACE(level, ("AUIPC")); \
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default: `TRACE(level, ("?")); \
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endcase \
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end \
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end \
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`EX_LSU: begin \
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if (op_mod == 0) begin \
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case (`INST_LSU_BITS'(op_type)) \
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`INST_LSU_LB: `TRACE(level, ("LB")); \
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`INST_LSU_LH: `TRACE(level, ("LH")); \
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`INST_LSU_LW: `TRACE(level, ("LW")); \
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`INST_LSU_LBU:`TRACE(level, ("LBU")); \
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`INST_LSU_LHU:`TRACE(level, ("LHU")); \
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`INST_LSU_SB: `TRACE(level, ("SB")); \
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`INST_LSU_SH: `TRACE(level, ("SH")); \
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`INST_LSU_SW: `TRACE(level, ("SW")); \
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default: `TRACE(level, ("?")); \
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endcase \
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end else if (op_mod == 1) begin \
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case (`INST_FENCE_BITS'(op_type)) \
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`INST_FENCE_D: `TRACE(level, ("DFENCE")); \
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`INST_FENCE_I: `TRACE(level, ("IFENCE")); \
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default: `TRACE(level, ("?")); \
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endcase \
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end \
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end \
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`EX_CSR: begin \
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case (`INST_CSR_BITS'(op_type)) \
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`INST_CSR_RW: `TRACE(level, ("CSRW")); \
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`INST_CSR_RS: `TRACE(level, ("CSRS")); \
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`INST_CSR_RC: `TRACE(level, ("CSRC")); \
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default: `TRACE(level, ("?")); \
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endcase \
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end \
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`EX_FPU: begin \
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case (`INST_FPU_BITS'(op_type)) \
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`INST_FPU_ADD: `TRACE(level, ("ADD")); \
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`INST_FPU_SUB: `TRACE(level, ("SUB")); \
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`INST_FPU_MUL: `TRACE(level, ("MUL")); \
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`INST_FPU_DIV: `TRACE(level, ("DIV")); \
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`INST_FPU_SQRT: `TRACE(level, ("SQRT")); \
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`INST_FPU_MADD: `TRACE(level, ("MADD")); \
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`INST_FPU_NMSUB: `TRACE(level, ("NMSUB")); \
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`INST_FPU_NMADD: `TRACE(level, ("NMADD")); \
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`INST_FPU_CVTWS: `TRACE(level, ("CVTWS")); \
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`INST_FPU_CVTWUS:`TRACE(level, ("CVTWUS")); \
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`INST_FPU_CVTSW: `TRACE(level, ("CVTSW")); \
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`INST_FPU_CVTSWU:`TRACE(level, ("CVTSWU")); \
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`INST_FPU_CLASS: `TRACE(level, ("CLASS")); \
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`INST_FPU_CMP: `TRACE(level, ("CMP")); \
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`INST_FPU_MISC: begin \
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case (op_mod) \
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0: `TRACE(level, ("SGNJ")); \
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1: `TRACE(level, ("SGNJN")); \
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2: `TRACE(level, ("SGNJX")); \
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3: `TRACE(level, ("MIN")); \
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4: `TRACE(level, ("MAX")); \
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5: `TRACE(level, ("MVXW")); \
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6: `TRACE(level, ("MVWX")); \
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endcase \
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end \
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default: `TRACE(level, ("?")); \
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endcase \
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end \
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`EX_GPU: begin \
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case (`INST_GPU_BITS'(op_type)) \
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`INST_GPU_TMC: `TRACE(level, ("TMC")); \
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`INST_GPU_WSPAWN:`TRACE(level, ("WSPAWN")); \
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`INST_GPU_SPLIT: `TRACE(level, ("SPLIT")); \
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`INST_GPU_JOIN: `TRACE(level, ("JOIN")); \
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`INST_GPU_BAR: `TRACE(level, ("BAR")); \
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`INST_GPU_PRED: `TRACE(level, ("PRED")); \
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`INST_GPU_TEX: `TRACE(level, ("TEX")); \
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`INST_GPU_RASTER:`TRACE(level, ("RASTER")); \
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`INST_GPU_ROP: `TRACE(level, ("ROP")); \
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`INST_GPU_IMADD: `TRACE(level, ("IMADD")); \
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default: `TRACE(level, ("?")); \
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endcase \
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end \
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default: `TRACE(level, ("?")); \
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endcase
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`define TRACE_BASE_DCR(level, addr) \
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case (addr) \
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