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Readded the ecall and ebreak instruction traps so that the riscv-vector tests run properly

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This commit is contained in:
MichaelJSr 2024-10-14 10:12:33 -07:00
parent 91c135ac15
commit 0d04423074
3 changed files with 20 additions and 0 deletions
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12
sim/simx/emulator.cpp
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@ -625,3 +625,15 @@ void Emulator::update_fcrs(uint32_t fflags, uint32_t tid, uint32_t wid) {
this->set_csr(VX_CSR_FFLAGS, this->get_csr(VX_CSR_FFLAGS, tid, wid) | fflags, tid, wid);
}
}
// For riscv-vector test functionality, ecall and ebreak must trap
// These instructions are used in the vector tests to stop execution of the test
// Therefore, without these instructions, undefined and incorrect behavior happens
//
// For now, we need these instructions to trap for testing the riscv-vector isa
void Emulator::trigger_ecall() {
active_warps_.reset();
}
void Emulator::trigger_ebreak() {
active_warps_.reset();
}

4
sim/simx/emulator.h
View file

@ -122,6 +122,10 @@ private:
void update_fcrs(uint32_t fflags, uint32_t tid, uint32_t wid);
void trigger_ecall(); // Re-added for riscv-vector test functionality
void trigger_ebreak(); // Re-added for riscv-vector test functionality
const Arch& arch_;
const DCRS& dcrs_;
Core* core_;

4
sim/simx/execute.cpp
View file

@ -830,7 +830,11 @@ void Emulator::execute(const Instr &instr, uint32_t wid, instr_trace_t *trace) {
trace->fetch_stall = true;
switch (csr_addr) {
case 0x000: // RV32I: ECALL
this->trigger_ecall(); // Re-added for riscv-vector test functionality
break;
case 0x001: // RV32I: EBREAK
this->trigger_ebreak(); // Re-added for riscv-vector test functionality
break;
case 0x002: // RV32I: URET
case 0x102: // RV32I: SRET
case 0x302: // RV32I: MRET