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This commit is contained in:
Blaise Tine 2024-10-20 07:49:27 -07:00
parent 9373e21950
commit 0f380a3d78
2 changed files with 11 additions and 15 deletions
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15
hw/rtl/cache/VX_cache_repl.sv vendored
View file

@ -110,7 +110,6 @@ module VX_cache_repl #(
if (REPL_POLICY == `CS_REPL_PLRU) begin : g_plru
// Pseudo Least Recently Used replacement policy
localparam LRU_WIDTH = `UP(NUM_WAYS-1);
localparam USE_BRAM = (LRU_WIDTH * `CS_LINES_PER_BANK) >= `MAX_LUTRAM;
wire [LRU_WIDTH-1:0] plru_rdata;
wire [LRU_WIDTH-1:0] plru_wdata;
@ -120,15 +119,15 @@ module VX_cache_repl #(
.DATAW (LRU_WIDTH),
.SIZE (`CS_LINES_PER_BANK),
.WRENW (LRU_WIDTH),
.OUT_REG (USE_BRAM)
.OUT_REG (1)
) plru_store (
.clk (clk),
.reset (reset),
.read (USE_BRAM ? ~stall : repl_valid),
.read (~stall),
.write (hit_valid),
.wren (plru_wmask),
.waddr (hit_line),
.raddr (USE_BRAM ? repl_line_n : repl_line),
.raddr (repl_line_n),
.wdata (plru_wdata),
.rdata (plru_rdata)
);
@ -150,8 +149,6 @@ module VX_cache_repl #(
end else if (REPL_POLICY == `CS_REPL_CYCLIC) begin : g_cyclic
// Cyclic replacement policy
localparam USE_BRAM = (WAY_SEL_WIDTH * `CS_LINES_PER_BANK) >= `MAX_LUTRAM;
`UNUSED_VAR (hit_valid)
`UNUSED_VAR (hit_line)
`UNUSED_VAR (hit_way)
@ -163,14 +160,14 @@ module VX_cache_repl #(
VX_dp_ram #(
.DATAW (WAY_SEL_WIDTH),
.SIZE (`CS_LINES_PER_BANK),
.OUT_REG (USE_BRAM)
.OUT_REG (1)
) ctr_store (
.clk (clk),
.reset (reset),
.read (USE_BRAM ? ~stall : repl_valid),
.read (~stall),
.write (repl_valid),
.wren (1'b1),
.raddr (USE_BRAM ? repl_line_n : repl_line),
.raddr (repl_line_n),
.waddr (repl_line),
.wdata (ctr_wdata),
.rdata (ctr_rdata)

11
hw/rtl/libs/VX_sp_ram.sv
View file

@ -141,18 +141,17 @@ module VX_sp_ram #(
reg [DATAW-1:0] ram [0:SIZE-1];
`RAM_INITIALIZATION
wire [DATAW-1:0] ram_n;
for (genvar i = 0; i < WRENW; ++i) begin : g_ram_n
assign ram_n[i * WSELW +: WSELW] = wren[i] ? wdata[i * WSELW +: WSELW] : ram[addr][i * WSELW +: WSELW];
end
always @(posedge clk) begin
if (RESET_RAM && reset) begin
for (integer i = 0; i < SIZE; ++i) begin
ram[i] <= DATAW'(INIT_VALUE);
end
end else if (write) begin
ram[addr] <= ram_n;
for (integer i = 0; i < WRENW; ++i) begin
if (wren[i]) begin
ram[addr][i * WSELW +: WSELW] <= wdata[i * WSELW +: WSELW];
end
end
end
end