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Merge branch 'fpga_synthesis' of https://github.gatech.edu/casl/Vortex into fpga_synthesis

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This commit is contained in:
Blaise Tine 2020-03-30 01:53:53 -04:00
commit 0f39d0fcbd
2 changed files with 4 additions and 4 deletions
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2
rtl/VX_cache/VX_bank.v
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@ -523,7 +523,7 @@ module VX_bank
wire invalidate_fill;
// Enqueue to miss reserv if it's a valid miss
assign miss_add = valid_st2 && miss_st2 && !mrvq_full && !((is_snp_st2 && valid_st2 && ffsq_full) ||((valid_st2 && !miss_st2) && cwbq_full) || (((valid_st2 && miss_st2 && dirty_st2) || fill_saw_dirty_st2) && dwbq_full) || (valid_st2 && miss_st2 && mrvq_full));
assign miss_add = valid_st2 && !is_snp_st2 && miss_st2 && !mrvq_full && !((is_snp_st2 && valid_st2 && ffsq_full) ||((valid_st2 && !miss_st2) && cwbq_full) || (((valid_st2 && miss_st2 && dirty_st2) || fill_saw_dirty_st2) && dwbq_full) || (valid_st2 && miss_st2 && mrvq_full));
assign miss_add_pc = pc_st2;
assign miss_add_addr = addr_st2;
assign miss_add_data = writeword_st2;

6
rtl/VX_define.v
View file

@ -223,7 +223,7 @@
// Snoop Req Queue
`ifndef DSNRQ_SIZE
`define DSNRQ_SIZE 8
`define DSNRQ_SIZE 32
`endif
// Queues for writebacks Knobs {1, 2, 4, 8, ...}
@ -250,7 +250,7 @@
// Fill Forward SNP Queue
`ifndef DFFSQ_SIZE
`define DFFSQ_SIZE 8
`define DFFSQ_SIZE 32
`endif
// Fill Invalidator Size {Fill invalidator must be active}
@ -331,7 +331,7 @@
// Snoop Req Queue
`ifndef ISNRQ_SIZE
`define ISNRQ_SIZE 8
`define ISNRQ_SIZE 32
`endif
// Queues for writebacks Knobs {1, 2, 4, 8, ...}