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csr minor update

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This commit is contained in:
Blaise Tine 2021-03-08 03:46:07 -08:00
parent 8eac091fb5
commit 10a994d11a
6 changed files with 18 additions and 18 deletions
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8
hw/rtl/VX_csr_io_arb.v
View file

@ -24,16 +24,16 @@ module VX_csr_io_arb (
`UNUSED_VAR (clk)
`UNUSED_VAR (reset)
wire [31:0] csr_core_req_mask = csr_core_req_if.use_imm ? 32'(csr_core_req_if.rs1) : csr_core_req_if.rs1_data;
wire [31:0] csr_core_req_data = csr_core_req_if.use_imm ? 32'(csr_core_req_if.rs1) : csr_core_req_if.rs1_data;
// requests
assign csr_pipe_req_if.valid = csr_core_req_if.valid || csr_io_req_if.valid;
assign csr_pipe_req_if.wid = csr_core_req_if.wid;
assign csr_pipe_req_if.tmask = csr_core_req_if.tmask;
assign csr_pipe_req_if.PC = csr_core_req_if.PC;
assign csr_pipe_req_if.op_type = csr_core_req_if.valid ? csr_core_req_if.op_type : (csr_io_req_if.rw ? `CSR_RW : `CSR_RS);
assign csr_pipe_req_if.csr_addr = csr_core_req_if.valid ? csr_core_req_if.csr_addr : csr_io_req_if.addr;
assign csr_pipe_req_if.csr_mask = csr_core_req_if.valid ? csr_core_req_mask : (csr_io_req_if.rw ? csr_io_req_if.data : 32'b0);
assign csr_pipe_req_if.op_type = csr_core_req_if.valid ? csr_core_req_if.op_type : (csr_io_req_if.rw ? `CSR_RW : `CSR_RS);
assign csr_pipe_req_if.addr = csr_core_req_if.valid ? csr_core_req_if.addr : csr_io_req_if.addr;
assign csr_pipe_req_if.data = csr_core_req_if.valid ? csr_core_req_data : (csr_io_req_if.rw ? csr_io_req_if.data : 32'b0);
assign csr_pipe_req_if.rd = csr_core_req_if.rd;
assign csr_pipe_req_if.wb = csr_core_req_if.wb;
assign csr_pipe_req_if.is_io = !csr_core_req_if.valid;

18
hw/rtl/VX_csr_unit.v
View file

@ -63,7 +63,7 @@ module VX_csr_unit #(
.cmt_to_csr_if (cmt_to_csr_if),
.fpu_to_csr_if (fpu_to_csr_if),
.read_enable (csr_pipe_req_if.valid),
.read_addr (csr_pipe_req_if.csr_addr),
.read_addr (csr_pipe_req_if.addr),
.read_wid (csr_pipe_req_if.wid),
.read_data (csr_read_data),
.write_enable (write_enable),
@ -73,7 +73,7 @@ module VX_csr_unit #(
.busy (busy)
);
wire write_hazard = (csr_addr_s1 == csr_pipe_req_if.csr_addr)
wire write_hazard = (csr_addr_s1 == csr_pipe_req_if.addr)
&& (csr_pipe_rsp_if.wid == csr_pipe_req_if.wid)
&& csr_pipe_rsp_if.valid;
@ -87,16 +87,16 @@ module VX_csr_unit #(
csr_we_s0_unqual = 0;
case (csr_pipe_req_if.op_type)
`CSR_RW: begin
csr_updated_data = csr_pipe_req_if.csr_mask;
csr_updated_data = csr_pipe_req_if.data;
csr_we_s0_unqual = 1;
end
`CSR_RS: begin
csr_updated_data = csr_read_data_qual | csr_pipe_req_if.csr_mask;
csr_we_s0_unqual = (csr_pipe_req_if.csr_mask != 0);
csr_updated_data = csr_read_data_qual | csr_pipe_req_if.data;
csr_we_s0_unqual = (csr_pipe_req_if.data != 0);
end
`CSR_RC: begin
csr_updated_data = csr_read_data_qual & (32'hFFFFFFFF - csr_pipe_req_if.csr_mask);
csr_we_s0_unqual = (csr_pipe_req_if.csr_mask != 0);
csr_updated_data = csr_read_data_qual & ~csr_pipe_req_if.data;
csr_we_s0_unqual = (csr_pipe_req_if.data != 0);
end
default: csr_updated_data = 'x;
endcase
@ -115,8 +115,8 @@ module VX_csr_unit #(
.clk (clk),
.reset (reset),
.enable (!stall_out),
.data_in ({pipe_req_valid_qual, csr_pipe_req_if.wid, csr_pipe_req_if.tmask, csr_pipe_req_if.PC, csr_pipe_req_if.rd, csr_pipe_req_if.wb, csr_we_s0_unqual, csr_pipe_req_if.csr_addr, csr_pipe_req_if.is_io, csr_read_data_qual, csr_updated_data}),
.data_out ({csr_pipe_rsp_if.valid, csr_pipe_rsp_if.wid, csr_pipe_rsp_if.tmask, csr_pipe_rsp_if.PC, csr_pipe_rsp_if.rd, csr_pipe_rsp_if.wb, csr_we_s1, csr_addr_s1, select_io_rsp, csr_read_data_s1, csr_updated_data_s1})
.data_in ({pipe_req_valid_qual, csr_pipe_req_if.wid, csr_pipe_req_if.tmask, csr_pipe_req_if.PC, csr_pipe_req_if.rd, csr_pipe_req_if.wb, csr_we_s0_unqual, csr_pipe_req_if.addr, csr_pipe_req_if.is_io, csr_read_data_qual, csr_updated_data}),
.data_out ({csr_pipe_rsp_if.valid, csr_pipe_rsp_if.wid, csr_pipe_rsp_if.tmask, csr_pipe_rsp_if.PC, csr_pipe_rsp_if.rd, csr_pipe_rsp_if.wb, csr_we_s1, csr_addr_s1, select_io_rsp, csr_read_data_s1, csr_updated_data_s1})
);
for (genvar i = 0; i < `NUM_THREADS; i++) begin

2
hw/rtl/VX_instr_demux.v
View file

@ -79,7 +79,7 @@ module VX_instr_demux (
.valid_in (csr_req_valid),
.ready_in (csr_req_ready),
.data_in ({execute_if.wid, execute_if.tmask, execute_if.PC, `CSR_OP(execute_if.op_type), execute_if.imm[`CSR_ADDR_BITS-1:0], execute_if.rd, execute_if.wb, execute_if.use_imm, execute_if.rs1, gpr_rsp_if.rs1_data[0]}),
.data_out ({csr_req_if.wid, csr_req_if.tmask, csr_req_if.PC, csr_req_if.op_type, csr_req_if.csr_addr, csr_req_if.rd, csr_req_if.wb, csr_req_if.use_imm, csr_req_if.rs1, csr_req_if.rs1_data}),
.data_out ({csr_req_if.wid, csr_req_if.tmask, csr_req_if.PC, csr_req_if.op_type, csr_req_if.addr, csr_req_if.rd, csr_req_if.wb, csr_req_if.use_imm, csr_req_if.rs1, csr_req_if.rs1_data}),
.valid_out (csr_req_if.valid),
.ready_out (csr_req_if.ready)
);

2
hw/rtl/VX_issue.v
View file

@ -189,7 +189,7 @@ module VX_issue #(
$display("%t: core%0d-issue: wid=%0d, PC=%0h, ex=LSU, tmask=%b, rd=%0d, baddr=%0h, offset=%0h, data=%0h", $time, CORE_ID, lsu_req_if.wid, lsu_req_if.PC, lsu_req_if.tmask, lsu_req_if.rd, lsu_req_if.base_addr, lsu_req_if.offset, lsu_req_if.store_data);
end
if (csr_req_if.valid && csr_req_if.ready) begin
$display("%t: core%0d-issue: wid=%0d, PC=%0h, ex=CSR, tmask=%b, rd=%0d, addr=%0h, rs1_data=%0h", $time, CORE_ID, csr_req_if.wid, csr_req_if.PC, csr_req_if.tmask, csr_req_if.rd, csr_req_if.csr_addr, csr_req_if.rs1_data);
$display("%t: core%0d-issue: wid=%0d, PC=%0h, ex=CSR, tmask=%b, rd=%0d, addr=%0h, rs1_data=%0h", $time, CORE_ID, csr_req_if.wid, csr_req_if.PC, csr_req_if.tmask, csr_req_if.rd, csr_req_if.addr, csr_req_if.rs1_data);
end
if (fpu_req_if.valid && fpu_req_if.ready) begin
$display("%t: core%0d-issue: wid=%0d, PC=%0h, ex=FPU, tmask=%b, rd=%0d, rs1_data=%0h, rs2_data=%0h, rs3_data=%0h", $time, CORE_ID, fpu_req_if.wid, fpu_req_if.PC, fpu_req_if.tmask, fpu_req_if.rd, fpu_req_if.rs1_data, fpu_req_if.rs2_data, fpu_req_if.rs3_data);

4
hw/rtl/interfaces/VX_csr_pipe_req_if.v
View file

@ -10,8 +10,8 @@ interface VX_csr_pipe_req_if ();
wire [`NUM_THREADS-1:0] tmask;
wire [31:0] PC;
wire [`CSR_BITS-1:0] op_type;
wire [`CSR_ADDR_BITS-1:0] csr_addr;
wire [31:0] csr_mask;
wire [`CSR_ADDR_BITS-1:0] addr;
wire [31:0] data;
wire [`NR_BITS-1:0] rd;
wire wb;
wire is_io;

2
hw/rtl/interfaces/VX_csr_req_if.v
View file

@ -10,7 +10,7 @@ interface VX_csr_req_if ();
wire [`NUM_THREADS-1:0] tmask;
wire [31:0] PC;
wire [`CSR_BITS-1:0] op_type;
wire [`CSR_ADDR_BITS-1:0] csr_addr;
wire [`CSR_ADDR_BITS-1:0] addr;
wire [31:0] rs1_data;
wire use_imm;
wire [`NR_BITS-1:0] rs1;