mirror of
https://github.com/vortexgpgpu/vortex.git
synced 2025-04-23 21:39:10 -04:00
adding CSR support to rtlsim driver
This commit is contained in:
Blaise Tine
parent
dccea80b68
commit
112d8ab815
10 changed files with 167 additions and 42 deletions
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@ -91,22 +91,22 @@ extern int vx_upload_kernel_file(vx_device_h device, const char* filename) {
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return err;
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}
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extern int vx_get_perf(vx_device_h device, size_t* cycles, size_t* instrs) {
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extern int vx_get_perf(vx_device_h device, int core_id, size_t* cycles, size_t* instrs) {
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int ret = 0;
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unsigned value;
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if (cycles) {
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ret |= vx_csr_get(device, 0, CSR_CYCLE_H, &value);
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ret |= vx_csr_get(device, core_id, CSR_CYCLE_H, &value);
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*cycles = value;
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ret |= vx_csr_get(device, 0, CSR_CYCLE, &value);
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ret |= vx_csr_get(device, core_id, CSR_CYCLE, &value);
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*cycles = (*cycles << 32) | value;
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}
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if (instrs) {
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ret |= vx_csr_get(device, 0, CSR_INSTRET_H, &value);
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ret |= vx_csr_get(device, core_id, CSR_INSTRET_H, &value);
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*instrs = value;
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ret |= vx_csr_get(device, 0, CSR_INSTRET, &value);
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ret |= vx_csr_get(device, core_id, CSR_INSTRET, &value);
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*instrs = (*instrs << 32) | value;
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}
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@ -58,10 +58,10 @@ int vx_start(vx_device_h hdevice);
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int vx_ready_wait(vx_device_h hdevice, long long timeout);
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// set device constant registers
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int vx_csr_set(vx_device_h hdevice, int core, int address, unsigned value);
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int vx_csr_set(vx_device_h hdevice, int core_id, int addr, unsigned value);
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// get device constant registers
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int vx_csr_get(vx_device_h hdevice, int core, int address, unsigned* value);
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int vx_csr_get(vx_device_h hdevice, int core_id, int addr, unsigned* value);
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////////////////////////////// UTILITY FUNCIONS ///////////////////////////////
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@ -72,7 +72,7 @@ int vx_upload_kernel_bytes(vx_device_h device, const void* content, size_t size)
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int vx_upload_kernel_file(vx_device_h device, const char* filename);
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// get performance counters
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int vx_get_perf(vx_device_h device, size_t* cycles, size_t* instrs);
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int vx_get_perf(vx_device_h device, int core_id, size_t* cycles, size_t* instrs);
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#ifdef __cplusplus
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}
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@ -17,6 +17,9 @@ CXXFLAGS +=-fstack-protector
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# Position independent code
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CXXFLAGS += -fPIC
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# Dump perf stats
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CXXFLAGS += -DDUMP_PERF_STATS
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# Enable scope analyzer
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#CXXFLAGS += -DSCOPE
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@ -211,14 +211,29 @@ extern int vx_dev_close(vx_device_h hdevice) {
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vx_scope_stop(device->fpga, 0);
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#endif
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{
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// Dump perf stats
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#ifdef DUMP_PERF_STATS
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// Dump perf stats
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if (device->num_cores > 1) {
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uint64_t total_instrs = 0, total_cycles = 0;
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for (unsigned core_id = 0; core_id < device->num_cores; ++core_id) {
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uint64_t instrs, cycles;
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int ret = vx_get_perf(hdevice, core_id, &instrs, &cycles);
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assert(ret == 0);
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float IPC = (float)(double(instrs) / double(cycles));
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fprintf(stdout, "PERF: core%d: instrs=%ld, cycles=%ld, IPC=%f\n", core_id, instrs, cycles, IPC);
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total_instrs += instrs;
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total_cycles = std::max<uint64_t>(total_cycles, cycles);
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}
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float IPC = (float)(double(total_instrs) / double(total_cycles));
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fprintf(stdout, "PERF: instrs=%ld, cycles=%ld, IPC=%f\n", total_instrs, total_cycles, IPC);
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} else {
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uint64_t instrs, cycles;
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int ret = vx_get_perf(hdevice, &instrs, &cycles);
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int ret = vx_get_perf(hdevice, 0, &instrs, &cycles);
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float IPC = (float)(double(instrs) / double(cycles));
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fprintf(stdout, "PERF: instrs=%ld, cycles=%ld, IPC=%f\n", instrs, cycles, IPC);
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assert(ret == 0);
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fprintf(stdout, "PERF: instrs=%ld, cycles=%ld, IPC=%f\n", instrs, cycles, IPC);
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}
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#endif
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fpgaClose(device->fpga);
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@ -480,7 +495,7 @@ extern int vx_start(vx_device_h hdevice) {
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}
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// set device constant registers
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extern int vx_csr_set(vx_device_h hdevice, int core, int address, unsigned value) {
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extern int vx_csr_set(vx_device_h hdevice, int core_id, int addr, unsigned value) {
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if (nullptr == hdevice)
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return -1;
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@ -491,8 +506,8 @@ extern int vx_csr_set(vx_device_h hdevice, int core, int address, unsigned value
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return -1;
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// write CSR value
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CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_CSR_CORE, core));
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CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_CSR_ADDR, address));
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CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_CSR_CORE, core_id));
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CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_CSR_ADDR, addr));
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CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_CSR_DATA, value));
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CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_CMD_TYPE, CMD_CSR_WRITE));
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@ -500,7 +515,7 @@ extern int vx_csr_set(vx_device_h hdevice, int core, int address, unsigned value
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}
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// get device constant registers
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extern int vx_csr_get(vx_device_h hdevice, int core, int address, unsigned* value) {
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extern int vx_csr_get(vx_device_h hdevice, int core_id, int addr, unsigned* value) {
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if (nullptr == hdevice || nullptr == value)
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return -1;
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@ -512,8 +527,8 @@ extern int vx_csr_get(vx_device_h hdevice, int core, int address, unsigned* valu
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// write CSR value
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CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_CSR_CORE, core));
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CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_CSR_ADDR, address));
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CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_CSR_CORE, core_id));
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CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_CSR_ADDR, addr));
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CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_CMD_TYPE, CMD_CSR_READ));
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// Ensure ready for new command
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@ -28,6 +28,8 @@ CFLAGS += -fPIC
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CFLAGS += -DUSE_RTLSIM $(CONFIGS)
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CFLAGS += -DDUMP_PERF_STATS
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LDFLAGS += -shared -pthread
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# LDFLAGS += -dynamiclib -pthread
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@ -69,7 +69,28 @@ public:
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}
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~vx_device() {
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simulator_.print_stats(std::cout);
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#ifdef DUMP_PERF_STATS
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unsigned num_cores;
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this->get_csr(0, CSR_NC, &num_cores);
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if (num_cores > 1) {
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uint64_t total_instrs = 0, total_cycles = 0;
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for (unsigned core_id = 0; core_id < num_cores; ++core_id) {
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uint64_t instrs, cycles;
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vx_get_perf(this, core_id, &instrs, &cycles);
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float IPC = (float)(double(instrs) / double(cycles));
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fprintf(stdout, "PERF: core%d: instrs=%ld, cycles=%ld, IPC=%f\n", core_id, instrs, cycles, IPC);
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total_instrs += instrs;
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total_cycles = std::max<uint64_t>(total_cycles, cycles);
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}
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float IPC = (float)(double(total_instrs) / double(total_cycles));
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fprintf(stdout, "PERF: instrs=%ld, cycles=%ld, IPC=%f\n", total_instrs, total_cycles, IPC);
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} else {
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uint64_t instrs, cycles;
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vx_get_perf(this, 0, &instrs, &cycles);
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float IPC = (float)(double(instrs) / double(cycles));
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fprintf(stdout, "PERF: instrs=%ld, cycles=%ld, IPC=%f\n", instrs, cycles, IPC);
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}
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#endif
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if (future_.valid()) {
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future_.wait();
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}
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@ -152,6 +173,28 @@ public:
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return 0;
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}
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int set_csr(int core_id, int addr, unsigned value) {
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if (future_.valid()) {
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future_.wait(); // ensure prior run completed
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}
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simulator_.set_csr(core_id, addr, value);
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while (simulator_.is_busy()) {
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simulator_.step();
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};
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return 0;
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}
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int get_csr(int core_id, int addr, unsigned *value) {
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if (future_.valid()) {
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future_.wait(); // ensure prior run completed
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}
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simulator_.get_csr(core_id, addr, value);
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while (simulator_.is_busy()) {
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simulator_.step();
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};
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return 0;
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}
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private:
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size_t mem_allocation_;
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@ -324,10 +367,20 @@ extern int vx_ready_wait(vx_device_h hdevice, long long timeout) {
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return device->wait(timeout);
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}
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extern int vx_csr_set(vx_device_h /*hdevice*/, int /*core*/, int /*address*/, unsigned /*value*/) {
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return -1;
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extern int vx_csr_set(vx_device_h hdevice, int core_id, int addr, unsigned value) {
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if (nullptr == hdevice)
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return -1;
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vx_device *device = ((vx_device*)hdevice);
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return device->set_csr(core_id, addr, value);
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}
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extern int vx_csr_get(vx_device_h /*hdevice*/, int /*core*/, int /*address*/, unsigned* /*value*/) {
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return -1;
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extern int vx_csr_get(vx_device_h hdevice, int core_id, int addr, unsigned* value) {
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if (nullptr == hdevice)
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return -1;
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vx_device *device = ((vx_device*)hdevice);
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return device->get_csr(core_id, addr, value);
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}
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@ -358,10 +358,10 @@ extern int vx_ready_wait(vx_device_h hdevice, long long timeout) {
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return device->wait(timeout);
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}
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extern int vx_csr_set(vx_device_h /*hdevice*/, int /*core*/, int /*address*/, unsigned /*value*/) {
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extern int vx_csr_set(vx_device_h /*hdevice*/, int /*core_id*/, int /*addr*/, unsigned /*value*/) {
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return -1;
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}
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extern int vx_csr_get(vx_device_h /*hdevice*/, int /*core*/, int /*address*/, unsigned* /*value*/) {
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extern int vx_csr_get(vx_device_h /*hdevice*/, int /*core_id*/, int /*addr*/, unsigned* /*value*/) {
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return -1;
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}
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@ -48,10 +48,10 @@ extern int vx_ready_wait(vx_device_h /*hdevice*/, long long /*timeout*/) {
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return -1;
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}
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extern int vx_csr_set(vx_device_h /*hdevice*/, int /*core*/, int /*address*/, unsigned /*value*/) {
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extern int vx_csr_set(vx_device_h /*hdevice*/, int /*core_id*/, int /*addr*/, unsigned /*value*/) {
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return -1;
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}
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extern int vx_csr_get(vx_device_h /*hdevice*/, int /*core*/, int /*address*/, unsigned* /*value*/) {
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extern int vx_csr_get(vx_device_h /*hdevice*/, int /*core_id*/, int /*addr*/, unsigned* /*value*/) {
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return -1;
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}
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@ -22,6 +22,7 @@ Simulator::Simulator() {
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dram_rsp_active_ = false;
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snp_req_active_ = false;
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csr_req_active_ = false;
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#ifdef VCD_OUTPUT
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Verilated::traceEverOn(true);
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@ -163,15 +164,6 @@ void Simulator::eval_io_bus() {
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vortex_->io_rsp_valid = 0;
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}
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void Simulator::eval_csr_bus() {
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vortex_->csr_io_req_valid = 0;
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vortex_->csr_io_req_coreid = 0;
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vortex_->csr_io_req_addr = 0;
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vortex_->csr_io_req_rw = 0;
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vortex_->csr_io_req_data = 0;
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vortex_->csr_io_rsp_ready = 1;
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}
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void Simulator::eval_snp_bus() {
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if (snp_req_active_) {
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if (vortex_->snp_rsp_valid) {
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@ -204,6 +196,27 @@ void Simulator::eval_snp_bus() {
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}
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}
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void Simulator::eval_csr_bus() {
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if (csr_req_active_) {
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if (vortex_->csr_io_req_rw) {
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if (vortex_->csr_io_req_ready) {
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vortex_->snp_req_valid = 0;
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csr_req_active_ = false;
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}
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} else {
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if (vortex_->csr_io_rsp_valid) {
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*csr_rsp_value_ = vortex_->csr_io_rsp_data;
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vortex_->snp_req_valid = 0;
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vortex_->csr_io_rsp_ready = 0;
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csr_req_active_ = false;
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}
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}
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} else {
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vortex_->csr_io_req_valid = 0;
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vortex_->csr_io_rsp_ready = 0;
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}
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}
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void Simulator::wait(uint32_t cycles) {
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for (int i = 0; i < cycles; ++i) {
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this->step();
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@ -211,7 +224,9 @@ void Simulator::wait(uint32_t cycles) {
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}
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bool Simulator::is_busy() const {
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return vortex_->busy || snp_req_active_;
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return vortex_->busy
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|| snp_req_active_
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|| csr_req_active_;
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}
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void Simulator::flush_caches(uint32_t mem_addr, uint32_t size) {
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@ -221,22 +236,52 @@ void Simulator::flush_caches(uint32_t mem_addr, uint32_t size) {
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if (0 == size)
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return;
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snp_req_active_ = true;
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snp_req_size_ = (size + GLOBAL_BLOCK_SIZE - 1) / GLOBAL_BLOCK_SIZE;
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vortex_->snp_req_addr = mem_addr / GLOBAL_BLOCK_SIZE;
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vortex_->snp_req_tag = 0;
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vortex_->snp_req_valid = 1;
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vortex_->snp_rsp_ready = 1;
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snp_req_size_ = (size + GLOBAL_BLOCK_SIZE - 1) / GLOBAL_BLOCK_SIZE;
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--snp_req_size_;
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pending_snp_reqs_ = 1;
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snp_req_active_ = true;
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#ifdef DBG_PRINT_CACHE_SNP
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std::cout << timestamp << ": [sim] snp req: addr=" << std::hex << vortex_->snp_req_addr << std::dec << " tag=" << vortex_->snp_req_tag << " remain=" << snp_req_size_ << std::endl;
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#endif
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}
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void Simulator::set_csr(int core_id, int addr, unsigned value) {
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#ifndef NDEBUG
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std::cout << timestamp << ": [sim] set_csr()" << std::endl;
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#endif
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vortex_->csr_io_req_valid = 1;
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vortex_->csr_io_req_coreid = core_id;
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vortex_->csr_io_req_addr = addr;
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vortex_->csr_io_req_rw = 1;
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vortex_->csr_io_req_data = value;
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vortex_->csr_io_rsp_ready = 0;
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csr_req_active_ = true;
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}
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void Simulator::get_csr(int core_id, int addr, unsigned *value) {
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#ifndef NDEBUG
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std::cout << timestamp << ": [sim] get_csr()" << std::endl;
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#endif
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vortex_->csr_io_req_valid = 1;
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vortex_->csr_io_req_coreid = core_id;
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vortex_->csr_io_req_addr = addr;
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vortex_->csr_io_req_rw = 0;
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vortex_->csr_io_rsp_ready = 1;
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csr_rsp_value_ = value;
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csr_req_active_ = true;
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}
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void Simulator::run() {
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#ifndef NDEBUG
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std::cout << timestamp << ": [sim] run()" << std::endl;
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@ -31,6 +31,8 @@ public:
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Simulator();
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virtual ~Simulator();
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void attach_ram(RAM* ram);
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void load_bin(const char* program_file);
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void load_ihex(const char* program_file);
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@ -39,12 +41,14 @@ public:
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void reset();
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void step();
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void wait(uint32_t cycles);
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void flush_caches(uint32_t mem_addr, uint32_t size);
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void attach_ram(RAM* ram);
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void set_csr(int core_id, int addr, unsigned value);
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void get_csr(int core_id, int addr, unsigned *value);
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void run();
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int get_last_wb_value(int reg) const;
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void print_stats(std::ostream& out);
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|
||||
private:
|
||||
|
|
@ -60,8 +64,11 @@ private:
|
|||
int dram_rsp_active_;
|
||||
|
||||
bool snp_req_active_;
|
||||
bool csr_req_active_;
|
||||
|
||||
uint32_t snp_req_size_;
|
||||
uint32_t pending_snp_reqs_;
|
||||
uint32_t* csr_rsp_value_;
|
||||
|
||||
RAM *ram_;
|
||||
VVortex *vortex_;
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue