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reset relay refactoring

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This commit is contained in:
Blaise Tine 2022-05-27 02:43:58 -04:00
parent 69836dc225
commit 12a68b6af8
22 changed files with 125 additions and 140 deletions
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22
hw/rtl/VX_cluster.sv
View file

@ -27,7 +27,7 @@ module VX_cluster #(
// simulation helper signals
output wire sim_ebreak,
output wire [`NUM_REGS-1:0][31:0] sim_last_wb_value,
output wire [`NUM_REGS-1:0][31:0] sim_wb_value,
// Status
output wire busy
@ -60,7 +60,7 @@ module VX_cluster #(
.TAG_WIDTH (`RCACHE_TAG_WIDTH)
) rcache_rsp_if();
`RESET_RELAY (raster_reset);
`RESET_RELAY (raster_reset, reset);
VX_raster_unit #(
.CLUSTER_ID (CLUSTER_ID),
@ -187,7 +187,7 @@ module VX_cluster #(
.TAG_WIDTH (`OCACHE_TAG_WIDTH)
) ocache_rsp_if();
`RESET_RELAY (rop_reset);
`RESET_RELAY (rop_reset, reset);
VX_rop_unit #(
.CLUSTER_ID (CLUSTER_ID),
@ -285,11 +285,11 @@ module VX_cluster #(
`endif
wire [`NUM_CORES-1:0] per_core_sim_ebreak;
wire [`NUM_CORES-1:0][`NUM_REGS-1:0][31:0] per_core_sim_last_wb_value;
wire [`NUM_CORES-1:0][`NUM_REGS-1:0][31:0] per_core_sim_wb_value;
assign sim_ebreak = per_core_sim_ebreak[0];
assign sim_last_wb_value = per_core_sim_last_wb_value[0];
assign sim_wb_value = per_core_sim_wb_value[0];
`UNUSED_VAR (per_core_sim_ebreak)
`UNUSED_VAR (per_core_sim_last_wb_value)
`UNUSED_VAR (per_core_sim_wb_value)
VX_mem_req_if #(
.DATA_WIDTH (`DCACHE_MEM_DATA_WIDTH),
@ -307,7 +307,7 @@ module VX_cluster #(
// Generate all cores
for (genvar i = 0; i < `NUM_CORES; i++) begin
`RESET_RELAY (core_reset);
`RESET_RELAY (core_reset, reset);
VX_core #(
.CORE_ID ((CLUSTER_ID * `NUM_CORES) + i)
@ -341,7 +341,7 @@ module VX_cluster #(
.mem_rsp_if (per_core_mem_rsp_if[i]),
.sim_ebreak (per_core_sim_ebreak[i]),
.sim_last_wb_value (per_core_sim_last_wb_value[i]),
.sim_wb_value (per_core_sim_wb_value[i]),
.busy (per_core_busy[i])
);
@ -366,7 +366,7 @@ module VX_cluster #(
VX_perf_cache_if perf_l2cache_if();
`endif
`RESET_RELAY (l2_reset);
`RESET_RELAY (l2_reset, reset);
VX_cache_wrap #(
.CACHE_ID (`L2_CACHE_ID),
@ -405,8 +405,6 @@ module VX_cluster #(
`else
`RESET_RELAY (mem_arb_reset);
VX_mem_mux #(
.NUM_REQS (`NUM_CORES),
.DATA_WIDTH (`DCACHE_MEM_DATA_WIDTH),
@ -417,7 +415,7 @@ module VX_cluster #(
.BUFFERED_RSP ((`NUM_CORES > 1) ? 1 : 0)
) mem_mux_core (
.clk (clk),
.reset (mem_arb_reset),
.reset (reset),
.req_in_if (per_core_mem_req_if),
.rsp_in_if (per_core_mem_rsp_if),
.req_out_if (l2_mem_req_if),

4
hw/rtl/VX_commit.sv
View file

@ -21,7 +21,7 @@ module VX_commit #(
VX_cmt_to_csr_if.master cmt_to_csr_if,
// simulation helper signals
output reg [`NUM_REGS-1:0][31:0] sim_last_wb_value
output reg [`NUM_REGS-1:0][31:0] sim_wb_value
);
localparam NUM_RSPS = 5 + `EXT_F_ENABLED;
localparam COMMIT_SIZEW = $clog2(NUM_RSPS * `NUM_THREADS + 1);
@ -105,7 +105,7 @@ module VX_commit #(
.gpu_commit_if (gpu_commit_if),
.writeback_if (writeback_if),
.sim_last_wb_value (sim_last_wb_value)
.sim_wb_value (sim_wb_value)
);
// store and gpu commits don't writeback

4
hw/rtl/VX_core.sv
View file

@ -35,7 +35,7 @@ module VX_core #(
// simulation helper signals
output wire sim_ebreak,
output wire [`NUM_REGS-1:0][31:0] sim_last_wb_value,
output wire [`NUM_REGS-1:0][31:0] sim_wb_value,
// Status
output wire busy
@ -130,7 +130,7 @@ module VX_core #(
`endif
.sim_ebreak (sim_ebreak),
.sim_last_wb_value (sim_last_wb_value),
.sim_wb_value (sim_wb_value),
// Status
.busy (busy)

13
hw/rtl/VX_decode.sv
View file

@ -23,12 +23,12 @@ module VX_decode #(
`endif
// inputs
VX_ifetch_rsp_if.slave ifetch_rsp_if,
VX_ifetch_rsp_if.slave ifetch_rsp_if,
// outputs
VX_decode_if.master decode_if,
VX_wstall_if.master wstall_if,
VX_join_if.master join_if
VX_decode_if.master decode_if,
VX_wrelease_if.master wrelease_if,
VX_join_if.master join_if
);
`UNUSED_PARAM (CORE_ID)
`UNUSED_VAR (clk)
@ -481,9 +481,8 @@ module VX_decode #(
assign join_if.valid = ifetch_rsp_fire && is_join;
assign join_if.wid = ifetch_rsp_if.wid;
assign wstall_if.valid = ifetch_rsp_fire;
assign wstall_if.wid = ifetch_rsp_if.wid;
assign wstall_if.stalled = is_wstall;
assign wrelease_if.valid = ifetch_rsp_fire && ~is_wstall;
assign wrelease_if.wid = ifetch_rsp_if.wid;
assign ifetch_rsp_if.ibuf_pop = decode_if.ibuf_pop;
assign ifetch_rsp_if.ready = decode_if.ready;

10
hw/rtl/VX_execute.sv
View file

@ -93,10 +93,10 @@ module VX_execute #(
VX_fpu_to_csr_if fpu_to_csr_if();
`endif
`RESET_RELAY (alu_reset);
`RESET_RELAY (lsu_reset);
`RESET_RELAY (csr_reset);
`RESET_RELAY (gpu_reset);
`RESET_RELAY (alu_reset, reset);
`RESET_RELAY (lsu_reset, reset);
`RESET_RELAY (csr_reset, reset);
`RESET_RELAY (gpu_reset, reset);
VX_alu_unit #(
.CORE_ID(CORE_ID)
@ -166,7 +166,7 @@ module VX_execute #(
);
`ifdef EXT_F_ENABLE
`RESET_RELAY (fpu_reset);
`RESET_RELAY (fpu_reset, reset);
VX_fpu_unit #(
.CORE_ID(CORE_ID)

8
hw/rtl/VX_fetch.sv
View file

@ -13,7 +13,7 @@ module VX_fetch #(
VX_cache_rsp_if.slave icache_rsp_if,
// inputs
VX_wstall_if.slave wstall_if,
VX_wrelease_if.slave wrelease_if,
VX_join_if.slave join_if,
VX_branch_ctl_if.slave branch_ctl_if,
VX_warp_ctl_if.slave warp_ctl_if,
@ -24,7 +24,7 @@ module VX_fetch #(
// csr interface
VX_fetch_to_csr_if.master fetch_to_csr_if,
// busy status
// Status
output wire busy
);
@ -39,14 +39,14 @@ module VX_fetch #(
.reset (reset),
.warp_ctl_if (warp_ctl_if),
.wstall_if (wstall_if),
.wrelease_if (wrelease_if),
.join_if (join_if),
.branch_ctl_if (branch_ctl_if),
.ifetch_req_if (ifetch_req_if),
.fetch_to_csr_if (fetch_to_csr_if),
.busy (busy)
);

16
hw/rtl/VX_issue.sv
View file

@ -83,10 +83,10 @@ module VX_issue #(
// issue the instruction
assign ibuffer_if.ready = scoreboard_if.ready && dispatch_if.ready;
`RESET_RELAY (ibuf_reset);
`RESET_RELAY (scoreboard_reset);
`RESET_RELAY (gpr_reset);
`RESET_RELAY (dispatch_reset);
`RESET_RELAY (ibuf_reset, reset);
`RESET_RELAY (scoreboard_reset, reset);
`RESET_RELAY (gpr_reset, reset);
`RESET_RELAY (dispatch_reset, reset);
VX_ibuffer #(
.CORE_ID(CORE_ID)
@ -142,16 +142,16 @@ module VX_issue #(
$time, CORE_ID, ibuffer_if.wid, ibuffer_if.PC, ibuffer_if.tmask, ibuffer_if.rd, ibuffer_if.wb, timeout_ctr,
in_use_regs[0], in_use_regs[1], in_use_regs[2], in_use_regs[3], ~dispatch_if.ready, ibuffer_if.uuid));
`endif
`ASSERT(timeout_ctr < `STALL_TIMEOUT,
("%t: *** core%0d-issue-timeout: wid=%0d, PC=0x%0h, tmask=%b, rd=%0d, wb=%0d, inuse=%b%b%b%b, dispatch=%b (#%0d)",
$time, CORE_ID, ibuffer_if.wid, ibuffer_if.PC, ibuffer_if.tmask, ibuffer_if.rd, ibuffer_if.wb,
in_use_regs[0], in_use_regs[1], in_use_regs[2], in_use_regs[3], ~dispatch_if.ready, ibuffer_if.uuid));
timeout_ctr <= timeout_ctr + 1;
end else if (ibuffer_if.valid && ibuffer_if.ready) begin
timeout_ctr <= 0;
end
end
end
`RUNTIME_ASSERT(timeout_ctr < `STALL_TIMEOUT,
("%t: *** core%0d-issue-timeout: wid=%0d, PC=0x%0h, tmask=%b, rd=%0d, wb=%0d, inuse=%b%b%b%b, dispatch=%b (#%0d)",
$time, CORE_ID, ibuffer_if.wid, ibuffer_if.PC, ibuffer_if.tmask, ibuffer_if.rd, ibuffer_if.wb,
in_use_regs[0], in_use_regs[1], in_use_regs[2], in_use_regs[3], ~dispatch_if.ready, ibuffer_if.uuid));
`SCOPE_ASSIGN (issue_fire, ibuffer_if.valid && ibuffer_if.ready);
`SCOPE_ASSIGN (issue_uuid, ibuffer_if.uuid);

11
hw/rtl/VX_mem_unit.sv
View file

@ -67,7 +67,7 @@ module VX_mem_unit # (
`CACHE_REQ_TO_MEM (icache_req_qual_if, icache_req_if, i);
end
`RESET_RELAY (icache_reset);
`RESET_RELAY (icache_reset, reset);
VX_cache_wrap #(
.CACHE_ID (`ICACHE_ID),
@ -146,7 +146,7 @@ module VX_mem_unit # (
`CACHE_REQ_TO_MEM (dcache_nosm_req_qual_if, dcache_nosm_req_if, i);
end
`RESET_RELAY (dcache_reset);
`RESET_RELAY (dcache_reset, reset);
VX_cache_wrap #(
.CACHE_ID (`DCACHE_ID),
@ -204,8 +204,7 @@ module VX_mem_unit # (
.TAG_WIDTH (`DCACHE_NOSM_TAG_WIDTH)
) smem_rsp_if();
`RESET_RELAY (smem_arb_reset);
`RESET_RELAY (smem_reset);
`RESET_RELAY (smem_reset, reset);
VX_cache_req_if #(
.NUM_REQS (`DCACHE_NUM_REQS),
@ -230,7 +229,7 @@ module VX_mem_unit # (
.BUFFERED_RSP (1)
) dcache_nosm_demux (
.clk (clk),
.reset (smem_arb_reset),
.reset (reset),
.req_in_if (dcache_req_if),
.rsp_in_if (dcache_rsp_if),
.req_out_if (dcache_nosm_demux_req_if),
@ -349,7 +348,7 @@ module VX_mem_unit # (
`CACHE_REQ_TO_MEM (tcache_req_qual_if, tcache_req_if, i);
end
`RESET_RELAY (tcache_reset);
`RESET_RELAY (tcache_reset, reset);
VX_cache_wrap #(
.CACHE_ID (`TCACHE_ID),

60
hw/rtl/VX_pipeline.sv
View file

@ -6,53 +6,53 @@ module VX_pipeline #(
`SCOPE_IO_VX_pipeline
// Clock
input wire clk,
input wire reset,
input wire clk,
input wire reset,
// Dcache interface
VX_cache_req_if.master dcache_req_if,
VX_cache_rsp_if.slave dcache_rsp_if,
VX_cache_req_if.master dcache_req_if,
VX_cache_rsp_if.slave dcache_rsp_if,
// Icache interface
VX_cache_req_if.master icache_req_if,
VX_cache_rsp_if.slave icache_rsp_if,
VX_cache_req_if.master icache_req_if,
VX_cache_rsp_if.slave icache_rsp_if,
VX_dcr_base_if.slave dcr_base_if,
VX_dcr_base_if.slave dcr_base_if,
`ifdef EXT_TEX_ENABLE
VX_tex_dcr_if.slave tex_dcr_if,
VX_cache_req_if.master tcache_req_if,
VX_cache_rsp_if.slave tcache_rsp_if,
VX_tex_dcr_if.slave tex_dcr_if,
VX_cache_req_if.master tcache_req_if,
VX_cache_rsp_if.slave tcache_rsp_if,
`ifdef PERF_ENABLE
VX_perf_cache_if.slave perf_tcache_if,
VX_perf_cache_if.slave perf_tcache_if,
`endif
`endif
`ifdef EXT_RASTER_ENABLE
VX_raster_req_if raster_req_if,
VX_raster_req_if raster_req_if,
`ifdef PERF_ENABLE
VX_raster_perf_if.slave raster_perf_if,
VX_perf_cache_if.slave perf_rcache_if,
VX_raster_perf_if.slave raster_perf_if,
VX_perf_cache_if.slave perf_rcache_if,
`endif
`endif
`ifdef EXT_ROP_ENABLE
VX_rop_req_if rop_req_if,
VX_rop_req_if rop_req_if,
`ifdef PERF_ENABLE
VX_rop_perf_if.slave rop_perf_if,
VX_perf_cache_if.slave perf_ocache_if,
VX_rop_perf_if.slave rop_perf_if,
VX_perf_cache_if.slave perf_ocache_if,
`endif
`endif
`ifdef PERF_ENABLE
VX_perf_memsys_if.slave perf_memsys_if,
VX_perf_memsys_if.slave perf_memsys_if,
`endif
// simulation helper signals
output wire sim_ebreak,
output wire [`NUM_REGS-1:0][31:0] sim_last_wb_value,
output wire sim_ebreak,
output wire [`NUM_REGS-1:0][31:0] sim_wb_value,
// Status
output wire busy
output wire busy
);
VX_fetch_to_csr_if fetch_to_csr_if();
VX_cmt_to_csr_if cmt_to_csr_if();
@ -68,7 +68,7 @@ module VX_pipeline #(
`endif
VX_gpu_req_if gpu_req_if();
VX_writeback_if writeback_if();
VX_wstall_if wstall_if();
VX_wrelease_if wrelease_if();
VX_join_if join_if();
VX_commit_if alu_commit_if();
VX_commit_if ld_commit_if();
@ -83,11 +83,11 @@ module VX_pipeline #(
VX_perf_pipeline_if perf_pipeline_if();
`endif
`RESET_RELAY (fetch_reset);
`RESET_RELAY (decode_reset);
`RESET_RELAY (issue_reset);
`RESET_RELAY (execute_reset);
`RESET_RELAY (commit_reset);
`RESET_RELAY (fetch_reset, reset);
`RESET_RELAY (decode_reset, reset);
`RESET_RELAY (issue_reset, reset);
`RESET_RELAY (execute_reset, reset);
`RESET_RELAY (commit_reset, reset);
VX_fetch #(
.CORE_ID(CORE_ID)
@ -97,7 +97,7 @@ module VX_pipeline #(
.reset (fetch_reset),
.icache_req_if (icache_req_if),
.icache_rsp_if (icache_rsp_if),
.wstall_if (wstall_if),
.wrelease_if (wrelease_if),
.join_if (join_if),
.warp_ctl_if (warp_ctl_if),
.branch_ctl_if (branch_ctl_if),
@ -116,7 +116,7 @@ module VX_pipeline #(
`endif
.ifetch_rsp_if (ifetch_rsp_if),
.decode_if (decode_if),
.wstall_if (wstall_if),
.wrelease_if (wrelease_if),
.join_if (join_if)
);
@ -228,7 +228,7 @@ module VX_pipeline #(
.writeback_if (writeback_if),
.cmt_to_csr_if (cmt_to_csr_if),
.sim_last_wb_value (sim_last_wb_value)
.sim_wb_value (sim_wb_value)
);
endmodule

20
hw/rtl/VX_platform.vh
View file

@ -131,20 +131,12 @@
end \
`TRACE(lvl, ("}"))
`define RESET_RELAY(signal) \
wire signal; \
VX_reset_relay __``signal ( \
.clk (clk), \
.reset (reset), \
.reset_o (signal) \
)
`define START_RELAY(signal) \
wire signal; \
VX_reset_relay __``signal ( \
.clk (clk), \
.reset (reset || start), \
.reset_o (signal) \
`define RESET_RELAY(signal, rst) \
wire signal; \
VX_reset_relay __``signal ( \
.clk (clk), \
.reset (rst), \
.reset_o (signal) \
)
`define POP_COUNT(out, in) \

20
hw/rtl/VX_warp_sched.sv
View file

@ -9,7 +9,7 @@ module VX_warp_sched #(
input wire reset,
VX_warp_ctl_if.slave warp_ctl_if,
VX_wstall_if.slave wstall_if,
VX_wrelease_if.slave wrelease_if,
VX_join_if.slave join_if,
VX_branch_ctl_if.slave branch_ctl_if,
@ -17,6 +17,7 @@ module VX_warp_sched #(
VX_fetch_to_csr_if.master fetch_to_csr_if,
// Status
output wire busy
);
@ -131,8 +132,8 @@ module VX_warp_sched #(
warp_pcs[ifetch_req_if.wid] <= ifetch_req_if.PC + 4;
end
if (wstall_if.valid) begin
stalled_warps[wstall_if.wid] <= wstall_if.stalled;
if (wrelease_if.valid) begin
stalled_warps[wrelease_if.wid] <= 0;
end
// join handling
@ -253,18 +254,23 @@ module VX_warp_sched #(
assign busy = (active_warps != 0);
reg [31:0] timeout_ctr;
reg timeout_enable;
always @(posedge clk) begin
if (reset) begin
timeout_ctr <= 0;
end else begin
if (active_warps !=0 && active_warps == stalled_warps) begin
`ASSERT(timeout_ctr < `STALL_TIMEOUT, ("%t: *** core%0d-scheduler-timeout: stalled_warps=%b", $time, CORE_ID, stalled_warps));
timeout_ctr <= 0;
timeout_enable <= 0;
end else begin
if (wrelease_if.valid) begin
timeout_enable <= 1;
end
if (timeout_enable && active_warps !=0 && active_warps == stalled_warps) begin
timeout_ctr <= timeout_ctr + 1;
end else if (active_warps == 0 || active_warps != stalled_warps) begin
timeout_ctr <= 0;
end
end
end
`RUNTIME_ASSERT(timeout_ctr < `STALL_TIMEOUT, ("%t: *** core%0d-scheduler-timeout: stalled_warps=%b", $time, CORE_ID, stalled_warps));
`SCOPE_ASSIGN (wsched_scheduled, warp_scheduled);
`SCOPE_ASSIGN (wsched_schedule_uuid, instr_uuid);

4
hw/rtl/VX_writeback.sv
View file

@ -19,7 +19,7 @@ module VX_writeback #(
VX_writeback_if.master writeback_if,
// simulation helper signals
output reg [`NUM_REGS-1:0][31:0] sim_last_wb_value
output reg [`NUM_REGS-1:0][31:0] sim_wb_value
);
`UNUSED_PARAM (CORE_ID)
@ -87,7 +87,7 @@ module VX_writeback #(
// simulation helper signal to get RISC-V tests Pass/Fail status
always @(posedge clk) begin
if (writeback_if.valid && writeback_if.ready) begin
sim_last_wb_value[writeback_if.rd] <= writeback_if.data[0];
sim_wb_value[writeback_if.rd] <= writeback_if.data[0];
end
end

24
hw/rtl/Vortex.sv
View file

@ -22,7 +22,7 @@ module Vortex (
input wire [`VX_MEM_TAG_WIDTH-1:0] mem_rsp_tag,
output wire mem_rsp_ready,
// DCR request
// DCR write request
input wire dcr_wr_valid,
input wire [`VX_DCR_ADDR_WIDTH-1:0] dcr_wr_addr,
input wire [`VX_DCR_DATA_WIDTH-1:0] dcr_wr_data,
@ -70,10 +70,12 @@ module Vortex (
`ifdef EXT_ROP_ENABLE
VX_rop_dcr_if rop_dcr_if();
`endif
`RESET_RELAY (dcr_reset, reset);
VX_dcr_data dcr_data(
.clk (clk),
.reset (reset),
.reset (dcr_reset),
.dcr_base_if (dcr_base_if),
`ifdef EXT_TEX_ENABLE
.tex_dcr_if (tex_dcr_if),
@ -91,13 +93,13 @@ module Vortex (
);
wire sim_ebreak /* verilator public */;
wire [`NUM_REGS-1:0][31:0] sim_last_wb_value /* verilator public */;
wire [`NUM_REGS-1:0][31:0] sim_wb_value /* verilator public */;
wire [`NUM_CLUSTERS-1:0] per_cluster_sim_ebreak;
wire [`NUM_CLUSTERS-1:0][`NUM_REGS-1:0][31:0] per_cluster_sim_last_wb_value;
wire [`NUM_CLUSTERS-1:0][`NUM_REGS-1:0][31:0] per_cluster_sim_wb_value;
assign sim_ebreak = per_cluster_sim_ebreak[0];
assign sim_last_wb_value = per_cluster_sim_last_wb_value[0];
assign sim_wb_value = per_cluster_sim_wb_value[0];
`UNUSED_VAR (per_cluster_sim_ebreak)
`UNUSED_VAR (per_cluster_sim_last_wb_value)
`UNUSED_VAR (per_cluster_sim_wb_value)
VX_mem_req_if #(
.DATA_WIDTH (`L2_MEM_DATA_WIDTH),
@ -115,7 +117,7 @@ module Vortex (
// Generate all clusters
for (genvar i = 0; i < `NUM_CLUSTERS; i++) begin
`START_RELAY (cluster_reset);
`RESET_RELAY (cluster_reset, reset | start);
VX_cluster #(
.CLUSTER_ID (i)
@ -140,7 +142,7 @@ module Vortex (
.mem_rsp_if (per_cluster_mem_rsp_if[i]),
.sim_ebreak (per_cluster_sim_ebreak[i]),
.sim_last_wb_value (per_cluster_sim_last_wb_value[i]),
.sim_wb_value (per_cluster_sim_wb_value[i]),
.busy (per_cluster_busy[i])
);
@ -154,7 +156,7 @@ module Vortex (
VX_perf_cache_if perf_l3cache_if();
`endif
`START_RELAY (l3_reset);
`RESET_RELAY (l3_reset, reset | start);
VX_cache_wrap #(
.CACHE_ID (`L3_CACHE_ID),
@ -193,8 +195,6 @@ module Vortex (
`else
`START_RELAY (mem_arb_reset);
VX_mem_mux #(
.NUM_REQS (`NUM_CLUSTERS),
.DATA_WIDTH (`L2_MEM_DATA_WIDTH),
@ -204,7 +204,7 @@ module Vortex (
.BUFFERED_RSP ((`NUM_CLUSTERS > 1) ? 1 : 0)
) mem_mux (
.clk (clk),
.reset (mem_arb_reset),
.reset (reset),
.req_in_if (per_cluster_mem_req_if),
.rsp_in_if (per_cluster_mem_rsp_if),
.req_out_if (mem_req_if),

2
hw/rtl/Vortex_axi.sv
View file

@ -57,7 +57,7 @@ module Vortex_axi #(
input wire m_axi_rvalid,
output wire m_axi_rready,
// CSR write request
// DCR write request
input wire dcr_wr_valid,
input wire [`VX_DCR_ADDR_WIDTH-1:0] dcr_wr_addr,
input wire [`VX_DCR_DATA_WIDTH-1:0] dcr_wr_data,

14
hw/rtl/afu/vortex_afu.sv
View file

@ -530,8 +530,6 @@ VX_mem_rsp_if #(
.TAG_WIDTH (AVS_REQ_TAGW+1)
) mem_rsp_if();
`RESET_RELAY (mem_arb_reset);
VX_mem_mux #(
.NUM_REQS (2),
.DATA_WIDTH (LMEM_DATA_WIDTH),
@ -542,7 +540,7 @@ VX_mem_mux #(
.BUFFERED_RSP (2)
) mem_mux (
.clk (clk),
.reset (mem_arb_reset),
.reset (reset),
.req_in_if (cci_vx_mem_req_if),
.rsp_in_if (cci_vx_mem_rsp_if),
.req_out_if (mem_req_if),
@ -551,8 +549,6 @@ VX_mem_mux #(
//--
`RESET_RELAY (avs_adapter_reset);
VX_avs_adapter #(
.AVS_DATA_WIDTH (LMEM_DATA_WIDTH),
.AVS_ADDR_WIDTH (LMEM_ADDR_WIDTH),
@ -562,7 +558,7 @@ VX_avs_adapter #(
.RD_QUEUE_SIZE (AVS_RD_QUEUE_SIZE)
) avs_adapter (
.clk (clk),
.reset (avs_adapter_reset),
.reset (reset),
// Memory request
.mem_req_valid (mem_req_if.valid),
@ -720,15 +716,13 @@ always @(posedge clk) begin
end
end
`RESET_RELAY (cci_rdq_reset);
VX_fifo_queue #(
.DATAW (CCI_RD_QUEUE_DATAW),
.SIZE (CCI_RD_QUEUE_SIZE),
.OUT_REG (1)
) cci_rd_req_queue (
.clk (clk),
.reset (cci_rdq_reset),
.reset (reset),
.push (cci_rdq_push),
.pop (cci_rdq_pop),
.data_in (cci_rdq_din),
@ -1011,7 +1005,7 @@ VX_fifo_queue #(
wire scope_changed = `SCOPE_TRIGGER;
`RESET_RELAY (scope_reset);
`RESET_RELAY (scope_reset, reset);
VX_scope #(
.DATAW ($bits({`SCOPE_DATA_LIST,`SCOPE_UPDATE_LIST})),

4
hw/rtl/cache/VX_cache.sv vendored
View file

@ -179,7 +179,7 @@ module VX_cache #(
wire [`LINE_SEL_BITS-1:0] flush_addr;
wire flush_enable;
`RESET_RELAY (flush_reset);
`RESET_RELAY (flush_reset, reset);
VX_flush_ctrl #(
.CACHE_SIZE (CACHE_SIZE),
@ -349,7 +349,7 @@ module VX_cache #(
assign curr_bank_mem_rsp_data = mem_rsp_data_s;
assign per_bank_mem_rsp_ready[i] = curr_bank_mem_rsp_ready;
`RESET_RELAY (bank_reset);
`RESET_RELAY (bank_reset, reset);
VX_bank #(
.BANK_ID (i),

2
hw/rtl/fp_cores/VX_fp_div.sv
View file

@ -51,7 +51,7 @@ module VX_fp_div #(
.data_out (result[i])
);
`else
`RESET_RELAY (fdiv_reset);
`RESET_RELAY (fdiv_reset, reset);
acl_fdiv fdiv (
.clk (clk),

2
hw/rtl/fp_cores/VX_fp_fma.sv
View file

@ -80,7 +80,7 @@ module VX_fp_fma #(
.data_out (result[i])
);
`else
`RESET_RELAY (fma_reset);
`RESET_RELAY (fma_reset, reset);
acl_fmadd fmadd (
.clk (clk),

2
hw/rtl/fp_cores/VX_fp_sqrt.sv
View file

@ -50,7 +50,7 @@ module VX_fp_sqrt #(
.data_out (result[i])
);
`else
`RESET_RELAY (fsqrt_reset);
`RESET_RELAY (fsqrt_reset, reset);
acl_fsqrt fsqrt (
.clk (clk),

10
hw/rtl/fp_cores/VX_fpu_fpga.sv
View file

@ -74,11 +74,11 @@ module VX_fpu_fpga #(
endcase
end
`RESET_RELAY (fma_reset);
`RESET_RELAY (div_reset);
`RESET_RELAY (sqrt_reset);
`RESET_RELAY (cvt_reset);
`RESET_RELAY (ncp_reset);
`RESET_RELAY (fma_reset, reset);
`RESET_RELAY (div_reset, reset);
`RESET_RELAY (sqrt_reset, reset);
`RESET_RELAY (cvt_reset, reset);
`RESET_RELAY (ncp_reset, reset);
VX_fp_fma #(
.NUM_LANES (NUM_LANES),

9
hw/rtl/interfaces/VX_wstall_if.sv → hw/rtl/interfaces/VX_wrelease_if.sv
View file

@ -1,21 +1,18 @@
`include "VX_define.vh"
interface VX_wstall_if();
interface VX_wrelease_if();
wire valid;
wire [`NW_BITS-1:0] wid;
wire stalled;
modport master (
output valid,
output wid,
output stalled
output wid
);
modport slave (
input valid,
input wid,
input stalled
input wid
);
endinterface

4
sim/rtlsim/processor.cpp
View file

@ -616,9 +616,9 @@ private:
int get_last_wb_value(int reg) const {
#ifdef AXI_BUS
return (int)device_->Vortex_axi->vortex->sim_last_wb_value[reg];
return (int)device_->Vortex_axi->vortex->sim_wb_value[reg];
#else
return (int)device_->Vortex->sim_last_wb_value[reg];
return (int)device_->Vortex->sim_wb_value[reg];
#endif
}