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minor updates

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This commit is contained in:
Blaise Tine 2021-08-28 15:21:40 -07:00
parent 28eb3cfdb2
commit 12b8b4af24
8 changed files with 33 additions and 16 deletions
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5
ci/regression.sh
View file

@ -77,8 +77,9 @@ CONFIGS="-DDNUM_BANKS=1" ./ci/blackbox.sh --driver=rtlsim --cores=1 --app=demo
CONFIGS="-DDNUM_BANKS=2" ./ci/blackbox.sh --driver=rtlsim --cores=1 --app=demo
# test cache multi-porting
CONFIGS="-DDNUM_PORTS=2" ./ci/blackbox.sh --driver=rtlsim --cores=1 --app=demo
CONFIGS="-DDNUM_PORTS=4" ./ci/blackbox.sh --driver=rtlsim --cores=1 --app=demo
CONFIGS="-DDNUM_PORTS=2" ./ci/blackbox.sh --driver=rtlsim --cores=1 --app=io_addr
CONFIGS="-DDNUM_PORTS=4" ./ci/blackbox.sh --driver=rtlsim --cores=1 --app=io_addr
CONFIGS="-DL2NUM_PORTS=2" ./ci/blackbox.sh --driver=rtlsim --cores=2 --l2cache --app=io_addr
# test 128-bit MEM block
CONFIGS=-DMEM_BLOCK_SIZE=16 ./ci/blackbox.sh --driver=vlsim --cores=1 --app=demo

1
hw/rtl/VX_cluster.v
View file

@ -87,6 +87,7 @@ module VX_cluster #(
.CACHE_SIZE (`L2CACHE_SIZE),
.CACHE_LINE_SIZE (`L2CACHE_LINE_SIZE),
.NUM_BANKS (`L2NUM_BANKS),
.NUM_PORTS (`L2NUM_PORTS),
.WORD_SIZE (`L2WORD_SIZE),
.NUM_REQS (`L2NUM_REQS),
.CREQ_SIZE (`L2CREQ_SIZE),

3
hw/rtl/VX_decode.v
View file

@ -192,7 +192,8 @@ module VX_decode #(
end
`INST_F: begin
ex_type = `EX_LSU;
op_mod = `MOD_BITS'(!func3[0]); // data fence
op_type = `OP_BITS'(func3[0]);
op_mod = `MOD_BITS'(1);
end
`INST_SYS : begin
if (func3[1:0] != 0) begin

4
hw/rtl/VX_define.vh
View file

@ -154,6 +154,10 @@
`define LSU_OP(x) x[`LSU_BITS-1:0]
`define LSU_IS_FENCE(x) x[0]
`define FENCE_BITS 1
`define FENCE_D 1'h0
`define FENCE_I 1'h1
`define CSR_RW 2'h1
`define CSR_RS 2'h2
`define CSR_RC 2'h3

30
hw/rtl/VX_print_instr.vh
View file

@ -71,17 +71,25 @@ task print_ex_op (
end
end
`EX_LSU: begin
case (`LSU_BITS'(op_type))
`LSU_LB: dpi_trace("LB");
`LSU_LH: dpi_trace("LH");
`LSU_LW: dpi_trace("LW");
`LSU_LBU:dpi_trace("LBU");
`LSU_LHU:dpi_trace("LHU");
`LSU_SB: dpi_trace("SB");
`LSU_SH: dpi_trace("SH");
`LSU_SW: dpi_trace("SW");
default: dpi_trace("?");
endcase
if (op_mod == 0) begin
case (`LSU_BITS'(op_type))
`LSU_LB: dpi_trace("LB");
`LSU_LH: dpi_trace("LH");
`LSU_LW: dpi_trace("LW");
`LSU_LBU:dpi_trace("LBU");
`LSU_LHU:dpi_trace("LHU");
`LSU_SB: dpi_trace("SB");
`LSU_SH: dpi_trace("SH");
`LSU_SW: dpi_trace("SW");
default: dpi_trace("?");
endcase
end else if (op_mod == 1) begin
case (`FENCE_BITS'(op_type))
`FENCE_D: dpi_trace("DFENCE");
`FENCE_I: dpi_trace("IFENCE");
default: dpi_trace("?");
endcase
end
end
`EX_CSR: begin
case (`CSR_BITS'(op_type))

2
tests/regression/dogfood/Makefile
View file

@ -21,7 +21,7 @@ VX_SRCS = kernel.c
#CXXFLAGS += -std=c++11 -O2 -Wall -Wextra -pedantic -Wfatal-errors
CXXFLAGS += -std=c++11 -O0 -g -Wall -Wextra -pedantic -Wfatal-errors
CXXFLAGS += -I$(VORTEX_DRV_PATH)/include
CXXFLAGS += -I$(VORTEX_DRV_PATH)/include -I$(VORTEX_RT_PATH)/../hw
LDFLAGS += -L$(VORTEX_DRV_PATH)/stub -lvortex

1
tests/regression/dogfood/main.cpp
View file

@ -3,6 +3,7 @@
#include <unistd.h>
#include <string.h>
#include <vortex.h>
#include <VX_config.h>
#include "testcases.h"
#include "common.h"

3
tests/riscv/isa/Makefile
View file

@ -1,8 +1,9 @@
ALL_TESTS := $(wildcard *.hex)
D_TESTS := $(wildcard *ud-p-*.hex)
V_TESTS := $(wildcard *-v-*.hex)
EXCLUDED_TESTS := $(V_TESTS) rv32si-p-scall.hex rv32si-p-sbreak.hex rv32mi-p-breakpoint.hex rv32ud-p-fclass.hex rv32ua-p-amomax_w.hex rv32ua-p-amoxor_w.hex rv32ud-p-ldst.hex rv32ua-p-amoor_w.hex rv32mi-p-ma_addr.hex rv32ud-p-fdiv.hex rv32ud-p-fcmp.hex rv32mi-p-mcsr.hex rv32ua-p-amoswap_w.hex rv32mi-p-ma_fetch.hex rv32mi-p-csr.hex rv32ua-p-amoadd_w.hex rv32si-p-dirty.hex rv32ud-p-fcvt.hex rv32ui-p-fence_i.hex rv32si-p-csr.hex rv32mi-p-shamt.hex rv32ua-p-amomin_w.hex rv32ua-p-lrsc.hex rv32ud-p-fmadd.hex rv32ud-p-fadd.hex rv32si-p-wfi.hex rv32ua-p-amomaxu_w.hex rv32si-p-ma_fetch.hex rv32ud-p-fmin.hex rv32mi-p-illegal.hex rv32uc-p-rvc.hex rv32mi-p-sbreak.hex rv32ua-p-amominu_w.hex rv32ua-p-amoand_w.hex
EXCLUDED_TESTS := $(V_TESTS) $(D_TESTS) rv32si-p-scall.hex rv32si-p-sbreak.hex rv32mi-p-breakpoint.hex rv32ua-p-amomax_w.hex rv32ua-p-amoxor_w.hex rv32ua-p-amoor_w.hex rv32mi-p-ma_addr.hex rv32mi-p-mcsr.hex rv32ua-p-amoswap_w.hex rv32mi-p-ma_fetch.hex rv32mi-p-csr.hex rv32ua-p-amoadd_w.hex rv32si-p-dirty.hex rv32ui-p-fence_i.hex rv32si-p-csr.hex rv32mi-p-shamt.hex rv32ua-p-amomin_w.hex rv32ua-p-lrsc.hex rv32si-p-wfi.hex rv32ua-p-amomaxu_w.hex rv32si-p-ma_fetch.hex rv32mi-p-illegal.hex rv32uc-p-rvc.hex rv32mi-p-sbreak.hex rv32ua-p-amominu_w.hex rv32ua-p-amoand_w.hex
TESTS := $(filter-out $(EXCLUDED_TESTS), $(ALL_TESTS))