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adding missing files, buffering teh snoop forwarder

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This commit is contained in:
Blaise Tine 2020-12-09 00:24:32 -08:00
parent 0d595bae3c
commit 12f7fcfa75
8 changed files with 1628 additions and 16 deletions
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29
hw/rtl/VX_cluster.v
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@ -309,11 +309,16 @@ module VX_cluster #(
wire [`NUM_CORES-1:0][`XDRAM_TAG_WIDTH-1:0] per_core_dram_req_tag_qual;
wire [`NUM_CORES-1:0] per_core_dram_req_ready_qual;
wire [`NUM_CORES-1:0] per_core_dram_rsp_valid_unqual;
wire [`NUM_CORES-1:0][`DDRAM_LINE_WIDTH-1:0] per_core_dram_rsp_data_unqual;
wire [`NUM_CORES-1:0][`XDRAM_TAG_WIDTH-1:0] per_core_dram_rsp_tag_unqual;
wire [`NUM_CORES-1:0] per_core_dram_rsp_ready_unqual;
for (genvar i = 0; i < `NUM_CORES; i++) begin
VX_skid_buffer #(
.DATAW (1 + `DDRAM_BYTEEN_WIDTH + `DDRAM_ADDR_WIDTH + `DDRAM_LINE_WIDTH + `XDRAM_TAG_WIDTH),
.PASSTHRU (`NUM_CORES < 4)
) dram_req_buffer (
) core_req_buffer (
.clk (clk),
.reset (reset),
.valid_in (per_core_dram_req_valid[i]),
@ -323,6 +328,20 @@ module VX_cluster #(
.data_out ({per_core_dram_req_rw_qual[i], per_core_dram_req_byteen_qual[i], per_core_dram_req_addr_qual[i], per_core_dram_req_data_qual[i], per_core_dram_req_tag_qual[i]}),
.ready_out (per_core_dram_req_ready_qual[i])
);
VX_skid_buffer #(
.DATAW (`DDRAM_LINE_WIDTH + `XDRAM_TAG_WIDTH),
.PASSTHRU (1)
) core_rsp_buffer (
.clk (clk),
.reset (reset),
.valid_in (per_core_dram_rsp_valid_unqual[i]),
.data_in ({per_core_dram_rsp_data_unqual[i], per_core_dram_rsp_tag_unqual[i]}),
.ready_in (per_core_dram_rsp_ready_unqual[i]),
.valid_out (per_core_dram_rsp_valid[i]),
.data_out ({per_core_dram_rsp_data[i], per_core_dram_rsp_tag[i]}),
.ready_out (per_core_dram_rsp_ready[i])
);
end
VX_cache #(
@ -366,10 +385,10 @@ module VX_cluster #(
.core_req_ready (per_core_dram_req_ready_qual),
// Core response
.core_rsp_valid (per_core_dram_rsp_valid),
.core_rsp_data (per_core_dram_rsp_data),
.core_rsp_tag (per_core_dram_rsp_tag),
.core_rsp_ready (per_core_dram_rsp_ready),
.core_rsp_valid (per_core_dram_rsp_valid_unqual),
.core_rsp_data (per_core_dram_rsp_data_unqual),
.core_rsp_tag (per_core_dram_rsp_tag_unqual),
.core_rsp_ready (per_core_dram_rsp_ready_unqual),
// DRAM request
.dram_req_valid (dram_req_valid),

29
hw/rtl/Vortex.v
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@ -308,9 +308,14 @@ module Vortex (
wire [`NUM_CLUSTERS-1:0][`L2DRAM_BYTEEN_WIDTH-1:0] per_cluster_dram_req_byteen_qual;
wire [`NUM_CLUSTERS-1:0][`L2DRAM_ADDR_WIDTH-1:0] per_cluster_dram_req_addr_qual;
wire [`NUM_CLUSTERS-1:0][`L2DRAM_LINE_WIDTH-1:0] per_cluster_dram_req_data_qual;
wire [`NUM_CLUSTERS-1:0][`L2DRAM_TAG_WIDTH-1:0] per_cluster_dram_req_tag_qual;
wire [`NUM_CLUSTERS-1:0][`L2DRAM_TAG_WIDTH-1:0] per_cluster_dram_req_tag_qual;
wire [`NUM_CLUSTERS-1:0] per_cluster_dram_req_ready_qual;
wire [`NUM_CLUSTERS-1:0] per_cluster_dram_rsp_valid_unqual;
wire [`NUM_CLUSTERS-1:0][`L2DRAM_LINE_WIDTH-1:0] per_cluster_dram_rsp_data_unqual;
wire [`NUM_CLUSTERS-1:0][`L2DRAM_TAG_WIDTH-1:0] per_cluster_dram_rsp_tag_unqual;
wire [`NUM_CLUSTERS-1:0] per_cluster_dram_rsp_ready_unqual;
for (genvar i = 0; i < `NUM_CLUSTERS; i++) begin
VX_skid_buffer #(
.DATAW (1 + `L2DRAM_BYTEEN_WIDTH + `L2DRAM_ADDR_WIDTH + `L2DRAM_LINE_WIDTH + `L2DRAM_TAG_WIDTH),
@ -325,6 +330,20 @@ module Vortex (
.data_out ({per_cluster_dram_req_rw_qual[i], per_cluster_dram_req_byteen_qual[i], per_cluster_dram_req_addr_qual[i], per_cluster_dram_req_data_qual[i], per_cluster_dram_req_tag_qual[i]}),
.ready_out (per_cluster_dram_req_ready_qual[i])
);
VX_skid_buffer #(
.DATAW (`L2DRAM_LINE_WIDTH + `L2DRAM_TAG_WIDTH),
.PASSTHRU (1)
) core_rsp_buffer (
.clk (clk),
.reset (reset),
.valid_in (per_cluster_dram_rsp_valid_unqual[i]),
.data_in ({per_cluster_dram_rsp_data_unqual[i], per_cluster_dram_rsp_tag_unqual[i]}),
.ready_in (per_cluster_dram_rsp_ready_unqual[i]),
.valid_out (per_cluster_dram_rsp_valid[i]),
.data_out ({per_cluster_dram_rsp_data[i], per_cluster_dram_rsp_tag[i]}),
.ready_out (per_cluster_dram_rsp_ready[i])
);
end
VX_cache #(
@ -368,10 +387,10 @@ module Vortex (
.core_req_ready (per_cluster_dram_req_ready_qual),
// Core response
.core_rsp_valid (per_cluster_dram_rsp_valid),
.core_rsp_data (per_cluster_dram_rsp_data),
.core_rsp_tag (per_cluster_dram_rsp_tag),
.core_rsp_ready (per_cluster_dram_rsp_ready),
.core_rsp_valid (per_cluster_dram_rsp_valid_unqual),
.core_rsp_data (per_cluster_dram_rsp_data_unqual),
.core_rsp_tag (per_cluster_dram_rsp_tag_unqual),
.core_rsp_ready (per_cluster_dram_rsp_ready_unqual),
// DRAM request
.dram_req_valid (dram_req_valid),

131
hw/rtl/afu/VX_avs_wrapper.v Normal file
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@ -0,0 +1,131 @@
`include "VX_define.vh"
module VX_avs_wrapper #(
parameter AVS_DATAW = 1,
parameter AVS_ADDRW = 1,
parameter AVS_BURSTW = 1,
parameter AVS_BANKS = 1,
parameter REQ_TAGW = 1,
parameter RD_QUEUE_SIZE = 1,
parameter AVS_BYTEENW = (AVS_DATAW / 8),
parameter RD_QUEUE_ADDRW= $clog2(RD_QUEUE_SIZE+1),
parameter AVS_BANKS_BITS= $clog2(AVS_BANKS)
) (
input wire clk,
input wire reset,
// AVS bus
output wire [AVS_DATAW-1:0] avs_writedata,
input wire [AVS_DATAW-1:0] avs_readdata,
output wire [AVS_ADDRW-1:0] avs_address,
input wire avs_waitrequest,
output wire avs_write,
output wire avs_read,
output wire [AVS_BYTEENW-1:0] avs_byteenable,
output wire [AVS_BURSTW-1:0] avs_burstcount,
input avs_readdatavalid,
output wire [AVS_BANKS_BITS-1:0] avs_bankselect,
// DRAM request
input wire dram_req_valid,
input wire dram_req_rw,
input wire [AVS_BYTEENW-1:0] dram_req_byteen,
input wire [AVS_ADDRW-1:0] dram_req_addr,
input wire [AVS_DATAW-1:0] dram_req_data,
input wire [REQ_TAGW-1:0] dram_req_tag,
output wire dram_req_ready,
// DRAM response
output wire dram_rsp_valid,
output wire [AVS_DATAW-1:0] dram_rsp_data,
output wire [REQ_TAGW-1:0] dram_rsp_tag,
input wire dram_rsp_ready
);
reg [AVS_BANKS_BITS-1:0] avs_bankselect_r;
reg [AVS_BURSTW-1:0] avs_burstcount_r;
wire avs_reqq_push = dram_req_valid && dram_req_ready && !dram_req_rw;
wire avs_reqq_pop = dram_rsp_valid && dram_rsp_ready;
wire avs_rspq_push = avs_readdatavalid;
wire avs_rspq_pop = avs_reqq_pop;
wire avs_rspq_empty;
reg [RD_QUEUE_ADDRW-1:0] avs_pending_reads;
wire [RD_QUEUE_ADDRW-1:0] avs_pending_reads_n;
assign avs_pending_reads_n = avs_pending_reads
+ RD_QUEUE_ADDRW'((avs_reqq_push && !avs_rspq_pop) ? 1 :
(avs_rspq_pop && !avs_reqq_push) ? -1 : 0);
always @(posedge clk) begin
if (reset) begin
avs_burstcount_r <= 1;
avs_bankselect_r <= 0;
avs_pending_reads <= 0;
end else begin
avs_pending_reads <= avs_pending_reads_n;
end
end
VX_generic_queue #(
.DATAW (REQ_TAGW),
.SIZE (RD_QUEUE_SIZE),
.BUFFERED (1)
) rd_req_queue (
.clk (clk),
.reset (reset),
.push (avs_reqq_push),
.pop (avs_reqq_pop),
.data_in (dram_req_tag),
.data_out (dram_rsp_tag),
`UNUSED_PIN (empty),
`UNUSED_PIN (full),
`UNUSED_PIN (size)
);
VX_generic_queue #(
.DATAW (AVS_DATAW),
.SIZE (RD_QUEUE_SIZE),
.BUFFERED (1)
) rd_rsp_queue (
.clk (clk),
.reset (reset),
.push (avs_rspq_push),
.pop (avs_rspq_pop),
.data_in (avs_readdata),
.data_out (dram_rsp_data),
.empty (avs_rspq_empty),
`UNUSED_PIN (full),
`UNUSED_PIN (size)
);
wire rsp_queue_ready = (avs_pending_reads != RD_QUEUE_SIZE);
assign avs_read = dram_req_valid && !dram_req_rw && rsp_queue_ready;
assign avs_write = dram_req_valid && dram_req_rw && rsp_queue_ready;
assign avs_address = dram_req_addr;
assign avs_byteenable = dram_req_byteen;
assign avs_writedata = dram_req_data;
assign dram_req_ready = !avs_waitrequest && rsp_queue_ready;
assign avs_burstcount = avs_burstcount_r;
assign avs_bankselect = avs_bankselect_r;
assign dram_rsp_valid = !avs_rspq_empty;
`ifdef DBG_PRINT_AVS
always @(posedge clk) begin
if (dram_req_valid && dram_req_ready) begin
if (dram_req_rw)
$display("%t: AVS Wr Req: addr=%0h, byteen=%0h, tag=%0h, data=%0h", $time, `TO_FULL_ADDR(dram_req_addr), dram_req_byteen, dram_req_tag, dram_req_data);
else
$display("%t: AVS Rd Req: addr=%0h, byteen=%0h, tag=%0h, pending=%0d", $time, `TO_FULL_ADDR(dram_req_addr), dram_req_byteen, dram_req_tag, avs_pending_reads_n);
end
if (dram_rsp_valid && dram_rsp_ready) begin
$display("%t: AVS Rd Rsp: tag=%0h, data=%0h, pending=%0d", $time, dram_rsp_tag, dram_rsp_data, avs_pending_reads_n);
end
end
`endif
endmodule

244
hw/rtl/afu/ccip/ccip_if_pkg.sv Normal file
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@ -0,0 +1,244 @@
// Date: 02/2/2016
// Compliant with CCI-P spec v0.71
package ccip_if_pkg;
//=====================================================================
// CCI-P interface defines
//=====================================================================
parameter CCIP_VERSION_NUMBER = 12'h071;
parameter CCIP_CLADDR_WIDTH = 42;
parameter CCIP_CLDATA_WIDTH = 512;
parameter CCIP_MMIOADDR_WIDTH = 16;
parameter CCIP_MMIODATA_WIDTH = 64;
parameter CCIP_TID_WIDTH = 9;
parameter CCIP_MDATA_WIDTH = 16;
// Number of requests that can be accepted after almost full is asserted.
parameter CCIP_TX_ALMOST_FULL_THRESHOLD = 8;
parameter CCIP_MMIO_RD_TIMEOUT = 512;
parameter CCIP_SYNC_RESET_POLARITY=1; // Active High Reset
// Base types
//----------------------------------------------------------------------
typedef logic [CCIP_CLADDR_WIDTH-1:0] t_ccip_clAddr;
typedef logic [CCIP_CLDATA_WIDTH-1:0] t_ccip_clData;
typedef logic [CCIP_MMIOADDR_WIDTH-1:0] t_ccip_mmioAddr;
typedef logic [CCIP_MMIODATA_WIDTH-1:0] t_ccip_mmioData;
typedef logic [CCIP_TID_WIDTH-1:0] t_ccip_tid;
typedef logic [CCIP_MDATA_WIDTH-1:0] t_ccip_mdata;
typedef logic [1:0] t_ccip_clNum;
typedef logic [2:0] t_ccip_qwIdx;
// Request Type Encodings
//----------------------------------------------------------------------
// Channel 0
typedef enum logic [3:0] {
eREQ_RDLINE_I = 4'h0, // Memory Read with FPGA Cache Hint=Invalid
eREQ_RDLINE_S = 4'h1 // Memory Read with FPGA Cache Hint=Shared
} t_ccip_c0_req;
// Channel 1
typedef enum logic [3:0] {
eREQ_WRLINE_I = 4'h0, // Memory Write with FPGA Cache Hint=Invalid
eREQ_WRLINE_M = 4'h1, // Memory Write with FPGA Cache Hint=Modified
eREQ_WRPUSH_I = 4'h2, // Memory Write with DDIO Hint ** NOT SUPPORTED CURRENTLY **
eREQ_WRFENCE = 4'h4, // Memory Write Fence
// eREQ_ATOMIC = 4'h5, // Atomic operation: Compare-Exchange for Memory Addr ** NOT SUPPORTED CURRENTELY **
eREQ_INTR = 4'h6 // Interrupt the CPU ** NOT SUPPORTED CURRENTLY **
} t_ccip_c1_req;
// Response Type Encodings
//----------------------------------------------------------------------
// Channel 0
typedef enum logic [3:0] {
eRSP_RDLINE = 4'h0, // Memory Read
eRSP_UMSG = 4'h4 // UMsg received
// eRSP_ATOMIC = 4'h5 // Atomic Operation: Compare-Exchange for Memory Addr
} t_ccip_c0_rsp;
// Channel 1
typedef enum logic [3:0] {
eRSP_WRLINE = 4'h0, // Memory Write
eRSP_WRFENCE = 4'h4, // Memory Write Fence
eRSP_INTR = 4'h6 // Interrupt delivered to the CPU ** NOT SUPPORTED CURRENTLY **
} t_ccip_c1_rsp;
//
// Virtual Channel Select
//----------------------------------------------------------------------
typedef enum logic [1:0] {
eVC_VA = 2'b00,
eVC_VL0 = 2'b01,
eVC_VH0 = 2'b10,
eVC_VH1 = 2'b11
} t_ccip_vc;
// Multi-CL Memory Request
//----------------------------------------------------------------------
typedef enum logic [1:0] {
eCL_LEN_1 = 2'b00,
eCL_LEN_2 = 2'b01,
eCL_LEN_4 = 2'b11
} t_ccip_clLen;
//
// Structures for Request and Response headers
//----------------------------------------------------------------------
typedef struct packed {
t_ccip_vc vc_sel;
logic [1:0] rsvd1; // reserved, drive 0
t_ccip_clLen cl_len;
t_ccip_c0_req req_type;
logic [5:0] rsvd0; // reserved, drive 0
t_ccip_clAddr address;
t_ccip_mdata mdata;
} t_ccip_c0_ReqMemHdr;
parameter CCIP_C0TX_HDR_WIDTH = $bits(t_ccip_c0_ReqMemHdr);
typedef struct packed {
logic [5:0] rsvd2;
t_ccip_vc vc_sel;
logic sop;
logic rsvd1; // reserved, drive 0
t_ccip_clLen cl_len;
t_ccip_c1_req req_type;
logic [5:0] rsvd0; // reserved, drive 0
t_ccip_clAddr address;
t_ccip_mdata mdata;
} t_ccip_c1_ReqMemHdr;
parameter CCIP_C1TX_HDR_WIDTH = $bits(t_ccip_c1_ReqMemHdr);
typedef struct packed {
logic [5:0] rsvd2; // reserved, drive 0
t_ccip_vc vc_sel;
logic [3:0] rsvd1; // reserved, drive 0
t_ccip_c1_req req_type;
logic [47:0] rsvd0; // reserved, drive 0
t_ccip_mdata mdata;
}t_ccip_c1_ReqFenceHdr;
typedef struct packed {
t_ccip_vc vc_used;
logic rsvd1; // reserved, don't care
logic hit_miss;
logic [1:0] rsvd0; // reserved, don't care
t_ccip_clNum cl_num;
t_ccip_c0_rsp resp_type;
t_ccip_mdata mdata;
} t_ccip_c0_RspMemHdr;
parameter CCIP_C0RX_HDR_WIDTH = $bits(t_ccip_c0_RspMemHdr);
typedef struct packed {
t_ccip_vc vc_used;
logic rsvd1; // reserved, don't care
logic hit_miss;
logic format;
logic rsvd0; // reserved, don't care
t_ccip_clNum cl_num;
t_ccip_c1_rsp resp_type;
t_ccip_mdata mdata;
} t_ccip_c1_RspMemHdr;
parameter CCIP_C1RX_HDR_WIDTH = $bits(t_ccip_c1_RspMemHdr);
typedef struct packed {
logic [7:0] rsvd0; // reserved, don't care
t_ccip_c1_rsp resp_type;
t_ccip_mdata mdata;
} t_ccip_c1_RspFenceHdr;
// Alternate Channel 0 MMIO request from host :
// MMIO requests arrive on the same channel as read responses, sharing
// t_if_ccip_c0_Rx below. When either mmioRdValid or mmioWrValid is set
// the message is an MMIO request and should be processed by casting
// t_if_ccip_c0_Rx.hdr to t_ccip_c0_ReqMmioHdr.
typedef struct packed {
t_ccip_mmioAddr address; // 4B aligned Mmio address
logic [1:0] length; // 2'b00- 4B, 2'b01- 8B, 2'b10- 64B
logic rsvd; // reserved, don't care
t_ccip_tid tid;
} t_ccip_c0_ReqMmioHdr;
typedef struct packed {
t_ccip_tid tid; // Returned back from ReqMmioHdr
} t_ccip_c2_RspMmioHdr;
parameter CCIP_C2TX_HDR_WIDTH = $bits(t_ccip_c2_RspMmioHdr);
//------------------------------------------------------------------------
// CCI-P Input & Output bus structures
//
// Users are encouraged to use these for AFU development
//------------------------------------------------------------------------
// Channel 0 : Memory Reads
typedef struct packed {
t_ccip_c0_ReqMemHdr hdr; // Request Header
logic valid; // Request Valid
} t_if_ccip_c0_Tx;
// Channel 1 : Memory Writes, Interrupts, CmpXchg
typedef struct packed {
t_ccip_c1_ReqMemHdr hdr; // Request Header
t_ccip_clData data; // Request Data
logic valid; // Request Wr Valid
} t_if_ccip_c1_Tx;
// Channel 2 : MMIO Read response
typedef struct packed {
t_ccip_c2_RspMmioHdr hdr; // Response Header
logic mmioRdValid; // Response Read Valid
t_ccip_mmioData data; // Response Data
} t_if_ccip_c2_Tx;
// Wrap all Tx channels
typedef struct packed {
t_if_ccip_c0_Tx c0;
t_if_ccip_c1_Tx c1;
t_if_ccip_c2_Tx c2;
} t_if_ccip_Tx;
// Channel 0: Memory Read response, MMIO Request
typedef struct packed {
t_ccip_c0_RspMemHdr hdr; // Rd Response/ MMIO req Header
t_ccip_clData data; // Rd Data / MMIO req Data
// Only one of valid, mmioRdValid and mmioWrValid may be set
// in a cycle. When either mmioRdValid or mmioWrValid are true
// the hdr must be processed specially. See t_ccip_c0_ReqMmioHdr
// above.
logic rspValid; // Rd Response Valid
logic mmioRdValid; // MMIO Read Valid
logic mmioWrValid; // MMIO Write Valid
} t_if_ccip_c0_Rx;
// Channel 1: Memory Writes
typedef struct packed {
t_ccip_c1_RspMemHdr hdr; // Response Header
logic rspValid; // Response Valid
} t_if_ccip_c1_Rx;
// Wrap all channels
typedef struct packed {
logic c0TxAlmFull; // C0 Request Channel Almost Full
logic c1TxAlmFull; // C1 Request Channel Almost Full
t_if_ccip_c0_Rx c0;
t_if_ccip_c1_Rx c1;
} t_if_ccip_Rx;
typedef union packed {
t_ccip_c0_RspMemHdr rspMemHdr;
t_ccip_c0_ReqMmioHdr reqMmioHdr;
} t_if_ccip_c0_RxHdr;
endpackage

61
hw/rtl/afu/ccip/local_mem_cfg_pkg.sv Normal file
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@ -0,0 +1,61 @@
//
// Copyright (c) 2017, Intel Corporation
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// Redistributions of source code must retain the above copyright notice, this
// list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
// Neither the name of the Intel Corporation nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//`include "platform_afu_top_config.vh"
`ifdef PLATFORM_PROVIDES_LOCAL_MEMORY
package local_mem_cfg_pkg;
parameter LOCAL_MEM_VERSION_NUMBER = 1;
parameter LOCAL_MEM_ADDR_WIDTH = `PLATFORM_PARAM_LOCAL_MEMORY_ADDR_WIDTH;
parameter LOCAL_MEM_DATA_WIDTH = `PLATFORM_PARAM_LOCAL_MEMORY_DATA_WIDTH;
parameter LOCAL_MEM_BURST_CNT_WIDTH = `PLATFORM_PARAM_LOCAL_MEMORY_BURST_CNT_WIDTH;
// Number of bytes in a data line
parameter LOCAL_MEM_DATA_N_BYTES = LOCAL_MEM_DATA_WIDTH / 8;
// Base types
// --------------------------------------------------------------------
typedef logic [LOCAL_MEM_ADDR_WIDTH-1:0] t_local_mem_addr;
typedef logic [LOCAL_MEM_DATA_WIDTH-1:0] t_local_mem_data;
typedef logic [LOCAL_MEM_BURST_CNT_WIDTH-1:0] t_local_mem_burst_cnt;
// Byte-level mask of a data line
typedef logic [LOCAL_MEM_DATA_N_BYTES-1:0] t_local_mem_byte_mask;
endpackage // local_mem_cfg_pkg
`endif // PLATFORM_PROVIDES_LOCAL_MEMORY

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hw/rtl/afu/vortex_afu.sv Normal file
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37
hw/rtl/afu/vortex_afu.vh Normal file
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`ifndef __VORTEX_AFU__
`define __VORTEX_AFU__
`include "ccip_if_pkg.sv"
`define PLATFORM_PROVIDES_LOCAL_MEMORY
`define PLATFORM_PARAM_LOCAL_MEMORY_ADDR_WIDTH 26
`define PLATFORM_PARAM_LOCAL_MEMORY_DATA_WIDTH 512
`define PLATFORM_PARAM_LOCAL_MEMORY_BURST_CNT_WIDTH 4
`include "local_mem_cfg_pkg.sv"
`define AFU_ACCEL_NAME "vortex_afu"
`define AFU_ACCEL_UUID 128'h35f9452b_25c2_434c_93d5_6f8c60db361c
`define AFU_IMAGE_CMD_CLFLUSH 4
`define AFU_IMAGE_CMD_CSR_READ 5
`define AFU_IMAGE_CMD_CSR_WRITE 6
`define AFU_IMAGE_CMD_MEM_READ 1
`define AFU_IMAGE_CMD_MEM_WRITE 2
`define AFU_IMAGE_CMD_RUN 3
`define AFU_IMAGE_MMIO_CMD_TYPE 10
`define AFU_IMAGE_MMIO_CSR_CORE 24
`define AFU_IMAGE_MMIO_CSR_ADDR 26
`define AFU_IMAGE_MMIO_CSR_DATA 28
`define AFU_IMAGE_MMIO_CSR_READ 30
`define AFU_IMAGE_MMIO_DATA_SIZE 16
`define AFU_IMAGE_MMIO_IO_ADDR 12
`define AFU_IMAGE_MMIO_MEM_ADDR 14
`define AFU_IMAGE_MMIO_SCOPE_READ 20
`define AFU_IMAGE_MMIO_SCOPE_WRITE 22
`define AFU_IMAGE_MMIO_STATUS 18
`define AFU_IMAGE_POWER 0
`define AFU_TOP_IFC "ccip_std_afu_avalon_mm"
`endif

22
hw/rtl/cache/VX_snp_forwarder.v vendored
View file

@ -138,12 +138,22 @@ module VX_snp_forwarder #(
end
reg [NUM_REQS-1:0] snp_fwdout_ready_other;
wire [NUM_REQS-1:0] fwdout_ready_unqual;
for (genvar i = 0; i < NUM_REQS; i++) begin
assign snp_fwdout_valid[i] = fwdout_valid && snp_fwdout_ready_other[i];
assign snp_fwdout_addr[i] = fwdout_addr;
assign snp_fwdout_inv[i] = fwdout_inv;
assign snp_fwdout_tag[i] = fwdout_tag;
VX_skid_buffer #(
.DATAW (DST_ADDR_WIDTH + 1 + TAG_OUT_WIDTH),
.PASSTHRU (NUM_REQS >= 4)
) fwdout_buffer (
.clk (clk),
.reset (reset),
.valid_in (fwdout_valid && snp_fwdout_ready_other[i]),
.data_in ({fwdout_addr, fwdout_inv, fwdout_tag}),
.ready_in (fwdout_ready_unqual[i]),
.valid_out (snp_fwdout_valid[i]),
.data_out ({snp_fwdout_addr[i], snp_fwdout_inv[i], snp_fwdout_tag[i]}),
.ready_out (snp_fwdout_ready[i])
);
end
always @(*) begin
@ -151,12 +161,12 @@ module VX_snp_forwarder #(
for (integer i = 0; i < NUM_REQS; i++) begin
for (integer j = 0; j < NUM_REQS; j++) begin
if (i != j)
snp_fwdout_ready_other[i] &= snp_fwdout_ready[j];
snp_fwdout_ready_other[i] &= fwdout_ready_unqual[j];
end
end
end
assign fwdout_ready = (& snp_fwdout_ready);
assign fwdout_ready = (& fwdout_ready_unqual);
assign snp_req_ready = fwdout_ready && !sfq_full && !dispatch_hold;