github-mirrors/vortex
1
0
Fork 0
mirror of https://github.com/vortexgpgpu/vortex.git synced 2025-04-23 21:39:10 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions

minor update

Browse source
This commit is contained in:
Blaise Tine 2024-04-09 01:58:04 -07:00
parent db35f5d768
commit 135cc4f5a7
3 changed files with 7 additions and 80 deletions
Download patch file Download diff file Expand all files Collapse all files

73
hw/rtl/interfaces/VX_sfu_csr_if.sv
View file

@ -1,73 +0,0 @@
// Copyright © 2019-2023
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
`include "VX_define.vh"
interface VX_sfu_csr_if #(
parameter NUM_LANES = `NUM_SFU_LANES,
parameter PID_WIDTH = `LOG2UP(`NUM_THREADS / NUM_LANES)
) ();
wire read_enable;
wire [`UUID_WIDTH-1:0] read_uuid;
wire [`NW_WIDTH-1:0] read_wid;
wire [NUM_LANES-1:0] read_tmask;
wire [PID_WIDTH-1:0] read_pid;
wire [`VX_CSR_ADDR_BITS-1:0] read_addr;
wire [NUM_LANES-1:0][31:0] read_data;
wire write_enable;
wire [`UUID_WIDTH-1:0] write_uuid;
wire [`NW_WIDTH-1:0] write_wid;
wire [NUM_LANES-1:0] write_tmask;
wire [PID_WIDTH-1:0] write_pid;
wire [`VX_CSR_ADDR_BITS-1:0] write_addr;
wire [NUM_LANES-1:0][31:0] write_data;
modport master (
output read_enable,
output read_uuid,
output read_wid,
output read_tmask,
output read_pid,
output read_addr,
input read_data,
output write_enable,
output write_uuid,
output write_wid,
output write_tmask,
output write_pid,
output write_addr,
output write_data
);
modport slave (
input read_enable,
input read_uuid,
input read_wid,
input read_tmask,
input read_pid,
input read_addr,
output read_data,
input write_enable,
input write_uuid,
input write_wid,
input write_tmask,
input write_pid,
input write_addr,
input write_data
);
endinterface

6
sim/simx/core.cpp
View file

@ -283,10 +283,10 @@ void Core::issue() {
for (uint32_t j = 0, n = uses.size(); j < n; ++j) {
auto& use = uses.at(j);
__unused (use);
if (j) DTN(3, ", ");
DTN(3, use.reg_type << use.reg_id << "(#" << use.uuid << ")");
if (j) DTN(4, ", ");
DTN(4, use.reg_type << use.reg_id << "(#" << use.uuid << ")");
}
DTN(3, "}, " << *trace << std::endl);
DTN(4, "}, " << *trace << std::endl);
}
for (uint32_t j = 0, n = uses.size(); j < n; ++j) {
auto& use = uses.at(j);

8
sim/simx/decode.cpp
View file

@ -107,7 +107,7 @@ static const char* op_string(const Instr &instr) {
}
} else {
switch (func3) {
case 0: return func7 ? "SUB" : "ADD";
case 0: return (func7 & 0x20) ? "SUB" : "ADD";
case 1: return "SLL";
case 2: return "SLT";
case 3: return "SLTU";
@ -179,9 +179,9 @@ static const char* op_string(const Instr &instr) {
}
} else {
switch (func3) {
case 0: return func7 ? "SUBW" : "ADDW";
case 0: return (func7 & 0x20) ? "SUBW" : "ADDW";
case 1: return "SLLW";
case 5: return func7 ? "SRAW" : "SRLW";
case 5: return (func7 & 0x20) ? "SRAW" : "SRLW";
default:
std::abort();
}
@ -190,7 +190,7 @@ static const char* op_string(const Instr &instr) {
switch (func3) {
case 0: return "ADDIW";
case 1: return "SLLIW";
case 5: return func7 ? "SRAIW" : "SRLIW";
case 5: return (func7 & 0x20) ? "SRAIW" : "SRLIW";
default:
std::abort();
}