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Merge branch 'graphics' of github.com:vortexgpgpu/vortex-dev into graphics

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This commit is contained in:
Blaise Tine 2023-03-24 06:41:45 -04:00
commit 1371e7714c
16 changed files with 334 additions and 140 deletions
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114
hw/rtl/libs/VX_dp_ram.sv
View file

@ -34,7 +34,119 @@ module VX_dp_ram #(
end \
end
`ifdef SYNTHESIS
`ifdef QUARTUS
if (LUTRAM != 0) begin
if (OUT_REG != 0) begin
reg [DATAW-1:0] rdata_r;
if (WRENW > 1) begin
`USE_FAST_BRAM reg [WRENW-1:0][WSELW-1:0] ram [SIZE-1:0];
`RAM_INITIALIZATION
always @(posedge clk) begin
for (integer i = 0; i < WRENW; ++i) begin
if (wren[i])
ram[waddr][i] <= wdata[i * WSELW +: WSELW];
end
rdata_r <= ram[raddr];
end
end else begin
`USE_FAST_BRAM reg [DATAW-1:0] ram [SIZE-1:0];
`RAM_INITIALIZATION
always @(posedge clk) begin
if (wren)
ram[waddr] <= wdata;
rdata_r <= ram[raddr];
end
end
assign rdata = rdata_r;
end else begin
if (WRENW > 1) begin
`USE_FAST_BRAM reg [WRENW-1:0][WSELW-1:0] ram [SIZE-1:0];
`RAM_INITIALIZATION
always @(posedge clk) begin
for (integer i = 0; i < WRENW; ++i) begin
if (wren[i])
ram[waddr][i] <= wdata[i * WSELW +: WSELW];
end
end
assign rdata = ram[raddr];
end else begin
`USE_FAST_BRAM reg [DATAW-1:0] ram [SIZE-1:0];
`RAM_INITIALIZATION
always @(posedge clk) begin
if (wren)
ram[waddr] <= wdata;
end
assign rdata = ram[raddr];
end
end
end else begin
if (OUT_REG != 0) begin
reg [DATAW-1:0] rdata_r;
if (WRENW > 1) begin
reg [WRENW-1:0][WSELW-1:0] ram [SIZE-1:0];
`RAM_INITIALIZATION
always @(posedge clk) begin
for (integer i = 0; i < WRENW; ++i) begin
if (wren[i])
ram[waddr][i] <= wdata[i * WSELW +: WSELW];
end
rdata_r <= ram[raddr];
end
end else begin
reg [DATAW-1:0] ram [SIZE-1:0];
`RAM_INITIALIZATION
always @(posedge clk) begin
if (wren)
ram[waddr] <= wdata;
rdata_r <= ram[raddr];
end
end
assign rdata = rdata_r;
end else begin
if (NO_RWCHECK != 0) begin
if (WRENW > 1) begin
`NO_RW_RAM_CHECK reg [WRENW-1:0][WSELW-1:0] ram [SIZE-1:0];
`RAM_INITIALIZATION
always @(posedge clk) begin
for (integer i = 0; i < WRENW; ++i) begin
if (wren[i])
ram[waddr][i] <= wdata[i * WSELW +: WSELW];
end
end
assign rdata = ram[raddr];
end else begin
`NO_RW_RAM_CHECK reg [DATAW-1:0] ram [SIZE-1:0];
`RAM_INITIALIZATION
always @(posedge clk) begin
if (wren)
ram[waddr] <= wdata;
end
assign rdata = ram[raddr];
end
end else begin
if (WRENW > 1) begin
reg [WRENW-1:0][WSELW-1:0] ram [SIZE-1:0];
`RAM_INITIALIZATION
always @(posedge clk) begin
for (integer i = 0; i < WRENW; ++i) begin
if (wren[i])
ram[waddr][i] <= wdata[i * WSELW +: WSELW];
end
end
assign rdata = ram[raddr];
end else begin
reg [DATAW-1:0] ram [SIZE-1:0];
`RAM_INITIALIZATION
always @(posedge clk) begin
if (wren)
ram[waddr] <= wdata;
end
assign rdata = ram[raddr];
end
end
end
end
`elsif VIVADO
if (LUTRAM != 0) begin
`USE_FAST_BRAM reg [DATAW-1:0] ram [SIZE-1:0];
`RAM_INITIALIZATION

3
hw/rtl/libs/VX_generic_buffer.sv
View file

@ -34,8 +34,7 @@ module VX_generic_buffer #(
VX_pipe_register #(
.DATAW (1 + DATAW),
.RESETW (1),
.DEPTH (1)
.RESETW (1)
) pipe_reg (
.clk (clk),
.reset (reset),

5
hw/rtl/libs/VX_pipe_register.sv
View file

@ -3,7 +3,7 @@
`TRACING_OFF
module VX_pipe_register #(
parameter DATAW = 1,
parameter RESETW = DATAW,
parameter RESETW = 0,
parameter DEPTH = 1
) (
input wire clk,
@ -64,8 +64,7 @@ module VX_pipe_register #(
for (genvar i = 1; i <= DEPTH; ++i) begin
VX_pipe_register #(
.DATAW (DATAW),
.RESETW (RESETW),
.DEPTH (1)
.RESETW (RESETW)
) pipe_reg (
.clk (clk),
.reset (reset),

37
hw/rtl/libs/VX_shift_register.sv
View file

@ -13,25 +13,34 @@ module VX_shift_register #(
input wire [DATAW-1:0] data_in,
output wire [NTAPS-1:0][DATAW-1:0] data_out
);
localparam TOTAL_DEPTH = NTAPS * DEPTH;
if (DEPTH != 0) begin
localparam TOTAL_DEPTH = NTAPS * DEPTH;
reg [TOTAL_DEPTH-1:0][DATAW-1:0] entries;
reg [TOTAL_DEPTH-1:0][DATAW-1:0] entries;
always @(posedge clk) begin
for (integer i = 0; i < DATAW; ++i) begin
if ((i >= (DATAW-RESETW)) && reset) begin
for (integer j = 0; j < TOTAL_DEPTH; ++j)
entries[j][i] <= 0;
end else if (enable) begin
for (integer j = 1; j < TOTAL_DEPTH; ++j)
entries[j-1][i] <= entries[j][i];
entries[TOTAL_DEPTH-1][i] <= data_in[i];
always @(posedge clk) begin
for (integer i = 0; i < DATAW; ++i) begin
if ((i >= (DATAW-RESETW)) && reset) begin
for (integer j = 0; j < TOTAL_DEPTH; ++j)
entries[j][i] <= 0;
end else if (enable) begin
for (integer j = 1; j < TOTAL_DEPTH; ++j)
entries[j-1][i] <= entries[j][i];
entries[TOTAL_DEPTH-1][i] <= data_in[i];
end
end
end
end
for (genvar i = 0; i < NTAPS; ++i) begin
assign data_out[i] = entries[i*DEPTH];
for (genvar i = 0; i < NTAPS; ++i) begin
assign data_out[i] = entries[i*DEPTH];
end
end else begin
`UNUSED_VAR (clk)
`UNUSED_VAR (reset)
`UNUSED_VAR (enable)
for (genvar i = 0; i < NTAPS; ++i) begin
assign data_out[i] = data_in;
end
end
endmodule

115
hw/rtl/libs/VX_sp_ram.sv
View file

@ -34,7 +34,120 @@ module VX_sp_ram #(
end \
end
`ifdef SYNTHESIS
`ifdef QUARTUS
if (LUTRAM != 0) begin
if (OUT_REG != 0) begin
reg [DATAW-1:0] rdata_r;
if (WRENW > 1) begin
`USE_FAST_BRAM reg [WRENW-1:0][WSELW-1:0] ram [SIZE-1:0];
`RAM_INITIALIZATION
always @(posedge clk) begin
for (integer i = 0; i < WRENW; ++i) begin
if (wren[i])
ram[addr][i] <= wdata[i * WSELW +: WSELW];
end
rdata_r <= ram[addr];
end
end else begin
`USE_FAST_BRAM reg [DATAW-1:0] ram [SIZE-1:0];
`RAM_INITIALIZATION
always @(posedge clk) begin
if (wren)
ram[addr] <= wdata;
rdata_r <= ram[addr];
end
end
assign rdata = rdata_r;
end else begin
if (WRENW > 1) begin
`USE_FAST_BRAM reg [WRENW-1:0][WSELW-1:0] ram [SIZE-1:0];
`RAM_INITIALIZATION
always @(posedge clk) begin
for (integer i = 0; i < WRENW; ++i) begin
if (wren[i])
ram[addr][i] <= wdata[i * WSELW +: WSELW];
end
end
assign rdata = ram[addr];
end else begin
`USE_FAST_BRAM reg [DATAW-1:0] ram [SIZE-1:0];
`RAM_INITIALIZATION
always @(posedge clk) begin
if (wren)
ram[addr] <= wdata;
end
assign rdata = ram[addr];
end
end
end else begin
if (OUT_REG != 0) begin
reg [DATAW-1:0] rdata_r;
if (WRENW > 1) begin
reg [WRENW-1:0][WSELW-1:0] ram [SIZE-1:0];
`RAM_INITIALIZATION
always @(posedge clk) begin
for (integer i = 0; i < WRENW; ++i) begin
if (wren[i])
ram[addr][i] <= wdata[i * WSELW +: WSELW];
end
rdata_r <= ram[addr];
end
end else begin
reg [DATAW-1:0] ram [SIZE-1:0];
`RAM_INITIALIZATION
always @(posedge clk) begin
if (wren)
ram[addr] <= wdata;
rdata_r <= ram[addr];
end
end
assign rdata = rdata_r;
end else begin
if (NO_RWCHECK != 0) begin
if (WRENW > 1) begin
`NO_RW_RAM_CHECK reg [WRENW-1:0][WSELW-1:0] ram [SIZE-1:0];
`RAM_INITIALIZATION
always @(posedge clk) begin
for (integer i = 0; i < WRENW; ++i) begin
if (wren[i])
ram[addr][i] <= wdata[i * WSELW +: WSELW];
end
end
assign rdata = ram[addr];
end else begin
`NO_RW_RAM_CHECK reg [DATAW-1:0] ram [SIZE-1:0];
`RAM_INITIALIZATION
always @(posedge clk) begin
if (wren)
ram[addr] <= wdata;
end
assign rdata = ram[addr];
end
end else begin
if (WRENW > 1) begin
reg [WRENW-1:0][WSELW-1:0] ram [SIZE-1:0];
`RAM_INITIALIZATION
always @(posedge clk) begin
for (integer i = 0; i < WRENW; ++i) begin
if (wren[i])
ram[addr][i] <= wdata[i * WSELW +: WSELW];
end
end
assign rdata = ram[addr];
end else begin
reg [DATAW-1:0] ram [SIZE-1:0];
`RAM_INITIALIZATION
always @(posedge clk) begin
if (wren)
ram[addr] <= wdata;
end
assign rdata = ram[addr];
end
end
end
end
`elsif VIVADO
if (LUTRAM != 0) begin
`USE_FAST_BRAM reg [DATAW-1:0] ram [SIZE-1:0];
`RAM_INITIALIZATION

8
hw/rtl/raster_unit/VX_raster_edge.sv
View file

@ -62,7 +62,7 @@ module VX_raster_edge #(
VX_shift_register #(
.DATAW (3 * `RASTER_DATA_BITS),
.DEPTH (LATENCY)
) shift_reg (
) shift_reg1 (
.clk (clk),
`UNUSED_PIN (reset),
.enable (enable),
@ -76,12 +76,12 @@ module VX_raster_edge #(
assign result_s[i] = sum[`RASTER_DATA_BITS-1:0];
end
VX_pipe_register #(
VX_shift_register #(
.DATAW (3 * `RASTER_DATA_BITS),
.DEPTH (LATENCY - `LATENCY_IMUL)
) pipe_reg (
) shift_reg2 (
.clk (clk),
.reset (reset),
`UNUSED_PIN (reset),
.enable (enable),
.data_in (result_s),
.data_out (result)

2
hw/rtl/raster_unit/VX_raster_mem.sv
View file

@ -346,7 +346,7 @@ module VX_raster_mem #(
VX_elastic_buffer #(
.DATAW (PRIM_DATA_WIDTH),
.SIZE (QUEUE_SIZE),
.OUT_REG (QUEUE_SIZE > 2)
.OUT_REG (1)
) buf_out (
.clk (clk),
.reset (reset),

2
hw/rtl/rop_unit/VX_rop_blend.sv
View file

@ -29,7 +29,7 @@ module VX_rop_blend #(
);
`UNUSED_SPARAM (INSTANCE_ID)
localparam LATENCY = `LATENCY_IMUL + 2;
localparam LATENCY = 3;
`UNUSED_VAR (dcrs)

126
hw/rtl/rop_unit/VX_rop_blend_multadd.sv
View file

@ -1,19 +1,5 @@
`include "VX_rop_define.vh"
`define MULT8(clk, en, dst, src1, src2) \
VX_multiplier #( \
.A_WIDTH (8), \
.B_WIDTH (8), \
.R_WIDTH (16), \
.LATENCY (`LATENCY_IMUL) \
) __``dst ( \
.clk (clk), \
.enable (en), \
.dataa (src1), \
.datab (src2), \
.result (dst) \
)
module VX_rop_blend_multadd #(
parameter LATENCY = 1
) (
@ -34,71 +20,62 @@ module VX_rop_blend_multadd #(
output rgba_t color_out
);
`STATIC_ASSERT((LATENCY > `LATENCY_IMUL), ("invalid parameter"))
`STATIC_ASSERT((LATENCY == 3), ("invalid parameter"))
`UNUSED_VAR (reset)
localparam LATENCY_REM = LATENCY - `LATENCY_IMUL;
// multiply-add
wire [15:0] prod_src_r, prod_src_g, prod_src_b, prod_src_a;
wire [15:0] prod_dst_r, prod_dst_g, prod_dst_b, prod_dst_a;
reg [15:0] prod_src_r, prod_src_g, prod_src_b, prod_src_a;
reg [15:0] prod_dst_r, prod_dst_g, prod_dst_b, prod_dst_a;
reg [16:0] sum_r, sum_g, sum_b, sum_a;
// src_color x src_factor
`MULT8(clk, enable, prod_src_r, src_color.r, src_factor.r);
`MULT8(clk, enable, prod_src_g, src_color.g, src_factor.g);
`MULT8(clk, enable, prod_src_b, src_color.b, src_factor.b);
`MULT8(clk, enable, prod_src_a, src_color.a, src_factor.a);
always @(posedge clk) begin
if (enable) begin
prod_src_r <= src_color.r * src_factor.r;
prod_src_g <= src_color.g * src_factor.g;
prod_src_b <= src_color.b * src_factor.b;
prod_src_a <= src_color.a * src_factor.a;
// dst_color x dst_factor
`MULT8(clk, enable, prod_dst_r, dst_color.r, dst_factor.r);
`MULT8(clk, enable, prod_dst_g, dst_color.g, dst_factor.g);
`MULT8(clk, enable, prod_dst_b, dst_color.b, dst_factor.b);
`MULT8(clk, enable, prod_dst_a, dst_color.a, dst_factor.a);
prod_dst_r <= dst_color.r * dst_factor.r;
prod_dst_g <= dst_color.g * dst_factor.g;
prod_dst_b <= dst_color.b * dst_factor.b;
prod_dst_a <= dst_color.a * dst_factor.a;
reg [16:0] sum_r, sum_g, sum_b, sum_a;
// apply blend mode
always @(*) begin
case (mode_rgb)
`ROP_BLEND_MODE_ADD: begin
sum_r = prod_src_r + prod_dst_r + 16'hff;
sum_g = prod_src_g + prod_dst_g + 16'hff;
sum_b = prod_src_b + prod_dst_b + 16'hff;
end
`ROP_BLEND_MODE_SUB: begin
sum_r = prod_src_r - prod_dst_r + 16'hff;
sum_g = prod_src_g - prod_dst_g + 16'hff;
sum_b = prod_src_b - prod_dst_b + 16'hff;
end
`ROP_BLEND_MODE_REV_SUB: begin
sum_r = prod_dst_r - prod_src_r + 16'hff;
sum_g = prod_dst_g - prod_src_g + 16'hff;
sum_b = prod_dst_b - prod_src_b + 16'hff;
end
default: begin
sum_r = 'x;
sum_g = 'x;
sum_b = 'x;
end
endcase
case (mode_a)
`ROP_BLEND_MODE_ADD: begin
sum_a = prod_src_a + prod_dst_a + 16'hff;
end
`ROP_BLEND_MODE_SUB: begin
sum_a = prod_src_a - prod_dst_a + 16'hff;
end
`ROP_BLEND_MODE_REV_SUB: begin
sum_a = prod_dst_a - prod_src_a + 16'hff;
end
default: begin
sum_a = 'x;
end
endcase
case (mode_rgb)
`ROP_BLEND_MODE_ADD: begin
sum_r <= prod_src_r + prod_dst_r + 16'h80;
sum_g <= prod_src_g + prod_dst_g + 16'h80;
sum_b <= prod_src_b + prod_dst_b + 16'h80;
end
`ROP_BLEND_MODE_SUB: begin
sum_r <= prod_src_r - prod_dst_r + 16'h80;
sum_g <= prod_src_g - prod_dst_g + 16'h80;
sum_b <= prod_src_b - prod_dst_b + 16'h80;
end
`ROP_BLEND_MODE_REV_SUB: begin
sum_r <= prod_dst_r - prod_src_r + 16'h80;
sum_g <= prod_dst_g - prod_src_g + 16'h80;
sum_b <= prod_dst_b - prod_src_b + 16'h80;
end
endcase
case (mode_a)
`ROP_BLEND_MODE_ADD: begin
sum_a <= prod_src_a + prod_dst_a + 16'h80;
end
`ROP_BLEND_MODE_SUB: begin
sum_a <= prod_src_a - prod_dst_a + 16'h80;
end
`ROP_BLEND_MODE_REV_SUB: begin
sum_a <= prod_dst_a - prod_src_a + 16'h80;
end
endcase
end
end
// clamp to (0, 255 * 256)
reg [15:0] clamp_r, clamp_g, clamp_b, clamp_a;
// clamp to (0, 255 * 256)
always @(*) begin
case (mode_rgb)
`ROP_BLEND_MODE_ADD: begin
@ -132,18 +109,17 @@ module VX_rop_blend_multadd #(
endcase
end
rgba_t result;
// divide by 255
// divide by 255
rgba_t result;
assign result.r = 8'((clamp_r + (clamp_r >> 8)) >> 8);
assign result.g = 8'((clamp_g + (clamp_g >> 8)) >> 8);
assign result.b = 8'((clamp_b + (clamp_b >> 8)) >> 8);
assign result.a = 8'((clamp_a + (clamp_a >> 8)) >> 8);
VX_shift_register #(
.DATAW (32),
.DEPTH (LATENCY_REM)
) shift_reg (
VX_pipe_register #(
.DATAW (32)
) pipe_reg (
.clk (clk),
`UNUSED_PIN (reset),
.enable (enable),

4
hw/rtl/tex_unit/VX_tex_lerp.sv
View file

@ -13,7 +13,7 @@ module VX_tex_lerp (
`UNUSED_VAR (reset)
reg [15:0] p1, p2;
reg [16:0] sum;
reg [15:0] sum;
reg [7:0] res;
wire [7:0] sub = (8'hff - frac);
@ -22,7 +22,7 @@ module VX_tex_lerp (
if (enable) begin
p1 <= in1 * sub;
p2 <= in2 * frac;
sum <= p1 + p2 + 17'h80;
sum <= p1 + p2 + 16'h80;
res <= 8'((sum + (sum >> 8)) >> 8);
end
end

1
hw/rtl/tex_unit/VX_tex_sampler.sv
View file

@ -45,7 +45,6 @@ module VX_tex_sampler #(
VX_pipe_register #(
.DATAW (1 + REQ_INFOW + (NUM_LANES * 2 * `TEX_BLEND_FRAC) + (NUM_LANES * 4 * 32)),
.DEPTH (1),
.RESETW (1)
) pipe_reg0 (
.clk (clk),

4
hw/rtl/tex_unit/VX_tex_sat.sv
View file

@ -11,9 +11,9 @@ module VX_tex_sat #(
`STATIC_ASSERT(((OUT_W+1) < IN_W), ("invalid parameter"))
if (MODEL == 1) begin
wire [OUT_W-1:0] underflow_mask = {OUT_W{~data_in[IN_W-1]}};
wire [OUT_W-1:0] underflow_mask = {OUT_W{~data_in[IN_W-1]}};
wire [OUT_W-1:0] overflow_mask = {OUT_W{(| data_in[IN_W-2:OUT_W])}};
assign data_out = (data_in[OUT_W-1:0] | overflow_mask) & underflow_mask;
assign data_out = (data_in[OUT_W-1:0] & underflow_mask) | overflow_mask;
end else begin
assign data_out = data_in[IN_W-1] ? OUT_W'(0) : ((data_in > {OUT_W{1'b1}}) ? {OUT_W{1'b1}} : OUT_W'(data_in));
end

4
hw/scripts/gen_sources.sh
View file

@ -57,9 +57,9 @@ then
# dump macros into global header
for value in ${macros[@]}; do
arrNV=(${value//=/ })
if [ ${#arrNV[@]} > 1 ];
if (( ${#arrNV[@]} > 1 ));
then
echo "\`define ${arrNV[0]} ${arrNV[1]}"
echo "\`define ${arrNV[0]} ${arrNV[1]}"
else
echo "\`define $value"
fi

1
hw/syn/altera/.gitignore vendored Normal file
View file

@ -0,0 +1 @@
ip_cache/*

2
hw/syn/altera/opae/.gitignore vendored
View file

@ -1 +1 @@
build_*/
build_*/*

46
hw/syn/altera/opae/Makefile
View file

@ -33,21 +33,6 @@ DBG_TRACE_FLAGS += -DDBG_TRACE_ROP
DBG_FLAGS += $(DBG_TRACE_FLAGS)
CONFIGS += -DEXT_GFX_ENABLE
#CONFIGS += -DNUM_ROP_UNITS=2
#CONFIGS += -DNUM_TEX_UNITS=4
#CONFIGS += -DNUM_RASTER_UNITS=2
#CONFIGS += -DTCACHE_NUM_BANKS=1
#CONFIGS += -DOCACHE_NUM_BANKS=1
#CONFIGS += -DOCACHE_NUM_BANKS=1
#CONFIGS += -DL1_DISABLE
#CONFIGS += -DSM_DISABLE
#CONFIGS += -DRCACHE_DISABLE
#CONFIGS += -DOCACHE_DISABLE
#CONFIGS += -DTCACHE_DISABLE
ifeq ($(DEVICE_FAMILY), stratix10)
CONFIGS += -DALTERA_S10
endif
@ -55,13 +40,14 @@ ifeq ($(DEVICE_FAMILY), arria10)
CONFIGS += -DALTERA_A10
endif
CONFIGS1 := -DNUM_CLUSTERS=1 -DNUM_CORES=1 $(CONFIGS)
CONFIGS2 := -DNUM_CLUSTERS=1 -DNUM_CORES=2 $(CONFIGS)
CONFIGS4 := -DNUM_CLUSTERS=1 -DNUM_CORES=4 -DL2_ENABLE $(CONFIGS)
CONFIGS8 := -DNUM_CLUSTERS=1 -DNUM_CORES=8 -DL2_ENABLE $(CONFIGS)
CONFIGS16 := -DNUM_CLUSTERS=1 -DNUM_CORES=16 -DL2_ENABLE $(CONFIGS)
CONFIGS32 := -DNUM_CLUSTERS=2 -DNUM_CORES=16 -DL2_ENABLE $(CONFIGS)
CONFIGS64 := -DNUM_CLUSTERS=4 -DNUM_CORES=16 -DL2_ENABLE $(CONFIGS)
CONFIGS_1 := -DNUM_CLUSTERS=1 -DNUM_CORES=1 $(CONFIGS)
CONFIGS_2 := -DNUM_CLUSTERS=1 -DNUM_CORES=2 $(CONFIGS)
CONFIGS_4 := -DNUM_CLUSTERS=1 -DNUM_CORES=4 -DL2_ENABLE $(CONFIGS)
CONFIGS_8 := -DNUM_CLUSTERS=1 -DNUM_CORES=8 -DL2_ENABLE $(CONFIGS)
CONFIGS_16 := -DNUM_CLUSTERS=1 -DNUM_CORES=16 -DL2_ENABLE $(CONFIGS)
CONFIGS_32 := -DNUM_CLUSTERS=2 -DNUM_CORES=16 -DL2_ENABLE $(CONFIGS)
CONFIGS_64 := -DNUM_CLUSTERS=4 -DNUM_CORES=16 -DL2_ENABLE $(CONFIGS)
CONFIGS_SEL := $(CONFIGS_$(NUM_CORES))
FPU_INCLUDE = -I$(RTL_DIR)/fpu_unit
TEX_INCLUDE = -I$(RTL_DIR)/tex_unit
@ -103,21 +89,21 @@ swconfig: vortex_afu.h
vortex_afu.h: vortex_afu.json
afu_json_mgr json-info --afu-json=$^ --c-hdr=$@
gen-sources:
setup:
mkdir -p $(BUILD_DIR)/src
$(SCRIPT_DIR)/gen_sources.sh $(CFLAGS) $(CONFIGS$(NUM_CORES)) -F$(BUILD_DIR)/src -Osources.txt
rm -rf $(BUILD_DIR)
setup: gen-sources
ifeq ($(TARGET), ase)
$(SCRIPT_DIR)/gen_sources.sh $(CFLAGS) $(CONFIGS_SEL) -DSIMULATION -G$(BUILD_DIR)/src/globals.vh -F$(BUILD_DIR)/src -Osources.txt
rm -rf $(BUILD_DIR)
afu_sim_setup -s setup.cfg $(BUILD_DIR)
mkdir -p $(BUILD_DIR)/src
$(SCRIPT_DIR)/gen_sources.sh $(CFLAGS) $(CONFIGS$(NUM_CORES)) -DSIMULATION -G$(BUILD_DIR)/src/globals.vh -F$(BUILD_DIR)/src
$(SCRIPT_DIR)/gen_sources.sh $(CFLAGS) $(CONFIGS_SEL) -DSIMULATION -G$(BUILD_DIR)/src/globals.vh -F$(BUILD_DIR)/src
else
$(SCRIPT_DIR)/gen_sources.sh $(CFLAGS) $(CONFIGS_SEL) -G$(BUILD_DIR)/src/globals.vh -F$(BUILD_DIR)/src -Osources.txt
rm -rf $(BUILD_DIR)
afu_synth_setup -s setup.cfg $(BUILD_DIR)
mkdir -p $(BUILD_DIR)/src
$(SCRIPT_DIR)/gen_sources.sh $(CFLAGS) $(CONFIGS$(NUM_CORES)) -G$(BUILD_DIR)/src/globals.vh -F$(BUILD_DIR)/src
endif
$(SCRIPT_DIR)/gen_sources.sh $(CFLAGS) $(CONFIGS_SEL) -G$(BUILD_DIR)/src/globals.vh -F$(BUILD_DIR)/src
endif
# build