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https://github.com/vortexgpgpu/vortex.git
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minor update
This commit is contained in:
Blaise Tine
parent
0acf7761ef
commit
13d5a9c969
2 changed files with 55 additions and 54 deletions
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@ -1,10 +1,10 @@
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// Copyright © 2019-2023
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//
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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@ -21,7 +21,7 @@ module VX_fpu_fma import VX_fpu_pkg::*; #(
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parameter TAG_WIDTH = 1
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) (
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input wire clk,
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input wire reset,
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input wire reset,
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output wire ready_in,
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input wire valid_in,
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@ -29,7 +29,7 @@ module VX_fpu_fma import VX_fpu_pkg::*; #(
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input wire [NUM_LANES-1:0] mask_in,
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input wire [TAG_WIDTH-1:0] tag_in,
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input wire [`INST_FRM_BITS-1:0] frm,
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input wire is_madd,
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@ -39,7 +39,7 @@ module VX_fpu_fma import VX_fpu_pkg::*; #(
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input wire [NUM_LANES-1:0][31:0] dataa,
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input wire [NUM_LANES-1:0][31:0] datab,
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input wire [NUM_LANES-1:0][31:0] datac,
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output wire [NUM_LANES-1:0][31:0] result,
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output wire [NUM_LANES-1:0][31:0] result,
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output wire has_fflags,
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output wire [`FP_FLAGS_BITS-1:0] fflags,
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@ -52,11 +52,11 @@ module VX_fpu_fma import VX_fpu_pkg::*; #(
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`UNUSED_VAR (frm)
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wire [NUM_LANES-1:0][3*32-1:0] data_in;
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wire [NUM_LANES-1:0] mask_out;
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wire [NUM_LANES-1:0] mask_out;
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wire [NUM_LANES-1:0][(`FP_FLAGS_BITS+32)-1:0] data_out;
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wire [NUM_LANES-1:0][`FP_FLAGS_BITS-1:0] fflags_out;
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wire pe_enable;
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wire pe_enable;
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wire [NUM_PES-1:0][3*32-1:0] pe_data_in;
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wire [NUM_PES-1:0][(`FP_FLAGS_BITS+32)-1:0] pe_data_out;
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@ -66,7 +66,7 @@ module VX_fpu_fma import VX_fpu_pkg::*; #(
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always @(*) begin
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if (is_madd) begin
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// MADD / MSUB / NMADD / NMSUB
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a[i] = is_neg ? {~dataa[i][31], dataa[i][30:0]} : dataa[i];
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a[i] = is_neg ? {~dataa[i][31], dataa[i][30:0]} : dataa[i];
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b[i] = datab[i];
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c[i] = (is_neg ^ is_sub) ? {~datac[i][31], datac[i][30:0]} : datac[i];
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end else begin
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@ -81,7 +81,7 @@ module VX_fpu_fma import VX_fpu_pkg::*; #(
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b[i] = dataa[i];
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c[i] = is_sub ? {~datab[i][31], datab[i][30:0]} : datab[i];
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end
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end
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end
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end
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end
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@ -90,15 +90,15 @@ module VX_fpu_fma import VX_fpu_pkg::*; #(
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assign data_in[i][32 +: 32] = b[i];
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assign data_in[i][64 +: 32] = c[i];
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end
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VX_pe_serializer #(
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.NUM_LANES (NUM_LANES),
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.NUM_PES (NUM_PES),
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.NUM_LANES (NUM_LANES),
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.NUM_PES (NUM_PES),
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.LATENCY (`LATENCY_FMA),
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.DATA_IN_WIDTH(3*32),
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.DATA_OUT_WIDTH(`FP_FLAGS_BITS + 32),
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.TAG_WIDTH (NUM_LANES + TAG_WIDTH),
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.PE_REG (1)
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.PE_REG ((NUM_LANES != NUM_PES) ? 1 : 0)
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) pe_serializer (
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.clk (clk),
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.reset (reset),
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@ -123,7 +123,7 @@ module VX_fpu_fma import VX_fpu_pkg::*; #(
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fflags_t [NUM_LANES-1:0] per_lane_fflags;
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`ifdef QUARTUS
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for (genvar i = 0; i < NUM_PES; ++i) begin
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acl_fmadd fmadd (
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.clk (clk),
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@ -136,7 +136,7 @@ module VX_fpu_fma import VX_fpu_pkg::*; #(
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);
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assign pe_data_out[i][32 +: `FP_FLAGS_BITS] = 'x;
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end
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assign has_fflags = 0;
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assign per_lane_fflags = 'x;
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@ -144,7 +144,7 @@ module VX_fpu_fma import VX_fpu_pkg::*; #(
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for (genvar i = 0; i < NUM_PES; ++i) begin
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wire [2:0] tuser;
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xil_fma fma (
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.aclk (clk),
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.aclken (pe_enable),
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@ -172,15 +172,15 @@ module VX_fpu_fma import VX_fpu_pkg::*; #(
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`UNUSED_VAR (r)
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fflags_t f;
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always @(*) begin
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always @(*) begin
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dpi_fmadd (
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pe_enable,
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int'(0),
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{32'hffffffff, pe_data_in[i][0 +: 32]},
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{32'hffffffff, pe_data_in[i][32 +: 32]},
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{32'hffffffff, pe_data_in[i][64 +: 32]},
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frm,
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r,
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pe_enable,
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int'(0),
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{32'hffffffff, pe_data_in[i][0 +: 32]},
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{32'hffffffff, pe_data_in[i][32 +: 32]},
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{32'hffffffff, pe_data_in[i][64 +: 32]},
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frm,
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r,
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f
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);
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end
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@ -1,10 +1,10 @@
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// Copyright © 2019-2023
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//
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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@ -15,8 +15,8 @@
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`TRACING_OFF
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module VX_pe_serializer #(
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parameter NUM_LANES = 1,
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parameter NUM_PES = 1,
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parameter NUM_LANES = 1,
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parameter NUM_PES = 1,
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parameter LATENCY = 1,
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parameter DATA_IN_WIDTH = 1,
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parameter DATA_OUT_WIDTH = 1,
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@ -28,12 +28,12 @@ module VX_pe_serializer #(
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// input
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input wire valid_in,
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input wire [NUM_LANES-1:0][DATA_IN_WIDTH-1:0] data_in,
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input wire [NUM_LANES-1:0][DATA_IN_WIDTH-1:0] data_in,
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input wire [TAG_WIDTH-1:0] tag_in,
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output wire ready_in,
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// PE
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output wire pe_enable,
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output wire pe_enable,
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output wire [NUM_PES-1:0][DATA_IN_WIDTH-1:0] pe_data_in,
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input wire [NUM_PES-1:0][DATA_OUT_WIDTH-1:0] pe_data_out,
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@ -43,6 +43,7 @@ module VX_pe_serializer #(
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output wire [TAG_WIDTH-1:0] tag_out,
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input wire ready_out
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);
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wire [NUM_PES-1:0][DATA_IN_WIDTH-1:0] pe_data_in_s;
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wire valid_out_s;
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wire [TAG_WIDTH-1:0] tag_out_s;
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wire enable;
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@ -59,6 +60,17 @@ module VX_pe_serializer #(
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.data_out ({valid_out_s, tag_out_s})
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);
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VX_pipe_register #(
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.DATAW (NUM_PES * DATA_IN_WIDTH),
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.DEPTH (PE_REG)
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) pe_reg (
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.clk (clk),
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.reset (reset),
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.enable (enable),
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.data_in (pe_data_in_s),
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.data_out (pe_data_in)
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);
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if (NUM_LANES != NUM_PES) begin
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localparam BATCH_SIZE = NUM_LANES / NUM_PES;
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@ -67,6 +79,10 @@ module VX_pe_serializer #(
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reg [BATCH_SIZEW-1:0] batch_in_idx;
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reg [BATCH_SIZEW-1:0] batch_out_idx;
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for (genvar i = 0; i < NUM_PES; ++i) begin
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assign pe_data_in_s[i] = data_in[batch_in_idx * NUM_PES + i];
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end
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always @(posedge clk) begin
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if (reset) begin
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batch_in_idx <= '0;
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@ -81,30 +97,14 @@ module VX_pe_serializer #(
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end
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end
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wire batch_in_done = (batch_in_idx == BATCH_SIZEW'(BATCH_SIZE-1));
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wire batch_in_done = (batch_in_idx == BATCH_SIZEW'(BATCH_SIZE-1));
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wire batch_out_done = (batch_out_idx == BATCH_SIZEW'(BATCH_SIZE-1));
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wire [NUM_PES-1:0][DATA_IN_WIDTH-1:0] pe_data_in_s;
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for (genvar i = 0; i < NUM_PES; ++i) begin
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assign pe_data_in_s[i] = data_in[batch_in_idx * NUM_PES + i];
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end
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VX_pipe_register #(
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.DATAW (NUM_PES * DATA_IN_WIDTH),
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.DEPTH (PE_REG)
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) pe_reg (
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.clk (clk),
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.reset (reset),
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.enable (enable),
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.data_in (pe_data_in_s),
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.data_out (pe_data_in)
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);
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reg valid_out_r;
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reg [BATCH_SIZE-1:0][NUM_PES-1:0][DATA_OUT_WIDTH-1:0] data_out_r;
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reg [TAG_WIDTH-1:0] tag_out_r;
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wire valid_out_b = valid_out_s && batch_out_done;
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wire valid_out_b = valid_out_s && batch_out_done;
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wire enable_r = ready_out || ~valid_out;
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always @(posedge clk) begin
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@ -113,13 +113,13 @@ module VX_pe_serializer #(
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end else if (enable_r) begin
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valid_out_r <= valid_out_b;
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end
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if (enable_r) begin
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if (enable_r) begin
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data_out_r[batch_out_idx] <= pe_data_out;
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tag_out_r <= tag_out_s;
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end
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end
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assign enable = (enable_r || ~valid_out_b);
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assign enable = enable_r || ~valid_out_b;
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assign ready_in = enable && batch_in_done;
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assign pe_enable = enable;
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@ -130,16 +130,17 @@ module VX_pe_serializer #(
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end else begin
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assign pe_data_in_s = data_in;
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assign enable = ready_out || ~valid_out;
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assign ready_in = enable;
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assign pe_enable = enable;
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assign pe_data_in= data_in;
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assign valid_out = valid_out_s;
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assign valid_out = valid_out_s;
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assign data_out = pe_data_out;
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assign tag_out = tag_out_s;
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end
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endmodule
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