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minor update

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This commit is contained in:
Blaise Tine 2023-07-04 12:54:44 -04:00
parent 0e96575b76
commit 13f577acd6
5 changed files with 37 additions and 49 deletions
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2
hw/rtl/core/VX_fetch.sv
View file

@ -62,7 +62,7 @@ module VX_fetch #(
// Ensure that the ibuffer doesn't fill up.
// This resolves potential deadlock if ibuffer fills and the LSU stalls the execute stage due to pending dcache request.
// This issue is particularly prevalent when the icache and dcache is disabled and both requests share the same bus.
wire [`NUM_WARPS-1:0] pending_ibuf_full = 0;
wire [`NUM_WARPS-1:0] pending_ibuf_full;
for (genvar i = 0; i < `NUM_WARPS; ++i) begin
VX_pending_size #(
.SIZE (`IBUF_SIZE + 1)

37
hw/rtl/core/VX_issue.sv
View file

@ -26,30 +26,10 @@ module VX_issue #(
`endif
VX_gpu_exe_if.master gpu_exe_if
);
VX_ibuffer_if ibuffer_if();
VX_ibuffer_if ibuffer_if();
VX_gpr_stage_if gpr_stage_if();
VX_writeback_if sboard_wb_if();
VX_scoreboard_if scoreboard_if();
VX_dispatch_if dispatch_if();
wire [3:0] in_use_regs;
// GPR request interface
assign gpr_stage_if.wid = ibuffer_if.wid;
assign gpr_stage_if.rs1 = ibuffer_if.rs1;
assign gpr_stage_if.rs2 = ibuffer_if.rs2;
assign gpr_stage_if.rs3 = ibuffer_if.rs3;
// scoreboard writeback interface
assign sboard_wb_if.valid = writeback_if.valid;
assign sboard_wb_if.uuid = writeback_if.uuid;
assign sboard_wb_if.wid = writeback_if.wid;
assign sboard_wb_if.tmask = writeback_if.tmask;
assign sboard_wb_if.PC = writeback_if.PC;
assign sboard_wb_if.rd = writeback_if.rd;
assign sboard_wb_if.data = writeback_if.data;
assign sboard_wb_if.eop = writeback_if.eop;
`UNUSED_VAR (sboard_wb_if.ready)
// scoreboard interface
assign scoreboard_if.valid = ibuffer_if.valid && dispatch_if.ready;
@ -64,6 +44,12 @@ module VX_issue #(
assign scoreboard_if.rs2_n = ibuffer_if.rs2_n;
assign scoreboard_if.rs3_n = ibuffer_if.rs3_n;
assign scoreboard_if.wid_n = ibuffer_if.wid_n;
// GPR request interface
assign gpr_stage_if.wid = ibuffer_if.wid;
assign gpr_stage_if.rs1 = ibuffer_if.rs1;
assign gpr_stage_if.rs2 = ibuffer_if.rs2;
assign gpr_stage_if.rs3 = ibuffer_if.rs3;
// dispatch interface
assign dispatch_if.valid = ibuffer_if.valid && scoreboard_if.ready;
@ -106,8 +92,7 @@ module VX_issue #(
.clk (clk),
.reset (scoreboard_reset),
.writeback_if (writeback_if),
.scoreboard_if (scoreboard_if),
.in_use_regs (in_use_regs)
.scoreboard_if (scoreboard_if)
);
VX_gpr_stage #(
@ -143,7 +128,7 @@ module VX_issue #(
`ifdef DBG_TRACE_CORE_PIPELINE
`TRACE(3, ("%d: *** core%0d-stall: wid=%0d, PC=0x%0h, tmask=%b, rd=%0d, wb=%0d, cycles=%0d, inuse=%b%b%b%b, dispatch=%b (#%0d)\n",
$time, CORE_ID, ibuffer_if.wid, ibuffer_if.PC, ibuffer_if.tmask, ibuffer_if.rd, ibuffer_if.wb, timeout_ctr,
in_use_regs[0], in_use_regs[1], in_use_regs[2], in_use_regs[3], ~dispatch_if.ready, ibuffer_if.uuid));
scoreboard_if.used_regs[0], scoreboard_if.used_regs[1], scoreboard_if.used_regs[2], scoreboard_if.used_regs[3], ~dispatch_if.ready, ibuffer_if.uuid));
`endif
timeout_ctr <= timeout_ctr + 1;
end else if (ibuffer_if_fire) begin
@ -154,7 +139,7 @@ module VX_issue #(
`RUNTIME_ASSERT(timeout_ctr < `STALL_TIMEOUT,
("%t: *** core%0d-issue-timeout: wid=%0d, PC=0x%0h, tmask=%b, rd=%0d, wb=%0d, inuse=%b%b%b%b, dispatch=%b (#%0d)",
$time, CORE_ID, ibuffer_if.wid, ibuffer_if.PC, ibuffer_if.tmask, ibuffer_if.rd, ibuffer_if.wb,
in_use_regs[0], in_use_regs[1], in_use_regs[2], in_use_regs[3], ~dispatch_if.ready, ibuffer_if.uuid));
scoreboard_if.used_regs[0], scoreboard_if.used_regs[1], scoreboard_if.used_regs[2], scoreboard_if.used_regs[3], ~dispatch_if.ready, ibuffer_if.uuid));
`ifdef DBG_SCOPE_ISSUE
if (CORE_ID == 0) begin
@ -211,7 +196,7 @@ module VX_issue #(
`ifdef CHIPSCOPE
ila_issue ila_issue_inst (
.clk (clk),
.probe0 ({ibuffer_if.uuid, ibuffer.rs3, ibuffer.rs2, ibuffer.rs1, ibuffer_if.PC, ibuffer_if.tmask, ibuffer_if.wid, ibuffer_if.ex_type, ibuffer_if.op_type, ibuffer_if.ready, ibuffer_if.valid, in_use_regs, scoreboard_if.ready, dispatch_if.ready, ibuffer_if.ready, ibuffer_if.valid}),
.probe0 ({ibuffer_if.uuid, ibuffer.rs3, ibuffer.rs2, ibuffer.rs1, ibuffer_if.PC, ibuffer_if.tmask, ibuffer_if.wid, ibuffer_if.ex_type, ibuffer_if.op_type, ibuffer_if.ready, ibuffer_if.valid, scoreboard_if.used_regs, scoreboard_if.ready, dispatch_if.ready, ibuffer_if.ready, ibuffer_if.valid}),
.probe1 ({writeback_if.uuid, writeback_if.data[0], writeback_if.PC, writeback_if.tmask, writeback_if.wid, writeback_if.eop, writeback_if.valid})
);
`endif

20
hw/rtl/core/VX_scoreboard.sv
View file

@ -7,13 +7,11 @@ module VX_scoreboard #(
input wire reset,
VX_scoreboard_if.slave scoreboard_if,
VX_writeback_if.slave writeback_if,
output wire [3:0] in_use_regs
VX_writeback_if.slave writeback_if
);
reg [`NUM_WARPS-1:0][`NUM_REGS-1:0] inuse_regs, inuse_regs_n;
wire reserve_reg = scoreboard_if.valid && scoreboard_if.ready && scoreboard_if.wb;
wire release_reg = writeback_if.valid && writeback_if.ready && writeback_if.eop;
always @(*) begin
@ -46,20 +44,20 @@ module VX_scoreboard #(
assign writeback_if.ready = 1'b1;
assign scoreboard_if.ready = ~(deq_inuse_rd
| deq_inuse_rs1
| deq_inuse_rs2
| deq_inuse_rs3);
| deq_inuse_rs1
| deq_inuse_rs2
| deq_inuse_rs3);
assign scoreboard_if.used_regs[0] = deq_inuse_rd;
assign scoreboard_if.used_regs[1] = deq_inuse_rs1;
assign scoreboard_if.used_regs[2] = deq_inuse_rs2;
assign scoreboard_if.used_regs[3] = deq_inuse_rs3;
`UNUSED_VAR (writeback_if.PC)
`UNUSED_VAR (scoreboard_if.PC)
`UNUSED_VAR (scoreboard_if.tmask)
`UNUSED_VAR (scoreboard_if.uuid)
assign in_use_regs[0] = deq_inuse_rd;
assign in_use_regs[1] = deq_inuse_rs1;
assign in_use_regs[2] = deq_inuse_rs2;
assign in_use_regs[3] = deq_inuse_rs3;
always @(posedge clk) begin
if (release_reg) begin
`ASSERT(inuse_regs[writeback_if.wid][writeback_if.rd] != 0,

19
hw/rtl/core/VX_writeback.sv
View file

@ -23,9 +23,10 @@ module VX_writeback #(
);
`UNUSED_PARAM (CORE_ID)
localparam NW_WIDTH = `UP(`NW_BITS);
localparam DATAW = NW_WIDTH + `XLEN + `NUM_THREADS + `NR_BITS + (`NUM_THREADS * `XLEN) + 1;
localparam NUM_RSPS = 4 + `EXT_F_ENABLED;
localparam UUID_WIDTH = `UP(`UUID_BITS);
localparam NW_WIDTH = `UP(`NW_BITS);
localparam DATAW = UUID_WIDTH + NW_WIDTH + `XLEN + `NUM_THREADS + `NR_BITS + (`NUM_THREADS * `XLEN) + 1;
localparam NUM_RSPS = 4 + `EXT_F_ENABLED;
`ifdef EXT_F_ENABLE
wire wb_fpu_ready_in;
@ -63,14 +64,14 @@ module VX_writeback #(
}),
.data_in ({
`ifdef EXT_F_ENABLE
{fpu_commit_if.wid, fpu_commit_if.PC, fpu_commit_if.tmask, fpu_commit_if.rd, fpu_commit_if.data, fpu_commit_if.eop},
{fpu_commit_if.uuid, fpu_commit_if.wid, fpu_commit_if.PC, fpu_commit_if.tmask, fpu_commit_if.rd, fpu_commit_if.data, fpu_commit_if.eop},
`endif
{gpu_commit_if.wid, gpu_commit_if.PC, gpu_commit_if.tmask, gpu_commit_if.rd, gpu_commit_if.data, gpu_commit_if.eop},
{csr_commit_if.wid, csr_commit_if.PC, csr_commit_if.tmask, csr_commit_if.rd, csr_commit_if.data, csr_commit_if.eop},
{alu_commit_if.wid, alu_commit_if.PC, alu_commit_if.tmask, alu_commit_if.rd, alu_commit_if.data, alu_commit_if.eop},
{ld_commit_if.wid, ld_commit_if.PC, ld_commit_if.tmask, ld_commit_if.rd, ld_commit_if.data, ld_commit_if.eop}
{gpu_commit_if.uuid, gpu_commit_if.wid, gpu_commit_if.PC, gpu_commit_if.tmask, gpu_commit_if.rd, gpu_commit_if.data, gpu_commit_if.eop},
{csr_commit_if.uuid, csr_commit_if.wid, csr_commit_if.PC, csr_commit_if.tmask, csr_commit_if.rd, csr_commit_if.data, csr_commit_if.eop},
{alu_commit_if.uuid, alu_commit_if.wid, alu_commit_if.PC, alu_commit_if.tmask, alu_commit_if.rd, alu_commit_if.data, alu_commit_if.eop},
{ld_commit_if.uuid, ld_commit_if.wid, ld_commit_if.PC, ld_commit_if.tmask, ld_commit_if.rd, ld_commit_if.data, ld_commit_if.eop}
}),
.data_out ({writeback_if.wid, writeback_if.PC, writeback_if.tmask, writeback_if.rd, writeback_if.data, writeback_if.eop}),
.data_out ({writeback_if.uuid, writeback_if.wid, writeback_if.PC, writeback_if.tmask, writeback_if.rd, writeback_if.data, writeback_if.eop}),
.valid_out (writeback_if.valid),
.ready_out (writeback_if.ready)
);

8
hw/rtl/interfaces/VX_scoreboard_if.sv
View file

@ -16,6 +16,8 @@ interface VX_scoreboard_if ();
wire [`NR_BITS-1:0] rs3_n;
wire [`UP(`NW_BITS)-1:0] wid_n;
wire [3:0] used_regs;
wire ready;
modport master (
@ -30,7 +32,8 @@ interface VX_scoreboard_if ();
output rs1_n,
output rs2_n,
output rs3_n,
output wid_n,
output wid_n,
input used_regs,
input ready
);
@ -46,7 +49,8 @@ interface VX_scoreboard_if ();
input rs1_n,
input rs2_n,
input rs3_n,
input wid_n,
input wid_n,
output used_regs,
output ready
);