texunit tex_wrap

hw/rtl/VX_define.vh

@@ -16,6 +16,8 @@
 
 `define REQS_BITS       `LOG2UP(NUM_REQS)
 
+`define NTEX_BITS       `LOG2UP(`NUM_TEX_UNITS)
+
 `ifdef EXT_F_ENABLE
 `define NUM_REGS        64
 `else
@@ -387,19 +389,7 @@
 
 `define XDRAM_TAG_WIDTH         (`DDRAM_TAG_WIDTH+`CLOG2(2))
 
-////////////////////////// Texture Unit Configurable Knobs //////////////////////////////
-
-`define NTEX_BITS        `LOG2UP(`NUM_TEX_UNITS)
-
-`define TEX_ADDR_BITS    32
-`define TEX_FORMAT_BITS  3
-`define TEX_WRAP_BITS    2
-`define TEX_WIDTH_BITS   12
-`define TEX_HEIGHT_BITS  12
-`define TEX_STRIDE_BITS  2
-`define TEX_FILTER_BITS  1
-
-////////////////////////////////////////////////////////////////////////////////////////
+///////////////////////////////////////////////////////////////////////////////
 
 `include "VX_types.vh"
 

hw/rtl/cache/VX_bank.v

@@ -1,4 +1,4 @@
-`include "VX_cache_config.vh"
+`include "VX_cache_define.vh"
 
 module VX_bank #(
     parameter CACHE_ID                      = 0,

hw/rtl/cache/VX_cache.v

@@ -1,4 +1,4 @@
-`include "VX_cache_config.vh"
+`include "VX_cache_define.vh"
 
 module VX_cache #(
     parameter CACHE_ID                      = 0,

hw/rtl/cache/VX_cache_core_req_bank_sel.v

@@ -1,4 +1,4 @@
-`include "VX_cache_config.vh"
+`include "VX_cache_define.vh"
 
 module VX_cache_core_req_bank_sel #(  
     // Size of line inside a bank in bytes

hw/rtl/cache/VX_cache_core_rsp_merge.v

@@ -1,4 +1,4 @@
-`include "VX_cache_config.vh"
+`include "VX_cache_define.vh"
 
 module VX_cache_core_rsp_merge #(
     // Number of Word requests per cycle

hw/rtl/cache/VX_cache_define.vh

@@ -1,5 +1,5 @@
-`ifndef VX_CACHE_CONFIG
-`define VX_CACHE_CONFIG
+`ifndef VX_CACHE_DEFINE
+`define VX_CACHE_DEFINE
 
 `include "VX_platform.vh"
 

hw/rtl/cache/VX_data_access.v

@@ -1,4 +1,4 @@
-`include "VX_cache_config.vh"
+`include "VX_cache_define.vh"
 
 module VX_data_access #(
     parameter CACHE_ID          = 0,

hw/rtl/cache/VX_flush_ctrl.v

@@ -1,4 +1,4 @@
-`include "VX_cache_config.vh"
+`include "VX_cache_define.vh"
 
 module VX_flush_ctrl #(
     // Size of cache in bytes

hw/rtl/cache/VX_miss_resrv.v

@@ -1,4 +1,4 @@
-`include "VX_cache_config.vh"
+`include "VX_cache_define.vh"
 
 module VX_miss_resrv #(
     parameter CACHE_ID          = 0,

hw/rtl/cache/VX_shared_mem.v

@@ -1,4 +1,4 @@
-`include "VX_cache_config.vh"
+`include "VX_cache_define.vh"
 
 module VX_shared_mem #(
     parameter CACHE_ID                      = 0,

hw/rtl/cache/VX_tag_access.v

@@ -1,4 +1,4 @@
-`include "VX_cache_config.vh"
+`include "VX_cache_define.vh"
 
 module VX_tag_access #(
     parameter CACHE_ID          = 0,

hw/rtl/interfaces/VX_cache_dram_req_if.v

@@ -1,7 +1,7 @@
 `ifndef VX_CACHE_DRAM_REQ_IF
 `define VX_CACHE_DRAM_REQ_IF
 
-`include "../cache/VX_cache_config.vh"
+`include "../cache/VX_cache_define.vh"
 
 interface VX_cache_dram_req_if #(
     parameter DRAM_LINE_WIDTH = 1,

hw/rtl/interfaces/VX_cache_dram_rsp_if.v

@@ -1,7 +1,7 @@
 `ifndef VX_CACHE_DRAM_RSP_IF
 `define VX_CACHE_DRAM_RSP_IF
 
-`include "../cache/VX_cache_config.vh"
+`include "../cache/VX_cache_define.vh"
 
 interface VX_cache_dram_rsp_if #(
     parameter DRAM_LINE_WIDTH = 1,

hw/rtl/interfaces/VX_dcache_core_req_if.v

@@ -1,7 +1,7 @@
 `ifndef VX_DCACHE_CORE_REQ_IF
 `define VX_DCACHE_CORE_REQ_IF
 
-`include "../cache/VX_cache_config.vh"
+`include "../cache/VX_cache_define.vh"
 
 interface VX_dcache_core_req_if #(
     parameter LANES          = 1,

hw/rtl/interfaces/VX_dcache_core_rsp_if.v

@@ -1,7 +1,7 @@
 `ifndef VX_DCACHE_CORE_RSP_IF
 `define VX_DCACHE_CORE_RSP_IF
 
-`include "../cache/VX_cache_config.vh"
+`include "../cache/VX_cache_define.vh"
 
 interface VX_dcache_core_rsp_if #(
     parameter LANES          = 1,

hw/rtl/interfaces/VX_icache_core_req_if.v

@@ -1,7 +1,7 @@
 `ifndef VX_ICACHE_CORE_REQ_IF
 `define VX_ICACHE_CORE_REQ_IF
 
-`include "../cache/VX_cache_config.vh"
+`include "../cache/VX_cache_define.vh"
 
 interface VX_icache_core_req_if #(
     parameter WORD_SIZE      = 1,

hw/rtl/interfaces/VX_icache_core_rsp_if.v

@@ -1,7 +1,7 @@
 `ifndef VX_ICACHE_CORE_RSP_IF
 `define VX_ICACHE_CORE_RSP_IF
 
-`include "../cache/VX_cache_config.vh"
+`include "../cache/VX_cache_define.vh"
 
 interface VX_icache_core_rsp_if #(
     parameter WORD_SIZE      = 1,

hw/rtl/tex_unit/VX_tex_addr_gen.v

@@ -1,10 +1,8 @@
-`include "VX_define.vh"
+`include "VX_tex_define.vh"
 
 module VX_tex_addr_gen #(
-    parameter CORE_ID   = 0,
-    parameter REQ_TAG_WIDTH = 1,
-    parameter FRAC_BITS = 20,
-    parameter INT_BITS  = 32 - FRAC_BITS
+    parameter CORE_ID = 0,
+    parameter REQ_TAG_WIDTH = 1
 ) (
     input wire  clk,
     input wire  reset,
@@ -16,17 +14,17 @@ module VX_tex_addr_gen #(
 
     // inputs
 
-    input wire [`NUM_THREADS-1:0]    req_tmask,
-    input wire [REQ_TAG_WIDTH-1:0]   req_tag,
+    input wire [`NUM_THREADS-1:0]       req_tmask,
+    input wire [REQ_TAG_WIDTH-1:0]      req_tag,
 
-    input wire [`TEX_FILTER_BITS-1:0] filter,
-    input wire [`TEX_WRAP_BITS-1:0]   wrap_u,
-    input wire [`TEX_WRAP_BITS-1:0]   wrap_v,
+    input wire [`TEX_FILTER_BITS-1:0]   filter,
+    input wire [`TEX_WRAP_BITS-1:0]     wrap_u,
+    input wire [`TEX_WRAP_BITS-1:0]     wrap_v,
 
-    input wire [`TEX_ADDR_BITS-1:0]   base_addr,
-    input wire [`TEX_STRIDE_BITS-1:0] log2_stride,
-    input wire [`TEX_WIDTH_BITS-1:0]  log2_width,
-    input wire [`TEX_HEIGHT_BITS-1:0] log2_height,
+    input wire [`TEX_ADDR_BITS-1:0]     base_addr,
+    input wire [`TEX_STRIDE_BITS-1:0]   log2_stride,
+    input wire [`TEX_WIDTH_BITS-1:0]    log2_width,
+    input wire [`TEX_HEIGHT_BITS-1:0]   log2_height,
     
     input wire [`NUM_THREADS-1:0][31:0] coord_u,
     input wire [`NUM_THREADS-1:0][31:0] coord_v,
@@ -43,23 +41,44 @@ module VX_tex_addr_gen #(
 );
 
     `UNUSED_PARAM (CORE_ID)
-
-    /*`UNUSED_VAR (filter)
     `UNUSED_VAR (lod)
 
-    wire [31:0]  u, y;
-    wire [31:0]  x_offset, y_offset;
-    wire [31:0]  addr0;
+    for (genvar i = 0; i < `NUM_THREADS; ++i) begin
 
-    // addressing mode
+        // addressing mode
+        
+        wire [31:0] u, v;
 
+        VX_tex_wrap #(
+            .CORE_ID (CORE_ID)
+        ) tex_wrap_u (
+            .wrap_i  (wrap_u),
+            .coord_i (coord_u[i]),
+            .coord_o (u)
+        );
 
-    assign x_offset = u >> (5'(FRAC_BITS) - log2_width); 
-    assign y_offset = v >> (5'(FRAC_BITS) - log2_height); 
-    assign addr0 = base_addr + (x_offset + (y_offset << log2_width)) << log2_stride;
+        VX_tex_wrap #(
+            .CORE_ID (CORE_ID)
+        ) tex_wrap_v (
+            .wrap_i  (wrap_v),
+            .coord_i (coord_v[i]),
+            .coord_o (v)
+        );
 
-    wire [3:0]       req_valids  = 4'(valid_in);
-    wire [3:0][31:0] req_address = {4{addr0}};
+        // texel addresses generation
+
+        wire [31:0]  x_offset, y_offset;
+        wire [31:0]  addr0;
+
+        assign x_offset = u >> (5'(`FIXED_FRAC) - log2_width); 
+        assign y_offset = v >> (5'(`FIXED_FRAC) - log2_height); 
+        assign addr0 = base_addr + (x_offset + (y_offset << log2_width)) << log2_stride;
+
+        wire [3:0]       req_valids  = 4'(valid_in);
+        wire [3:0][31:0] req_address = {4{addr0}};
+    end
+
+    wire stall_out = mem_req_valid && ~mem_req_ready;
 
     VX_pipe_register #(
         .DATAW  (1 + 4 + 4 * 32 + REQ_TAG_WIDTH),
@@ -72,6 +91,6 @@ module VX_tex_addr_gen #(
         .data_out ({mem_req_valid, mem_req_addr, mem_req_tag})
     );
 
-    assign ready_in = ~stall_out;*/
+    assign ready_in = ~stall_out;
 
 endmodule

hw/rtl/tex_unit/VX_tex_define.vh

@@ -0,0 +1,25 @@
+`ifndef VX_TEX_DEFINE
+`define VX_TEX_DEFINE
+
+`include "VX_define.vh"
+
+`define FIXED_FRAC      20
+`define FIXED_INT       (32 - `FIXED_FRAC)
+`define FIXED_ONE       (1 << `FIXED_FRAC)
+`define FIXED_MASK      (`FIXED_ONE - 1)
+
+`define CLAMP(x,lo,hi)  ((x < lo) ? lo : ((x > hi) ? hi : x))
+
+`define TEX_ADDR_BITS    32
+`define TEX_FORMAT_BITS  3
+`define TEX_WRAP_BITS    2
+`define TEX_WIDTH_BITS   12
+`define TEX_HEIGHT_BITS  12
+`define TEX_STRIDE_BITS  2
+`define TEX_FILTER_BITS  1
+
+`define TEX_WRAP_REPEAT  0
+`define TEX_WRAP_CLAMP   1
+`define TEX_WRAP_MIRROR  2
+
+`endif

hw/rtl/tex_unit/VX_tex_format.v

@@ -1,8 +1,10 @@
+`include "VX_tex_define.vh"
+
 module VX_tex_format #(
     parameter CORE_ID = 0
 ) (
     // TODO
-)   
+);  
     `UNUSED_PARAM (CORE_ID)
     
     // TODO

hw/rtl/tex_unit/VX_tex_memory.v

@@ -1,4 +1,4 @@
-`include "VX_define.vh"
+`include "VX_tex_define.vh"
 
 module VX_tex_memory #(
     parameter CORE_ID       = 0,

hw/rtl/tex_unit/VX_tex_sampler.v

@@ -1,4 +1,4 @@
-`include "VX_define.vh"
+`include "VX_tex_define.vh"
 
 module VX_tex_sampler #(
     parameter CORE_ID = 0    

hw/rtl/tex_unit/VX_tex_unit.v

@@ -1,5 +1,4 @@
-`include "VX_platform.vh"
-`include "VX_define.vh"
+`include "VX_tex_define.vh"
 
 module VX_tex_unit #(  
     parameter CORE_ID = 0
@@ -83,7 +82,6 @@ module VX_tex_unit #(
     wire mem_rsp_ready;
                 
     VX_tex_addr_gen #(
-        .FRAC_BITS     (20),
         .REQ_TAG_WIDTH (REQ_TAG_WIDTH)
     ) tex_addr_gen (
         .clk            (clk),

hw/rtl/tex_unit/VX_tex_wrap.v

@@ -1,25 +1,49 @@
-`include "VX_define.vh"
+`include "VX_tex_define.vh"
+
+/*
+switch(addressing_mode) {
+case undefined:       return is_undefined;
+case clamp_to_edge:   return intdowni(max(0, min(coord, coorddim - 1)));
+case clamp_to_border: return is_border;
+case repeat:
+    tile = intdowni(coord / coorddim);
+    return intdowni(coord - (tile * coorddim));
+case mirrored_repeat:
+    mirrored_coord = (coord < 0) ? (-coord - 1) : coord;
+    tile = intdowni(mirrored_coord / coorddim);
+    mirrored_coord = intdowni(mirrored_coord - (tile * coorddim));
+    if (tile & 1) {
+        mirrored_coord = (coorddim - 1) - mirrored_coord;
+    }
+    return mirrored_coord;
+}
+*/
 
 module VX_tex_wrap #(
-    parameter CORE_ID   = 0,
-    parameter FRAC_BITS = 20,
-    parameter INT_BITS  = 32 - FRAC_BITS
+    parameter CORE_ID = 0    
 ) (
-    input wire [`TEX_WRAP_BITS-1:0] wrap_i;
+    input wire [`TEX_WRAP_BITS-1:0] wrap_i,
     input wire [31:0] coord_i,
-    input wire [31:0] coord_o
-)
+    input wire [`FIXED_FRAC-1:0] coord_o
+);
     
     `UNUSED_PARAM (CORE_ID)
 
-    /*always @(*) begin
+    reg [31:0] coord_r;
+
+    wire [31:0] clamp = `CLAMP(coord_i, 0, `FIXED_MASK);
+
+    always @(*) begin
         case (wrap_i)
-            `ALU_AND:   msc_result[i] = alu_in1[i] & alu_in2_imm[i];
-            `ALU_OR:    msc_result[i] = alu_in1[i] | alu_in2_imm[i];
-            `ALU_XOR:   msc_result[i] = alu_in1[i] ^ alu_in2_imm[i];                
-            //`ALU_SLL,
-            default:    msc_result[i] = alu_in1[i] << alu_in2_imm[i][4:0];
+            `TEX_WRAP_CLAMP:   
+                coord_r = clamp[`FIXED_FRAC-1:0];
+            `TEX_WRAP_MIRROR: 
+                coord_r = coord_i[`FIXED_FRAC-1:0] ^ {`FIXED_FRAC{coord_i[`FIXED_FRAC]}};
+            default: //`TEX_WRAP_REPEAT
+                coord_r = coord_i[`FIXED_FRAC-1:0];
         endcase
-    end*/
+    end
+
+    assign coord_o = coord_r;
 
 endmodule