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minor update

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This commit is contained in:
Blaise Tine 2024-08-12 20:07:50 -07:00
parent 2edda834c3
commit 14ae4b8c13
3 changed files with 11 additions and 17 deletions
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7
hw/rtl/cache/VX_bank_flush.sv vendored
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@ -114,12 +114,7 @@ module VX_bank_flush #(
assign flush_line = counter_r[`CS_LINE_SEL_BITS-1:0];
if (WRITEBACK && `CS_WAY_SEL_BITS > 0) begin
reg [NUM_WAYS-1:0] flush_way_r;
always @(*) begin
flush_way_r = '0;
flush_way_r[counter_r[`CS_LINE_SEL_BITS +: `CS_WAY_SEL_BITS]] = 1;
end
assign flush_way = flush_way_r;
assign flush_way = NUM_WAYS'(1) << counter_r[`CS_LINE_SEL_BITS +: `CS_WAY_SEL_BITS];
end else begin
assign flush_way = {NUM_WAYS{1'b1}};
end

10
hw/rtl/libs/VX_mem_coalescer.sv
View file

@ -168,12 +168,8 @@ module VX_mem_coalescer #(
for (integer i = 0; i < OUT_REQS; ++i) begin
for (integer j = 0; j < DATA_RATIO; ++j) begin
if (current_pmask[i * DATA_RATIO + j]) begin
for (integer k = 0; k < DATA_IN_SIZE; ++k) begin
if (in_req_byteen[DATA_RATIO * i + j][k]) begin
req_byteen_merged[i][in_addr_offset[DATA_RATIO * i + j]][k] = 1'b1;
req_data_merged[i][in_addr_offset[DATA_RATIO * i + j]][k * 8 +: 8] = in_req_data[DATA_RATIO * i + j][k * 8 +: 8];
end
end
req_byteen_merged[i][in_addr_offset[DATA_RATIO * i + j]] = in_req_byteen[DATA_RATIO * i + j];
req_data_merged[i][in_addr_offset[DATA_RATIO * i + j]] = in_req_data[DATA_RATIO * i + j];
end
end
end
@ -216,7 +212,7 @@ module VX_mem_coalescer #(
out_req_byteen_n= req_byteen_merged;
out_req_data_n = req_data_merged;
out_req_tag_n = {in_req_tag[TAG_WIDTH-1 -: UUID_WIDTH], ibuf_waddr};
processed_mask_n= is_last_batch ? '0 (processed_mask_r | current_pmask);
processed_mask_n= is_last_batch ? '0 : (processed_mask_r | current_pmask);
in_req_ready_n = is_last_batch;
end
endcase

11
hw/rtl/libs/VX_priority_encoder.sv
View file

@ -73,11 +73,14 @@ module VX_priority_encoder #(
end else if (MODEL == 2) begin
`IGNORE_WARNINGS_BEGIN
`IGNORE_UNOPTFLAT_BEGIN
wire [N-1:0] higher_pri_regs;
`IGNORE_WARNINGS_END
assign higher_pri_regs[N-1:1] = higher_pri_regs[N-2:0] | reversed[N-2:0];
assign higher_pri_regs[0] = 1'b0;
`IGNORE_UNOPTFLAT_END
assign higher_pri_regs[0] = 1'b0;
for (genvar i = 1; i < N; ++i) begin
assign higher_pri_regs[i] = higher_pri_regs[i-1] | reversed[i-1];
end
assign onehot_out[N-1:0] = reversed[N-1:0] & ~higher_pri_regs[N-1:0];
VX_lzc #(