mirror of
https://github.com/vortexgpgpu/vortex.git
synced 2025-04-23 21:39:10 -04:00
moved apae sources into rtl/afu
This commit is contained in:
Blaise Tine
parent
d5fa82f5e4
commit
14baec86d5
18 changed files with 35 additions and 1710 deletions
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@ -93,7 +93,8 @@ $(ASE_DIR):
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clean:
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rm -rf $(PROJECT) $(PROJECT_ASE) $(PROJECT_VLSIM) *.o .depend
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$(MAKE) -C vlsim clean
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$(MAKE) -C vlsim clean
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$(MAKE) -C ase clean
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ifneq ($(MAKECMDGOALS),clean)
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-include .depend
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@ -1,6 +1,6 @@
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ASE_BUILD_DIR=build_ase
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FPGA_BUILD_DIR=build_fpga
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RTL_DIR=../rtl
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all: ase-1c
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@ -11,15 +11,15 @@ gen_sources: sources.txt
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ase-1c: gen_sources setup-ase-1c
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make -C $(ASE_BUILD_DIR)_1c
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cp ../rtl/fp_cores/altera/*.hex $(ASE_BUILD_DIR)_1c/work
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cp $(RTL_DIR)/fp_cores/altera/*.hex $(ASE_BUILD_DIR)_1c/work
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ase-2c: gen_sources setup-ase-2c
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make -C $(ASE_BUILD_DIR)_2c
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cp ../rtl/fp_cores/altera/*.hex $(ASE_BUILD_DIR)_2c/work
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cp $(RTL_DIR)/fp_cores/altera/*.hex $(ASE_BUILD_DIR)_2c/work
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ase-4c: gen_sources setup-ase-4c
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make -C $(ASE_BUILD_DIR)_4c
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cp ../rtl/fp_cores/altera/*.hex $(ASE_BUILD_DIR)_4c/work
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cp $(RTL_DIR)/fp_cores/altera/*.hex $(ASE_BUILD_DIR)_4c/work
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setup-ase-1c: $(ASE_BUILD_DIR)_1c/Makefile
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@ -38,15 +38,15 @@ $(ASE_BUILD_DIR)_4c/Makefile: sources.txt
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fpga-1c: gen_sources setup-fpga-1c
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cd $(FPGA_BUILD_DIR)_1c && qsub-synth
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cp ../rtl/fp_cores/altera/*.hex $(FPGA_BUILD_DIR)_1c
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cp $(RTL_DIR)/fp_cores/altera/*.hex $(FPGA_BUILD_DIR)_1c
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fpga-2c: gen_sources setup-fpga-2c
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cd $(FPGA_BUILD_DIR)_2c && qsub-synth
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cp ../rtl/fp_cores/altera/*.hex $(FPGA_BUILD_DIR)_2c
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cp $(RTL_DIR)/fp_cores/altera/*.hex $(FPGA_BUILD_DIR)_2c
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fpga-4c: gen_sources setup-fpga-4c
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cd $(FPGA_BUILD_DIR)_4c && qsub-synth
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cp ../rtl/fp_cores/altera/*.hex $(FPGA_BUILD_DIR)_4c
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cp $(RTL_DIR)/fp_cores/altera/*.hex $(FPGA_BUILD_DIR)_4c
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setup-fpga-1c: $(FPGA_BUILD_DIR)_1c/build/dcp.qpf
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@ -90,3 +90,5 @@ clean-fpga-2c:
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clean-fpga-4c:
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rm -rf $(FPGA_BUILD_DIR)_4c sources.txt
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clean: clean-ase-1c clean-ase-2c clean-ase-4c clean-fpga-1c clean-fpga-2c clean-fpga-4c
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rm sources.txt
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@ -87,8 +87,8 @@ tar -cvjf trace.fst.tar.bz2 trace.fst run.log
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tar -cvjf trace.vcd.tar.bz2 trace.vcd run.log
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# decompress VCD trace
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tar -zxvf /mnt/c/Users/Blaise/Downloads/vortex.vcd.tar.gz
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tar -xvf /mnt/c/Users/Blaise/Downloads/vortex.vcd.tar.bz2
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tar -zxvf vortex.vcd.tar.gz
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tar -xvf vortex.vcd.tar.bz2
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# launch Gtkwave
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gtkwave ./build_ase_1c/work/vortex.vcd &
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@ -1,131 +0,0 @@
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`include "VX_define.vh"
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module VX_avs_wrapper #(
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parameter AVS_DATAW = 1,
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parameter AVS_ADDRW = 1,
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parameter AVS_BURSTW = 1,
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parameter AVS_BANKS = 1,
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parameter REQ_TAGW = 1,
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parameter RD_QUEUE_SIZE = 1,
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parameter AVS_BYTEENW = (AVS_DATAW / 8),
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parameter RD_QUEUE_ADDRW= $clog2(RD_QUEUE_SIZE+1),
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parameter AVS_BANKS_BITS= $clog2(AVS_BANKS)
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) (
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input wire clk,
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input wire reset,
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// AVS bus
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output wire [AVS_DATAW-1:0] avs_writedata,
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input wire [AVS_DATAW-1:0] avs_readdata,
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output wire [AVS_ADDRW-1:0] avs_address,
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input wire avs_waitrequest,
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output wire avs_write,
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output wire avs_read,
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output wire [AVS_BYTEENW-1:0] avs_byteenable,
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output wire [AVS_BURSTW-1:0] avs_burstcount,
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input avs_readdatavalid,
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output wire [AVS_BANKS_BITS-1:0] avs_bankselect,
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// DRAM request
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input wire dram_req_valid,
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input wire dram_req_rw,
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input wire [AVS_BYTEENW-1:0] dram_req_byteen,
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input wire [AVS_ADDRW-1:0] dram_req_addr,
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input wire [AVS_DATAW-1:0] dram_req_data,
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input wire [REQ_TAGW-1:0] dram_req_tag,
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output wire dram_req_ready,
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// DRAM response
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output wire dram_rsp_valid,
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output wire [AVS_DATAW-1:0] dram_rsp_data,
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output wire [REQ_TAGW-1:0] dram_rsp_tag,
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input wire dram_rsp_ready
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);
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reg [AVS_BANKS_BITS-1:0] avs_bankselect_r;
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reg [AVS_BURSTW-1:0] avs_burstcount_r;
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wire avs_reqq_push = dram_req_valid && dram_req_ready && !dram_req_rw;
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wire avs_reqq_pop = dram_rsp_valid && dram_rsp_ready;
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wire avs_rspq_push = avs_readdatavalid;
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wire avs_rspq_pop = avs_reqq_pop;
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wire avs_rspq_empty;
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reg [RD_QUEUE_ADDRW-1:0] avs_pending_reads;
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wire [RD_QUEUE_ADDRW-1:0] avs_pending_reads_n;
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assign avs_pending_reads_n = avs_pending_reads
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+ RD_QUEUE_ADDRW'((avs_reqq_push && !avs_rspq_pop) ? 1 :
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(avs_rspq_pop && !avs_reqq_push) ? -1 : 0);
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always @(posedge clk) begin
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if (reset) begin
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avs_burstcount_r <= 1;
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avs_bankselect_r <= 0;
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avs_pending_reads <= 0;
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end else begin
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avs_pending_reads <= avs_pending_reads_n;
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end
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end
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VX_generic_queue #(
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.DATAW (REQ_TAGW),
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.SIZE (RD_QUEUE_SIZE),
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.BUFFERED (1)
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) rd_req_queue (
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.clk (clk),
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.reset (reset),
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.push (avs_reqq_push),
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.pop (avs_reqq_pop),
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.data_in (dram_req_tag),
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.data_out (dram_rsp_tag),
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`UNUSED_PIN (empty),
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`UNUSED_PIN (full),
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`UNUSED_PIN (size)
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);
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VX_generic_queue #(
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.DATAW (AVS_DATAW),
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.SIZE (RD_QUEUE_SIZE),
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.BUFFERED (1)
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) rd_rsp_queue (
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.clk (clk),
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.reset (reset),
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.push (avs_rspq_push),
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.pop (avs_rspq_pop),
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.data_in (avs_readdata),
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.data_out (dram_rsp_data),
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.empty (avs_rspq_empty),
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`UNUSED_PIN (full),
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`UNUSED_PIN (size)
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);
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wire rsp_queue_ready = (avs_pending_reads != RD_QUEUE_SIZE);
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assign avs_read = dram_req_valid && !dram_req_rw && rsp_queue_ready;
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assign avs_write = dram_req_valid && dram_req_rw && rsp_queue_ready;
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assign avs_address = dram_req_addr;
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assign avs_byteenable = dram_req_byteen;
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assign avs_writedata = dram_req_data;
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assign dram_req_ready = !avs_waitrequest && rsp_queue_ready;
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assign avs_burstcount = avs_burstcount_r;
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assign avs_bankselect = avs_bankselect_r;
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assign dram_rsp_valid = !avs_rspq_empty;
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`ifdef DBG_PRINT_AVS
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always @(posedge clk) begin
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if (dram_req_valid && dram_req_ready) begin
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if (dram_req_rw)
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$display("%t: AVS Wr Req: addr=%0h, byteen=%0h, tag=%0h, data=%0h", $time, `TO_FULL_ADDR(dram_req_addr), dram_req_byteen, dram_req_tag, dram_req_data);
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else
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$display("%t: AVS Rd Req: addr=%0h, byteen=%0h, tag=%0h, pending=%0d", $time, `TO_FULL_ADDR(dram_req_addr), dram_req_byteen, dram_req_tag, avs_pending_reads_n);
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end
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if (dram_rsp_valid && dram_rsp_ready) begin
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$display("%t: AVS Rd Rsp: tag=%0h, data=%0h, pending=%0d", $time, dram_rsp_tag, dram_rsp_data, avs_pending_reads_n);
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end
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end
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`endif
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endmodule
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@ -1,244 +0,0 @@
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// Date: 02/2/2016
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// Compliant with CCI-P spec v0.71
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package ccip_if_pkg;
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//=====================================================================
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// CCI-P interface defines
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//=====================================================================
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parameter CCIP_VERSION_NUMBER = 12'h071;
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parameter CCIP_CLADDR_WIDTH = 42;
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parameter CCIP_CLDATA_WIDTH = 512;
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parameter CCIP_MMIOADDR_WIDTH = 16;
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parameter CCIP_MMIODATA_WIDTH = 64;
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parameter CCIP_TID_WIDTH = 9;
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parameter CCIP_MDATA_WIDTH = 16;
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// Number of requests that can be accepted after almost full is asserted.
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parameter CCIP_TX_ALMOST_FULL_THRESHOLD = 8;
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parameter CCIP_MMIO_RD_TIMEOUT = 512;
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parameter CCIP_SYNC_RESET_POLARITY=1; // Active High Reset
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// Base types
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//----------------------------------------------------------------------
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typedef logic [CCIP_CLADDR_WIDTH-1:0] t_ccip_clAddr;
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typedef logic [CCIP_CLDATA_WIDTH-1:0] t_ccip_clData;
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typedef logic [CCIP_MMIOADDR_WIDTH-1:0] t_ccip_mmioAddr;
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typedef logic [CCIP_MMIODATA_WIDTH-1:0] t_ccip_mmioData;
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typedef logic [CCIP_TID_WIDTH-1:0] t_ccip_tid;
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typedef logic [CCIP_MDATA_WIDTH-1:0] t_ccip_mdata;
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typedef logic [1:0] t_ccip_clNum;
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typedef logic [2:0] t_ccip_qwIdx;
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// Request Type Encodings
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//----------------------------------------------------------------------
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// Channel 0
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typedef enum logic [3:0] {
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eREQ_RDLINE_I = 4'h0, // Memory Read with FPGA Cache Hint=Invalid
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eREQ_RDLINE_S = 4'h1 // Memory Read with FPGA Cache Hint=Shared
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} t_ccip_c0_req;
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// Channel 1
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typedef enum logic [3:0] {
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eREQ_WRLINE_I = 4'h0, // Memory Write with FPGA Cache Hint=Invalid
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eREQ_WRLINE_M = 4'h1, // Memory Write with FPGA Cache Hint=Modified
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eREQ_WRPUSH_I = 4'h2, // Memory Write with DDIO Hint ** NOT SUPPORTED CURRENTLY **
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eREQ_WRFENCE = 4'h4, // Memory Write Fence
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// eREQ_ATOMIC = 4'h5, // Atomic operation: Compare-Exchange for Memory Addr ** NOT SUPPORTED CURRENTELY **
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eREQ_INTR = 4'h6 // Interrupt the CPU ** NOT SUPPORTED CURRENTLY **
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} t_ccip_c1_req;
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// Response Type Encodings
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//----------------------------------------------------------------------
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// Channel 0
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typedef enum logic [3:0] {
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eRSP_RDLINE = 4'h0, // Memory Read
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eRSP_UMSG = 4'h4 // UMsg received
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// eRSP_ATOMIC = 4'h5 // Atomic Operation: Compare-Exchange for Memory Addr
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} t_ccip_c0_rsp;
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// Channel 1
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typedef enum logic [3:0] {
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eRSP_WRLINE = 4'h0, // Memory Write
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eRSP_WRFENCE = 4'h4, // Memory Write Fence
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eRSP_INTR = 4'h6 // Interrupt delivered to the CPU ** NOT SUPPORTED CURRENTLY **
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} t_ccip_c1_rsp;
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//
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// Virtual Channel Select
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//----------------------------------------------------------------------
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typedef enum logic [1:0] {
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eVC_VA = 2'b00,
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eVC_VL0 = 2'b01,
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eVC_VH0 = 2'b10,
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eVC_VH1 = 2'b11
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} t_ccip_vc;
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// Multi-CL Memory Request
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//----------------------------------------------------------------------
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typedef enum logic [1:0] {
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eCL_LEN_1 = 2'b00,
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eCL_LEN_2 = 2'b01,
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eCL_LEN_4 = 2'b11
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} t_ccip_clLen;
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//
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// Structures for Request and Response headers
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//----------------------------------------------------------------------
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typedef struct packed {
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t_ccip_vc vc_sel;
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logic [1:0] rsvd1; // reserved, drive 0
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t_ccip_clLen cl_len;
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t_ccip_c0_req req_type;
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logic [5:0] rsvd0; // reserved, drive 0
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t_ccip_clAddr address;
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t_ccip_mdata mdata;
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} t_ccip_c0_ReqMemHdr;
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parameter CCIP_C0TX_HDR_WIDTH = $bits(t_ccip_c0_ReqMemHdr);
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typedef struct packed {
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logic [5:0] rsvd2;
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t_ccip_vc vc_sel;
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logic sop;
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logic rsvd1; // reserved, drive 0
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t_ccip_clLen cl_len;
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t_ccip_c1_req req_type;
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logic [5:0] rsvd0; // reserved, drive 0
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t_ccip_clAddr address;
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t_ccip_mdata mdata;
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} t_ccip_c1_ReqMemHdr;
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parameter CCIP_C1TX_HDR_WIDTH = $bits(t_ccip_c1_ReqMemHdr);
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typedef struct packed {
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logic [5:0] rsvd2; // reserved, drive 0
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t_ccip_vc vc_sel;
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logic [3:0] rsvd1; // reserved, drive 0
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t_ccip_c1_req req_type;
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logic [47:0] rsvd0; // reserved, drive 0
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t_ccip_mdata mdata;
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}t_ccip_c1_ReqFenceHdr;
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typedef struct packed {
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t_ccip_vc vc_used;
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logic rsvd1; // reserved, don't care
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logic hit_miss;
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logic [1:0] rsvd0; // reserved, don't care
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t_ccip_clNum cl_num;
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t_ccip_c0_rsp resp_type;
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t_ccip_mdata mdata;
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} t_ccip_c0_RspMemHdr;
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parameter CCIP_C0RX_HDR_WIDTH = $bits(t_ccip_c0_RspMemHdr);
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typedef struct packed {
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t_ccip_vc vc_used;
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logic rsvd1; // reserved, don't care
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logic hit_miss;
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logic format;
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logic rsvd0; // reserved, don't care
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t_ccip_clNum cl_num;
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t_ccip_c1_rsp resp_type;
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t_ccip_mdata mdata;
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} t_ccip_c1_RspMemHdr;
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parameter CCIP_C1RX_HDR_WIDTH = $bits(t_ccip_c1_RspMemHdr);
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typedef struct packed {
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logic [7:0] rsvd0; // reserved, don't care
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t_ccip_c1_rsp resp_type;
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t_ccip_mdata mdata;
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} t_ccip_c1_RspFenceHdr;
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// Alternate Channel 0 MMIO request from host :
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// MMIO requests arrive on the same channel as read responses, sharing
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// t_if_ccip_c0_Rx below. When either mmioRdValid or mmioWrValid is set
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// the message is an MMIO request and should be processed by casting
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// t_if_ccip_c0_Rx.hdr to t_ccip_c0_ReqMmioHdr.
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typedef struct packed {
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t_ccip_mmioAddr address; // 4B aligned Mmio address
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logic [1:0] length; // 2'b00- 4B, 2'b01- 8B, 2'b10- 64B
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logic rsvd; // reserved, don't care
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t_ccip_tid tid;
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} t_ccip_c0_ReqMmioHdr;
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typedef struct packed {
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t_ccip_tid tid; // Returned back from ReqMmioHdr
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} t_ccip_c2_RspMmioHdr;
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parameter CCIP_C2TX_HDR_WIDTH = $bits(t_ccip_c2_RspMmioHdr);
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//------------------------------------------------------------------------
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// CCI-P Input & Output bus structures
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//
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// Users are encouraged to use these for AFU development
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//------------------------------------------------------------------------
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// Channel 0 : Memory Reads
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typedef struct packed {
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t_ccip_c0_ReqMemHdr hdr; // Request Header
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logic valid; // Request Valid
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} t_if_ccip_c0_Tx;
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// Channel 1 : Memory Writes, Interrupts, CmpXchg
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typedef struct packed {
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t_ccip_c1_ReqMemHdr hdr; // Request Header
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t_ccip_clData data; // Request Data
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logic valid; // Request Wr Valid
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} t_if_ccip_c1_Tx;
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// Channel 2 : MMIO Read response
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typedef struct packed {
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t_ccip_c2_RspMmioHdr hdr; // Response Header
|
||||
logic mmioRdValid; // Response Read Valid
|
||||
t_ccip_mmioData data; // Response Data
|
||||
} t_if_ccip_c2_Tx;
|
||||
|
||||
// Wrap all Tx channels
|
||||
typedef struct packed {
|
||||
t_if_ccip_c0_Tx c0;
|
||||
t_if_ccip_c1_Tx c1;
|
||||
t_if_ccip_c2_Tx c2;
|
||||
} t_if_ccip_Tx;
|
||||
|
||||
// Channel 0: Memory Read response, MMIO Request
|
||||
typedef struct packed {
|
||||
t_ccip_c0_RspMemHdr hdr; // Rd Response/ MMIO req Header
|
||||
t_ccip_clData data; // Rd Data / MMIO req Data
|
||||
// Only one of valid, mmioRdValid and mmioWrValid may be set
|
||||
// in a cycle. When either mmioRdValid or mmioWrValid are true
|
||||
// the hdr must be processed specially. See t_ccip_c0_ReqMmioHdr
|
||||
// above.
|
||||
logic rspValid; // Rd Response Valid
|
||||
logic mmioRdValid; // MMIO Read Valid
|
||||
logic mmioWrValid; // MMIO Write Valid
|
||||
} t_if_ccip_c0_Rx;
|
||||
|
||||
// Channel 1: Memory Writes
|
||||
typedef struct packed {
|
||||
t_ccip_c1_RspMemHdr hdr; // Response Header
|
||||
logic rspValid; // Response Valid
|
||||
} t_if_ccip_c1_Rx;
|
||||
|
||||
// Wrap all channels
|
||||
typedef struct packed {
|
||||
logic c0TxAlmFull; // C0 Request Channel Almost Full
|
||||
logic c1TxAlmFull; // C1 Request Channel Almost Full
|
||||
|
||||
t_if_ccip_c0_Rx c0;
|
||||
t_if_ccip_c1_Rx c1;
|
||||
} t_if_ccip_Rx;
|
||||
|
||||
|
||||
typedef union packed {
|
||||
t_ccip_c0_RspMemHdr rspMemHdr;
|
||||
t_ccip_c0_ReqMmioHdr reqMmioHdr;
|
||||
} t_if_ccip_c0_RxHdr;
|
||||
|
||||
endpackage
|
||||
|
|
@ -1,61 +0,0 @@
|
|||
//
|
||||
// Copyright (c) 2017, Intel Corporation
|
||||
// All rights reserved.
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright notice, this
|
||||
// list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright notice,
|
||||
// this list of conditions and the following disclaimer in the documentation
|
||||
// and/or other materials provided with the distribution.
|
||||
//
|
||||
// Neither the name of the Intel Corporation nor the names of its contributors
|
||||
// may be used to endorse or promote products derived from this software
|
||||
// without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
// POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
//`include "platform_afu_top_config.vh"
|
||||
|
||||
`ifdef PLATFORM_PROVIDES_LOCAL_MEMORY
|
||||
|
||||
package local_mem_cfg_pkg;
|
||||
|
||||
parameter LOCAL_MEM_VERSION_NUMBER = 1;
|
||||
|
||||
parameter LOCAL_MEM_ADDR_WIDTH = `PLATFORM_PARAM_LOCAL_MEMORY_ADDR_WIDTH;
|
||||
parameter LOCAL_MEM_DATA_WIDTH = `PLATFORM_PARAM_LOCAL_MEMORY_DATA_WIDTH;
|
||||
|
||||
parameter LOCAL_MEM_BURST_CNT_WIDTH = `PLATFORM_PARAM_LOCAL_MEMORY_BURST_CNT_WIDTH;
|
||||
|
||||
// Number of bytes in a data line
|
||||
parameter LOCAL_MEM_DATA_N_BYTES = LOCAL_MEM_DATA_WIDTH / 8;
|
||||
|
||||
|
||||
// Base types
|
||||
// --------------------------------------------------------------------
|
||||
|
||||
typedef logic [LOCAL_MEM_ADDR_WIDTH-1:0] t_local_mem_addr;
|
||||
typedef logic [LOCAL_MEM_DATA_WIDTH-1:0] t_local_mem_data;
|
||||
|
||||
typedef logic [LOCAL_MEM_BURST_CNT_WIDTH-1:0] t_local_mem_burst_cnt;
|
||||
|
||||
// Byte-level mask of a data line
|
||||
typedef logic [LOCAL_MEM_DATA_N_BYTES-1:0] t_local_mem_byte_mask;
|
||||
|
||||
endpackage // local_mem_cfg_pkg
|
||||
|
||||
`endif // PLATFORM_PROVIDES_LOCAL_MEMORY
|
||||
|
|
@ -1,7 +1,10 @@
|
|||
#!/bin/bash
|
||||
|
||||
dir_list='../rtl/libs ../rtl/cache ../rtl/interfaces ../rtl ../rtl/fp_cores/fpnew/src/common_cells/include ../rtl/fp_cores ../rtl/fp_cores/altera'
|
||||
exclude_list='VX_fpnew.v'
|
||||
rtl_dir="../rtl"
|
||||
|
||||
dir_list="$rtl_dir/libs $rtl_dir/cache $rtl_dir/interfaces $rtl_dir $rtl_dir/fp_cores/fpnew/src/common_cells/include $rtl_dir/fp_cores $rtl_dir/fp_cores/altera $rtl_dir/afu"
|
||||
|
||||
exclude_list="VX_fpnew.v"
|
||||
|
||||
# read design sources
|
||||
for dir in $dir_list; do
|
||||
|
|
|
|||
|
|
@ -1,97 +0,0 @@
|
|||
|
||||
|
||||
## Required tools
|
||||
# gcc (>4.9)
|
||||
# libjson
|
||||
# python
|
||||
# Quartus
|
||||
# RTL Simulator (VCS or ModelSim or QuestaSim)
|
||||
|
||||
|
||||
|
||||
## Download OPAE SDK from https://github.com/OPAE/opae-sdk/archive/1.4.0-1.tar.gz
|
||||
cd /nethome/achawda6/specialProblem/opae-sdk-1.4.0-1/
|
||||
|
||||
## Update the following file based on /nethome/achawda6/specialProblem/opae-sdk-1.4.0-1/libopae/plugins/ase/scripts/ase_setup_template.sh
|
||||
# ./opae-sdk-1.4.0-1/libopae/plugins/ase/scripts/ase_setup_template.sh
|
||||
|
||||
|
||||
|
||||
###################################################################################################
|
||||
################################### TO BE DONE EVERY TIME #########################################
|
||||
###################################################################################################
|
||||
## Change the shell to bash before running
|
||||
bash
|
||||
|
||||
## Setup Environment
|
||||
## Running the default script results in multiple versions of libcurl during cmake.
|
||||
#source /nethome/achawda6/specialProblem/rg_intel_fpga_end_19.3.sh
|
||||
source /tools/reconfig/intel/19.3/rg_intel_fpga_end_19.3.sh
|
||||
|
||||
## Setup the variables for using the Quartus modelsim
|
||||
source /nethome/achawda6/specialProblem/modelsim_env.sh
|
||||
|
||||
## Run this to setup the environment variables
|
||||
source /nethome/achawda6/specialProblem/opae-sdk-1.4.0-1/libopae/plugins/ase/scripts/ase_setup_template.sh
|
||||
|
||||
## gcc version should be greater than 4.9 to support c++14
|
||||
source /nethome/achawda6/specialProblem/opae-sdk-1.4.0-1/libopae/plugins/ase/scripts/env_check.sh
|
||||
|
||||
export PATH=/nethome/achawda6/specialProblem/opae-sdk-1.4.0-1/mybuild/opaeInstall/bin:${PATH}
|
||||
export FPGA_BBB_CCI_SRC=/nethome/achawda6/specialProblem/opae-sdk-1.4.0-1/intel-fpga-bbb
|
||||
####################################################################################################
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
## Setup OPAE
|
||||
mkdir mybuild
|
||||
cd mybuild
|
||||
|
||||
## Update the directory path where you want to install OPAE
|
||||
cmake .. -DBUILD_ASE=1 -DCMAKE_INSTALL_PREFIX=/nethome/achawda6/specialProblem/opae-sdk-1.4.0-1/mybuild/opaeInstall
|
||||
make
|
||||
make install
|
||||
|
||||
|
||||
|
||||
|
||||
## Setup ASE
|
||||
## Add the installed OPAE path in PATH
|
||||
export PATH=/nethome/achawda6/specialProblem/opae-sdk-1.4.0-1/mybuild/opaeInstall/bin:${PATH}
|
||||
|
||||
## Use this version of HDL files
|
||||
/nethome/achawda6/specialProblem/opae-sdk-1.4.0-1/libopae/plugins/ase/scripts/afu_sim_setup --sources=/nethome/achawda6/specialProblem/opae-sdk-1.4.0-1/libopae/plugins/ase/rtl/sources_ase_server.txt run1Build
|
||||
cd run1Build/
|
||||
python scripts/ipc_clean.py
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
## Running Sample
|
||||
## Download opae-bbb from https://github.com/OPAE/intel-fpga-bbb
|
||||
cd /nethome/achawda6/specialProblem/opae-sdk-1.4.0-1
|
||||
git clone https://github.com/OPAE/intel-fpga-bbb
|
||||
cd /nethome/achawda6/specialProblem/opae-sdk-1.4.0-1/intel-fpga-bbb
|
||||
mkdir mybuild
|
||||
cd mybuild
|
||||
cmake .. -DCMAKE_INSTALL_PREFIX=/nethome/achawda6/specialProblem/opae-sdk-1.4.0-1/mybuild/opaeInstall
|
||||
make
|
||||
make install
|
||||
|
||||
export FPGA_BBB_CCI_SRC=/nethome/achawda6/specialProblem/opae-sdk-1.4.0-1/intel-fpga-bbb
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
## Running hello world
|
||||
cd /nethome/achawda6/specialProblem/opae-sdk-1.4.0-1/intel-fpga-bbb/samples/tutorial/01_hello_world
|
||||
afu_sim_setup --source hw/rtl/sources.txt build_sim
|
||||
cd build_sim
|
||||
## Update libstdc++6 if it errors out
|
||||
make
|
||||
make sim
|
||||
|
|
@ -1,8 +0,0 @@
|
|||
#!/bin/bash
|
||||
|
||||
source /tools/reconfig/intel/19.3/rg_intel_fpga_end_19.3.sh
|
||||
export PATH=/tools/opae/1.4.0/bin:/tools/reconfig/intel/19.3/modelsim_ase/bin:$PATH
|
||||
export LD_LIBRARY_PATH=/tools/opae/1.4.0/lib:$PATH
|
||||
export QUARTUS_HOME=$QUARTUS_ROOTDIR
|
||||
export MTI_HOME=/tools/reconfig/intel/19.3/modelsim_ase
|
||||
export FPGA_FAMILY=arria10
|
||||
|
|
@ -21,9 +21,5 @@
|
|||
|
||||
vortex_afu.json
|
||||
QI:vortex_afu.qsf
|
||||
ccip_interface_reg.sv
|
||||
ccip_std_afu.sv
|
||||
VX_avs_wrapper.v
|
||||
vortex_afu.sv
|
||||
|
||||
C:sources.txt
|
||||
|
|
@ -6,9 +6,5 @@
|
|||
|
||||
vortex_afu.json
|
||||
QI:vortex_afu.qsf
|
||||
ccip_interface_reg.sv
|
||||
ccip_std_afu.sv
|
||||
VX_avs_wrapper.v
|
||||
vortex_afu.sv
|
||||
|
||||
C:sources.txt
|
||||
|
|
@ -6,9 +6,5 @@
|
|||
|
||||
vortex_afu.json
|
||||
QI:vortex_afu.qsf
|
||||
ccip_interface_reg.sv
|
||||
ccip_std_afu.sv
|
||||
VX_avs_wrapper.v
|
||||
vortex_afu.sv
|
||||
|
||||
C:sources.txt
|
||||
File diff suppressed because it is too large
Load diff
|
|
@ -1,37 +0,0 @@
|
|||
`ifndef __VORTEX_AFU__
|
||||
`define __VORTEX_AFU__
|
||||
|
||||
`include "ccip_if_pkg.sv"
|
||||
|
||||
`define PLATFORM_PROVIDES_LOCAL_MEMORY
|
||||
`define PLATFORM_PARAM_LOCAL_MEMORY_ADDR_WIDTH 26
|
||||
`define PLATFORM_PARAM_LOCAL_MEMORY_DATA_WIDTH 512
|
||||
`define PLATFORM_PARAM_LOCAL_MEMORY_BURST_CNT_WIDTH 4
|
||||
|
||||
`include "local_mem_cfg_pkg.sv"
|
||||
|
||||
`define AFU_ACCEL_NAME "vortex_afu"
|
||||
`define AFU_ACCEL_UUID 128'h35f9452b_25c2_434c_93d5_6f8c60db361c
|
||||
|
||||
`define AFU_IMAGE_CMD_CLFLUSH 4
|
||||
`define AFU_IMAGE_CMD_CSR_READ 5
|
||||
`define AFU_IMAGE_CMD_CSR_WRITE 6
|
||||
`define AFU_IMAGE_CMD_MEM_READ 1
|
||||
`define AFU_IMAGE_CMD_MEM_WRITE 2
|
||||
`define AFU_IMAGE_CMD_RUN 3
|
||||
`define AFU_IMAGE_MMIO_CMD_TYPE 10
|
||||
`define AFU_IMAGE_MMIO_CSR_CORE 24
|
||||
`define AFU_IMAGE_MMIO_CSR_ADDR 26
|
||||
`define AFU_IMAGE_MMIO_CSR_DATA 28
|
||||
`define AFU_IMAGE_MMIO_CSR_READ 30
|
||||
`define AFU_IMAGE_MMIO_DATA_SIZE 16
|
||||
`define AFU_IMAGE_MMIO_IO_ADDR 12
|
||||
`define AFU_IMAGE_MMIO_MEM_ADDR 14
|
||||
`define AFU_IMAGE_MMIO_SCOPE_READ 20
|
||||
`define AFU_IMAGE_MMIO_SCOPE_WRITE 22
|
||||
`define AFU_IMAGE_MMIO_STATUS 18
|
||||
|
||||
`define AFU_IMAGE_POWER 0
|
||||
`define AFU_TOP_IFC "ccip_std_afu_avalon_mm"
|
||||
|
||||
`endif
|
||||
|
|
@ -40,22 +40,22 @@ set_global_assignment -name VERILOG_MACRO NDEBUG
|
|||
set_global_assignment -name MESSAGE_DISABLE 16818
|
||||
set_global_assignment -name VERILOG_MACRO FPU_FAST
|
||||
|
||||
#set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
|
||||
#set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
|
||||
#set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
|
||||
#set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS ON
|
||||
#set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION ON
|
||||
#set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON
|
||||
#set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
|
||||
#set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
|
||||
#set_global_assignment -name POWER_USE_TA_VALUE 65
|
||||
#set_global_assignment -name SEED 1
|
||||
#set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
|
||||
#set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
|
||||
#set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
|
||||
#set_global_assignment -name OPTIMIZATION_TECHNIQUE SPEED
|
||||
#set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM
|
||||
#set_global_assignment -name OPTIMIZATION_MODE "AGGRESSIVE PERFORMANCE"
|
||||
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
|
||||
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
|
||||
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
|
||||
set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS ON
|
||||
set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION ON
|
||||
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON
|
||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
|
||||
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
|
||||
set_global_assignment -name POWER_USE_TA_VALUE 65
|
||||
set_global_assignment -name SEED 1
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
|
||||
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
|
||||
set_global_assignment -name OPTIMIZATION_TECHNIQUE SPEED
|
||||
set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM
|
||||
set_global_assignment -name OPTIMIZATION_MODE "AGGRESSIVE PERFORMANCE"
|
||||
|
||||
set idx 0
|
||||
foreach arg $q_args_orig {
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@ PROJECT = vortex_afu
|
|||
TOP_LEVEL_ENTITY = vortex_afu
|
||||
SRC_FILE = vortex_afu.sv
|
||||
FPU_INCLUDE = ../../../rtl/fp_cores;../../../rtl/fp_cores/altera;../../../rtl/fp_cores/fpnew/src;../../../rtl/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl;../../../rtl/fp_cores/fpnew/src/common_cells/include;../../../rtl/fp_cores/fpnew/src/common_cells/src
|
||||
RTL_INCLUDE = $(FPU_INCLUDE);../../../rtl;../../../rtl/libs;../../../rtl/interfaces;../../../rtl/cache;../../../opae;../../../opae/ccip
|
||||
RTL_INCLUDE = $(FPU_INCLUDE);../../../rtl;../../../rtl/libs;../../../rtl/interfaces;../../../rtl/cache;../../../rtl/afu;../../../rtl/afu/ccip
|
||||
PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf
|
||||
|
||||
# Part, Family
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue