mirror of
https://github.com/vortexgpgpu/vortex.git
synced 2025-04-24 05:47:35 -04:00
minor update
This commit is contained in:
Blaise Tine
parent
b02fc14da6
commit
1512138a15
8 changed files with 45 additions and 132 deletions
9
.gitignore
vendored
9
.gitignore
vendored
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@ -1,9 +0,0 @@
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./rtl/obj_dir/
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./rtl/obj_dir/*.vcd
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./rtl/.*
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./rtl/modelsim/*.vcd
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*.vcd
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.*
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!.gitignore
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*.pyc
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__pycache__
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@ -2,7 +2,7 @@
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ASE_BUILD_DIR=build_ase
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FPGA_BUILD_DIR=build_fpga
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all: ase fpga fpga-1c
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all: ase ase-1c fpga fpga-1c
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ase: setup-ase
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make -C $(ASE_BUILD_DIR)
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@ -12,6 +12,14 @@ setup-ase: $(ASE_BUILD_DIR)/Makefile
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$(ASE_BUILD_DIR)/Makefile:
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afu_sim_setup -s sources.txt $(ASE_BUILD_DIR)
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ase-1c: setup-ase-1c
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make -C $(ASE_BUILD_DIR)_1c
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setup-ase-1c: $(ASE_BUILD_DIR)_1c/Makefile
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$(ASE_BUILD_DIR)_1c/Makefile:
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afu_sim_setup -s sources_1c.txt $(ASE_BUILD_DIR)_1c
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fpga: setup-fpga
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cd $(FPGA_BUILD_DIR) && qsub-synth
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@ -31,6 +39,9 @@ $(FPGA_BUILD_DIR)_1c/build/dcp.qpf:
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run-ase:
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cd $(ASE_BUILD_DIR) && make sim
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run-ase-1c:
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cd $(ASE_BUILD_DIR)_1c && make sim
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wave:
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vsim -view $(ASE_BUILD_DIR)/work/vsim.wlf -do wave.do
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@ -40,5 +51,11 @@ run-fpga:
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clean-ase:
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rm -rf $(ASE_BUILD_DIR)
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clean-ase-1c:
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rm -rf $(ASE_BUILD_DIR)_1c
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clean-fpga:
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rm -rf $(FPGA_BUILD_DIR)
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rm -rf $(FPGA_BUILD_DIR)
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clean-fpga-1c:
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rm -rf $(FPGA_BUILD_DIR)_1c
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@ -58,8 +58,8 @@ source /export/fpga/bin/setup-fpga-env fpga-pac-a10
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qsub-sim
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# tests
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./run_ase.sh ../../driver/tests/basic/basic
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./run_ase.sh ../../driver/tests/demo/demo
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./run_ase.sh build_ase ../../driver/tests/basic/basic
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./run_ase.sh build_ase ../../driver/tests/demo/demo
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# modify "vsim_run.tcl" to dump VCD trace
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vcd file vortex.vcd
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@ -1,22 +1,25 @@
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#!/bin/bash
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SCRIPT_DIR=$PWD
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PROGRAM=$(basename "$1")
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PROGRAM_DIR=`dirname $1`
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BUILD_DIR=$1
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PROGRAM=$(basename "$2")
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PROGRAM_DIR=`dirname $2`
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# Export ASE_WORKDIR variable
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export ASE_WORKDIR=$SCRIPT_DIR/build_ase/work
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export ASE_WORKDIR=$SCRIPT_DIR/$BUILD_DIR/work
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shift 1
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shift 2
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# cleanup incomplete runs
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rm -f $ASE_WORKDIR/.app_lock.pid
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rm -f $ASE_WORKDIR/.ase_ready.pid
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rm -f $SCRIPT_DIR/build_ase/nohup.out
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rm -f $SCRIPT_DIR/$BUILD_DIR/nohup.out
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# Start Simulator in background
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pushd $SCRIPT_DIR/build_ase
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echo " [DBG] starting ASE simnulator (stdout saved to '$SCRIPT_DIR/build_ase/nohup.out')"
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pushd $SCRIPT_DIR/$BUILD_DIR
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echo " [DBG] starting ASE simnulator (stdout saved to '$SCRIPT_DIR/$BUILD_DIR/nohup.out')"
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nohup make sim &
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popd
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@ -2,7 +2,21 @@ vortex_afu.json
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+define+GLOBAL_BLOCK_SIZE=64
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+define+DCACHE_SIZE=2048
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+define+ICACHE_SIZE=1024
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+define+SCACHE_SIZE=1024
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+define+NUM_CORES=2
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+define+NUM_WARPS=4
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+define+NUM_THREADS=4
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+define+DNUM_BANKS=4
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+define+INUM_BANKS=2
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+define+SNUM_BANKS=4
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+define+DDFPQ_SIZE=16
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+define+IDFPQ_SIZE=16
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+define+SDFPQ_SIZE=0
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#+define+DBG_PRINT_CORE_ICACHE
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#+define+DBG_PRINT_CORE_DCACHE
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@ -1,70 +0,0 @@
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PROJECT = VX_scheduler
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TOP_LEVEL_ENTITY = VX_scheduler
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SRC_FILE = VX_scheduler.v
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PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf
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# Part, Family
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FAMILY = "Arria 10"
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DEVICE = 10AX115N3F40E2SG
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# Executable Configuration
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SYN_ARGS = --parallel --read_settings_files=on
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FIT_ARGS = --part=$(DEVICE) --read_settings_files=on
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ASM_ARGS =
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STA_ARGS = --do_report_timing
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# Build targets
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all: $(PROJECT).sta.rpt
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syn: $(PROJECT).syn.rpt
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fit: $(PROJECT).fit.rpt
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asm: $(PROJECT).asm.rpt
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sta: $(PROJECT).sta.rpt
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smart: smart.log
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# Target implementations
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STAMP = echo done >
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$(PROJECT).syn.rpt: smart.log syn.chg $(SOURCE_FILES)
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quartus_syn $(PROJECT) $(SYN_ARGS)
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$(STAMP) fit.chg
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$(PROJECT).fit.rpt: smart.log fit.chg $(PROJECT).syn.rpt
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quartus_fit $(PROJECT) $(FIT_ARGS)
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$(STAMP) asm.chg
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$(STAMP) sta.chg
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$(PROJECT).asm.rpt: smart.log asm.chg $(PROJECT).fit.rpt
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quartus_asm $(PROJECT) $(ASM_ARGS)
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$(PROJECT).sta.rpt: smart.log sta.chg $(PROJECT).fit.rpt
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quartus_sta $(PROJECT) $(STA_ARGS)
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smart.log: $(PROJECT_FILES)
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quartus_sh --determine_smart_action $(PROJECT) > smart.log
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# Project initialization
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$(PROJECT_FILES):
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quartus_sh -t project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src $(SRC_FILE) -sdc project.sdc -inc "../../../rtl;../../../rtl/libs;../../../rtl/interfaces;../../../rtl/pipe_regs;../../../rtl/cache"
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syn.chg:
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$(STAMP) syn.chg
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fit.chg:
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$(STAMP) fit.chg
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sta.chg:
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$(STAMP) sta.chg
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asm.chg:
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$(STAMP) asm.chg
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program: $(PROJECT).sof
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quartus_pgm --no_banner --mode=jtag -o "$(PROJECT).sof"
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clean:
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rm -rf bin *.rpt *.chg *.qsf *.qpf *.qws smart.log *.htm *.eqn *.pin *.sof *.pof qdb incremental_db tmp-clearbox
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@ -1 +0,0 @@
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create_clock -name {clk} -period "250 MHz" -waveform { 0.0 1.0 } [get_ports {clk}]
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@ -1,41 +0,0 @@
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load_package flow
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package require cmdline
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set options { \
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{ "project.arg" "" "Project name" } \
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{ "family.arg" "" "Device family name" } \
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{ "device.arg" "" "Device name" } \
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{ "top.arg" "" "Top level module" } \
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{ "sdc.arg" "" "Timing Design Constraints file" } \
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{ "src.arg" "" "Verilog source file" } \
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{ "inc.arg" "." "Include path" } \
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}
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array set opts [::cmdline::getoptions quartus(args) $options]
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project_new $opts(project) -overwrite
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set_global_assignment -name FAMILY $opts(family)
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set_global_assignment -name DEVICE $opts(device)
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set_global_assignment -name TOP_LEVEL_ENTITY $opts(top)
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set_global_assignment -name VERILOG_FILE $opts(src)
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set_global_assignment -name SEARCH_PATH $opts(inc)
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set_global_assignment -name SDC_FILE $opts(sdc)
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set_global_assignment -name PROJECT_OUTPUT_DIRECTORY bin
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set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
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set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2009
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proc make_all_pins_virtual {} {
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execute_module -tool map
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set name_ids [get_names -filter * -node_type pin]
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foreach_in_collection name_id $name_ids {
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set pin_name [get_name_info -info full_path $name_id]
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post_message "Making VIRTUAL_PIN assignment to $pin_name"
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set_instance_assignment -to $pin_name -name VIRTUAL_PIN ON
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}
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export_assignments
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}
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make_all_pins_virtual
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project_close
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