mirror of
https://github.com/vortexgpgpu/vortex.git
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Fixed SM + added def SYN
This commit is contained in:
felsabbagh3
parent
3cb5820ecd
commit
1645a04b1d
13 changed files with 2388 additions and 2364 deletions
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:100950009387871B032784FD23A2E700B7670281E3
|
||||
:100960009387871B032744FD23A4E700B767028111
|
||||
:100970009387871B032704FD23A6E700EFF01F885A
|
||||
:100980002324A4FE032704FD832784FEB357F70224
|
||||
:100990002326F4FE032704FD832784FEB377F702A2
|
||||
:1009A000638807008327C4FE938717002326F4FE7D
|
||||
:1009B000B76702819387871B0327C4FE23A8E7003C
|
||||
:1009C000032704FD832784FE6362F702B767028171
|
||||
:1009D0009386871BB7170080138647A4832584FE60
|
||||
:1009E000032504FDEFF01FA96F000002B767028125
|
||||
:1009F0009386871BB7170080138647A4832504FDC1
|
||||
:100A0000032504FDEFF01FA7EFF0CFFE2322A4FE85
|
||||
:100A1000032704FD832744FE63F8E700032544FE13
|
||||
:100A2000EFF05FB46F00C000032504FDEFF09FB34B
|
||||
:100A3000130000008320C10203248102130101037B
|
||||
:100A400067800000130101FA232E1104232C810476
|
||||
:100A5000130401062326A4FA2324B4FAEFF09FBF5F
|
||||
:100A6000232CA4FC832784FD83A70700232AF4FCFE
|
||||
:100A7000832784FD83A747002328F4FC832784FD74
|
||||
:100A800083A787002326F4FC832784FD83A707011F
|
||||
:100A90002326F4FE0327C4FE8327C4FAB307F70214
|
||||
:100AA0002324F4FE8327C4FE639A070093071000F3
|
||||
:100AB0002326F4FE8327C4FA2324F4FE832784FD2F
|
||||
:100AC00083A7C7002324F4FC232204FE6F00800DBB
|
||||
:100AD000232004FE232E04FC6F008007032784FAE2
|
||||
:100AE000832784FCB307F7020327C4FDB307F7008D
|
||||
:100AF0002322F4FC032784FC8327C4FDB307F702F9
|
||||
:100B0000032784FEB307F7002320F4FC832744FC6B
|
||||
:100B100093972700032744FDB307F70003A70700B7
|
||||
:100B2000832704FC93972700832604FDB387F600F0
|
||||
:100B300083A70700B307F702032704FEB307F700F4
|
||||
:100B40002320F4FE8327C4FD93871700232EF4FC93
|
||||
:100B50000327C4FD832784FCE362F7F8032784FAA4
|
||||
:100B6000832784FC3307F702832784FEB307F7004B
|
||||
:100B7000232EF4FA8327C4FB939727000327C4FC92
|
||||
:100B8000B307F700032704FE23A0E700832784FEB2
|
||||
:100B9000938717002324F4FE832744FE93871700CE
|
||||
:100BA0002322F4FE832744FE0327C4FEE3E2E7F298
|
||||
:100BB000130000008320C1050324810513010106F1
|
||||
:100BC00067800000130101FC232E1102232C8102F7
|
||||
:100BD00013040104232EA4FC232CB4FC232AC4FCFC
|
||||
:100BE0002328D4FC2326E4FCB76702810327C4FD35
|
||||
:100BF00023A6E71CB76702819387C71C032784FDE0
|
||||
:100C000023A2E700B76702819387C71C032744FD2F
|
||||
:100C100023A4E700B76702819387C71C0327C4FC9E
|
||||
:100C200023A6E700B76702819387C71C032704FD4B
|
||||
:100C300023A8E700EFF08FDC2324A4FE0327C4FCE5
|
||||
:100C4000832784FEB357F7022326F4FE0327C4FC50
|
||||
:100C5000832784FEB377F702638807008327C4FEE7
|
||||
:100C6000938717002326F4FEB76702819387C71C7A
|
||||
:100C70000327C4FE23AAE7000327C4FC832784FEBE
|
||||
:100C80006362F702B76702819386C71CB7170080BB
|
||||
:100C90001386C7CF832584FE032504FDEFF08FFD67
|
||||
:100CA0006F000002B76702819386C71CB7170080E8
|
||||
:100CB0001386C7CF8325C4FC032504FDEFF08FFB0B
|
||||
:100CC000EFF04FD32322A4FE032704FD832744FE25
|
||||
:100CD00063F8E700032544FEEFF0DF886F00C000F3
|
||||
:100CE000032504FDEFF01F88130000008320C103DB
|
||||
:100CF000032481031301010467800000130101FB39
|
||||
:100D0000232611042324810413040105232EA4FAAD
|
||||
:100D1000232CB4FAEFF01F942320A4FE832704FEB3
|
||||
:100D200083A70700232EF4FC832704FE83A7470034
|
||||
:100D3000232CF4FC832704FE83A78700232AF4FCDA
|
||||
:100D4000832704FE83A747012326F4FE0327C4FE5E
|
||||
:100D50008327C4FBB307F7022324F4FE8327C4FED2
|
||||
:100D6000639A0700930710002326F4FE8327C4FB31
|
||||
:100D70002324F4FE832704FE83A7C7002328F4FC62
|
||||
:100D8000232204FE6F00000C032784FB832704FD4D
|
||||
:100D90003307F702832784FEB307F7002326F4FC0A
|
||||
:100DA000032784FE832704FDB337F70093F7F70F7B
|
||||
:100DB0002324F4FC832784FC93B71700A303F4FCDB
|
||||
:100DC000834774FC138F0700B7170080938F07E3E6
|
||||
:100DD0006B200F007B70FF018327C4FC93972700D3
|
||||
:100DE0000327C4FDB307F70083A607008327C4FCCD
|
||||
:100DF00093972700032784FDB307F70003A7070095
|
||||
:100E00008327C4FC93972700032644FDB307F6000D
|
||||
:100E10003387E60023A0E700832784FE938717002B
|
||||
:100E20002324F4FEB7170080138E47E367000E00FB
|
||||
:100E3000130000006B300000832744FE93871700E7
|
||||
:100E40002322F4FE832744FE0327C4FEE3EEE7F2E9
|
||||
:100E5000130000008320C104032481041301010551
|
||||
:100E600067800000130101FC232E1102232C810254
|
||||
:100E700013040104232EA4FC232CB4FC232AC4FC59
|
||||
:100E80002328D4FC2326E4FCB76702810327C4FD92
|
||||
:100E900023A6E71CB76702819387C71C032784FD3D
|
||||
:100EA00023A2E700B76702819387C71C032744FD8D
|
||||
:100EB00023A4E700B76702819387C71C0327C4FCFC
|
||||
:100EC00023A6E700B76702819387C71C032704FDA9
|
||||
:100ED00023A8E700EFF08FB22324A4FE0327C4FC6D
|
||||
:100EE000832784FEB357F7022326F4FE0327C4FCAE
|
||||
:100EF000832784FEB377F702638807008327C4FE45
|
||||
:100F0000938717002326F4FEB76702819387C71CD7
|
||||
:100F10000327C4FE23AAE7000327C4FC832784FE1B
|
||||
:100F20006362F702B76702819386C71CB717008018
|
||||
:100F30001386C7F9832584FE032504FDEFF08FD3C4
|
||||
:100F40006F000002B76702819386C71CB717008045
|
||||
:100F50001386C7F98325C4FC032504FDEFF08FD168
|
||||
:100F6000EFF04FA92322A4FE032704FD832744FEAC
|
||||
:100F700063F8E700032544FEEFF0CFDE6F00C0000A
|
||||
:100F8000032504FDEFF00FDE130000008320C103F2
|
||||
:100F9000032481031301010467800000130101FB96
|
||||
:100FA000232611042324810413040105232EA4FA0B
|
||||
:100FB000232CB4FAEFF00FEA2320A4FE832704FECB
|
||||
:100FC00083A70700232EF4FC832704FE83A7470092
|
||||
:100FD000232CF4FC832704FE83A78700232AF4FC38
|
||||
:100FE000832704FE83A747012326F4FE0327C4FEBC
|
||||
:100FF0008327C4FBB307F7022324F4FE8327C4FE30
|
||||
:10100000639A0700930710002326F4FE8327C4FB8E
|
||||
:101010002324F4FE832704FE83A7C7002328F4FCBF
|
||||
:10102000232204FE6F00000C032784FB832704FDAA
|
||||
:101030003307F702832784FEB307F7002326F4FC67
|
||||
:10104000032784FE832704FDB337F70093F7F70FD8
|
||||
:101050002324F4FC832784FC93B71700A303F4FC38
|
||||
:10106000834774FC138F0700B7170080938F070D19
|
||||
:101070006B200F007B70FF018327C4FC9397270030
|
||||
:101080000327C4FDB307F70083A607008327C4FC2A
|
||||
:1010900093972700032784FDB307F70003A70700F2
|
||||
:1010A0008327C4FC93972700032644FDB307F6006B
|
||||
:1010B0003387E64023A0E700832784FE9387170049
|
||||
:1010C0002324F4FEB7170080138E470D67000E002F
|
||||
:1010D000130000006B300000832744FE9387170045
|
||||
:1010E0002322F4FE832744FE0327C4FEE3EEE7F247
|
||||
:1010F000130000008320C1040324810413010105AF
|
||||
:1011000067800000130101FC232E1102232C8102B1
|
||||
:1011100013040104232EA4FC232CB4FC232AC4FCB6
|
||||
:101120002328D4FC2326E4FCB76702810327C4FDEF
|
||||
:1011300023A2E71EB76702819387471E032784FD1A
|
||||
:1011400023A2E700B76702819387471E032744FD68
|
||||
:1011500023A4E700B76702819387471E0327C4FCD7
|
||||
:1011600023A6E700B76702819387471E032704FD84
|
||||
:1011700023A8E700EFF08F882324A4FE0327C4FCF4
|
||||
:10118000832784FEB357F7022326F4FE0327C4FC0B
|
||||
:10119000832784FEB377F702638807008327C4FEA2
|
||||
:1011A000938717002326F4FEB76702819387471EB3
|
||||
:1011B0000327C4FE23AAE7000327C4FC832784FE79
|
||||
:1011C0006362F702B76702819386471EB7170080F4
|
||||
:1011D0001386C723832584FE032504FDEFF08FA922
|
||||
:1011E0006F000002B76702819386471EB717008021
|
||||
:1011F0001386C7238325C4FC032504FDEFF08FA7C6
|
||||
:10120000EFE05FFF2322A4FE032704FD832744FEB3
|
||||
:1012100063F8E700032544FEEFF0CFB46F00C00091
|
||||
:10122000032504FDEFF00FB4130000008320C10379
|
||||
:10123000032481031301010467800000130101FBF3
|
||||
:10124000232611042324810413040105232EA4FA68
|
||||
:10125000232CB4FAEFF00FC02320A4FE832704FE52
|
||||
:1012600083A70700232EF4FC832704FE83A74700EF
|
||||
:1012700083A70700232CF4FC832704FE83A78700A1
|
||||
:10128000232AF4FC832704FE83A747012326F4FEC8
|
||||
:101290000327C4FE8327C4FBB307F7022324F4FE0D
|
||||
:1012A0008327C4FE639A0700930710002326F4FEE9
|
||||
:1012B0008327C4FB2324F4FE832704FE83A7C700EF
|
||||
:1012C0002328F4FC232204FE6F00000B032784FB79
|
||||
:1012D000832704FD3307F702832784FEB307F70053
|
||||
:1012E0002326F4FC032784FE832704FDB337F7008D
|
||||
:1012F00093F7F70F2324F4FC832784FC93B717009C
|
||||
:10130000A303F4FC834774FC138F0700B717008016
|
||||
:10131000938F47366B200F007B70FF018327C4FC3F
|
||||
:10132000939727000327C4FDB307F70083A60700A0
|
||||
:101330008327C4FC93972700032744FDB307F700D6
|
||||
:10134000032784FD3387E60023A0E700832784FE7C
|
||||
:10135000938717002324F4FEB7170080138E873677
|
||||
:1013600067000E00130000006B300000832744FE6E
|
||||
:10137000938717002322F4FE832744FE0327C4FE2D
|
||||
:10138000E3E6E7F4130000008320C1040324810492
|
||||
:101390001301010567800000130101FC232E1102D7
|
||||
:1013A000232C810213040104232EA4FC232CB4FC5F
|
||||
:1013B000232AC4FC2328D4FC2326E4FCB76702813B
|
||||
:1013C0000327C4FD23A2E71EB76702819387471E48
|
||||
:1013D000032784FD23A2E700B76702819387471E96
|
||||
:1013E000032744FD23A4E700B76702819387471EC4
|
||||
:1013F0000327C4FC23A6E700B76702819387471E33
|
||||
:10140000032704FD23A8E700EFE05FDF2324A4FE09
|
||||
:101410000327C4FC832784FEB357F7022326F4FE78
|
||||
:101420000327C4FC832784FEB377F7026388070091
|
||||
:101430008327C4FE938717002326F4FEB767028133
|
||||
:101440009387471E0327C4FE23AAE7000327C4FC93
|
||||
:10145000832784FE6362F702B76702819386471E83
|
||||
:10146000B71700801386074D832584FE032504FDEE
|
||||
:10147000EFF04F806F000002B76702819386471E2E
|
||||
:10148000B71700801386074D8325C4FC032504FD90
|
||||
:10149000EFE05FFEEFE01FD62322A4FE032704FD4A
|
||||
:1014A000832744FE63F8E700032544FEEFF08F8BAB
|
||||
:1014B0006F00C000032504FDEFF0CF8A1300000089
|
||||
:1014C0008320C1030324810313010104678000000A
|
||||
:1014D000130101FB232611042324810413040105B5
|
||||
:1014E000232EA4FA232CB4FAEFF0CF962320A4FEE7
|
||||
:1014F000832704FE83A70700232EF4FC832704FE22
|
||||
:1015000083A7470083A70700232CF4FC832704FE4E
|
||||
:1015100083A78700232AF4FC832704FE83A74701BF
|
||||
:101520002326F4FE0327C4FE8327C4FBB307F70278
|
||||
:101530002324F4FE8327C4FE639A07009307100058
|
||||
:101540002326F4FE8327C4FB2324F4FE832704FE12
|
||||
:1015500083A7C7002328F4FC232204FE6F00000B9E
|
||||
:10156000032784FB832704FD3307F702832784FEC8
|
||||
:10157000B307F7002326F4FC032784FE832704FD2A
|
||||
:10158000B337F70093F7F70F2324F4FC832784FC89
|
||||
:1015900093B71700A303F4FC834774FC138F070071
|
||||
:1015A000B7170080938F875F6B200F007B70FF0160
|
||||
:1015B0008327C4FC939727000327C4FDB307F700D4
|
||||
:1015C00083A607008327C4FC93972700032744FDC5
|
||||
:1015D000B307F700032784FD3387E60223A0E70063
|
||||
:1015E000832784FE938717002324F4FEB717008017
|
||||
:1015F000138EC75F67000E00130000006B30000001
|
||||
:10160000832744FE938717002322F4FE832744FE9A
|
||||
:101610000327C4FEE3E6E7F4130000008320C104BF
|
||||
:10162000032481041301010567800000130101FDFB
|
||||
:101630002326810213040103232EA4FC232604FE87
|
||||
:101640006F0000018327C4FE938717002326F4FE52
|
||||
:101650000327C4FE8327C4FDE346F7FE1300000002
|
||||
:101660000324C1021301010367800000130101FD7F
|
||||
:10167000232611022324810213040103232EA4FC38
|
||||
:10168000232CB4FCB76702811387C71F8327C4FDCF
|
||||
:10169000B307F700130710002380E7008327C4FD7A
|
||||
:1016A0006390070CA30104FE232604FE6F00800A4A
|
||||
:1016B000232604FE232404FE6F004003B767028143
|
||||
:1016C0001387C71F832784FEB307F70083C707006C
|
||||
:1016D000638807008327C4FE938717002326F4FE40
|
||||
:1016E000832784FE938717002324F4FE032784FEB8
|
||||
:1016F000832784FDE344F7FC0327C4FE832784FD8E
|
||||
:10170000631AF704232204FE6F000004B767028106
|
||||
:101710001387C71F832744FEB307F7002380070002
|
||||
:10172000B7970281130710002382E72C130560048A
|
||||
:10173000EFF0DFEFB79702812382072C832744FE67
|
||||
:10174000938717002322F4FE032744FE832784FD9A
|
||||
:10175000E34EF7FA834734FEE39C07F46F00400240
|
||||
:1017600013000000B797028183C7472C93C7170067
|
||||
:1017700093F7F70FE39807FE13054006EFF01FEB12
|
||||
:10178000130000008320C10203248102130101031E
|
||||
:1017900067800000130101FF23268100130401016B
|
||||
:1017A0009307000013080000138507009305080045
|
||||
:1017B0000324C1001301010167800000130101FE31
|
||||
:1017C000232E810013040102232604FE6F008004EF
|
||||
:1017D000B76702810327C4FE131727009387C72129
|
||||
:1017E000B307F7001307300023A0E700B7770281A3
|
||||
:1017F0000327C4FE131727009387C721B307F700F9
|
||||
:101800001307200023A0E7008327C4FE9387170057
|
||||
:101810002326F4FE0327C4FE9307F00FE3DAE7FA6A
|
||||
:10182000130000000324C1011301010267800000BE
|
||||
:10183000130101FD23261102232481021304010355
|
||||
:10184000232EA4FCB707008113858711EFE0DFF892
|
||||
:10185000232604FE6F0080058327C4FE638E0700E5
|
||||
:101860008327C4FE93F7F70063980700B70700814A
|
||||
:101870001385C713EFE05FF68327C4FE9397270015
|
||||
:101880000327C4FDB307F70083A7070013850700EC
|
||||
:10189000EFE05FF8B707008113850714EFE0DFF38F
|
||||
:1018A0008327C4FE938717002326F4FE0327C4FE74
|
||||
:1018B0009307F00FE3D2E7FAB707008113854714C7
|
||||
:1018C000EFE09FF1130000008320C1020324810296
|
||||
:1018D0001301010367800000130101FF232611009B
|
||||
:1018E0002324810013040101EFF05FEDB76702814B
|
||||
:1018F0001385C721EFF0DFF393070000138507007E
|
||||
:101900008320C100032481001301010167800000CE
|
||||
:02000004810079
|
||||
:10000000300000003100000032000000330000002A
|
||||
:10001000340000003500000036000000370000000A
|
||||
|
|
|
|||
|
|
@ -9,6 +9,9 @@ _start:
|
|||
la a0, 0xFF003300
|
||||
li a1, 7
|
||||
sw a1, 4(a0)
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
lw a2, 4(a0)
|
||||
li a0, 0
|
||||
.word 0x0005006b # tmc a0
|
||||
|
|
|
|||
|
|
@ -13,7 +13,7 @@ COMP=--compiler gcc
|
|||
|
||||
WNO=-Wno-UNOPTFLAT -Wno-UNDRIVEN --Wno-PINMISSING -Wno-STMTDLY -Wno-WIDTH -Wno-UNSIGNED
|
||||
|
||||
LIGHTW=-Wno-UNOPTFLAT --Wno-PINMISSING -Wno-WIDTH -Wno-STMTDLY
|
||||
LIGHTW=-Wno-UNOPTFLAT
|
||||
# LIB=-LDFLAGS '-L/usr/local/systemc/'
|
||||
LIB=
|
||||
|
||||
|
|
@ -27,7 +27,7 @@ MAKECPP=(cd obj_dir && make -j -f VVortex.mk)
|
|||
# -LDFLAGS '-lsystemc'
|
||||
VERILATOR:
|
||||
echo "#define VCD_OFF" > simulate/tb_debug.h
|
||||
verilator $(COMP) -cc $(FILE) $(INCLUDE) $(EXE) $(LIB) $(CF)
|
||||
verilator $(COMP) -cc $(FILE) $(INCLUDE) $(EXE) $(LIB) $(CF) $(LIGHTW)
|
||||
|
||||
VERILATORnoWarnings:
|
||||
echo "#define VCD_OFF" > simulate/tb_debug.h
|
||||
|
|
|
|||
|
|
@ -9,6 +9,7 @@
|
|||
// Uncomment the below line if NW=1
|
||||
// `define ONLY
|
||||
|
||||
// `define SYN 1
|
||||
|
||||
|
||||
`define NUMBER_BANKS 8
|
||||
|
|
|
|||
210
rtl/VX_gpr.v
210
rtl/VX_gpr.v
|
|
@ -11,116 +11,122 @@ module VX_gpr (
|
|||
output reg[`NT_M1:0][31:0] out_b_reg_data
|
||||
);
|
||||
|
||||
|
||||
|
||||
wire write_enable;
|
||||
|
||||
assign write_enable = valid_write_request && ((VX_writeback_inter.wb != 0) && (VX_writeback_inter.rd != 5'h0));
|
||||
|
||||
byte_enabled_simple_dual_port_ram first_ram(
|
||||
.we (write_enable),
|
||||
.clk (clk),
|
||||
.waddr (VX_writeback_inter.rd),
|
||||
.raddr1(VX_gpr_read.rs1),
|
||||
.raddr2(VX_gpr_read.rs2),
|
||||
.be (VX_writeback_inter.wb_valid),
|
||||
.wdata (VX_writeback_inter.write_data),
|
||||
.q1 (out_a_reg_data),
|
||||
.q2 (out_b_reg_data)
|
||||
);
|
||||
|
||||
`ifndef SYN
|
||||
|
||||
byte_enabled_simple_dual_port_ram first_ram(
|
||||
.we (write_enable),
|
||||
.clk (clk),
|
||||
.waddr (VX_writeback_inter.rd),
|
||||
.raddr1(VX_gpr_read.rs1),
|
||||
.raddr2(VX_gpr_read.rs2),
|
||||
.be (VX_writeback_inter.wb_valid),
|
||||
.wdata (VX_writeback_inter.write_data),
|
||||
.q1 (out_a_reg_data),
|
||||
.q2 (out_b_reg_data)
|
||||
);
|
||||
|
||||
`else
|
||||
wire[`NT_M1:0][31:0] write_bit_mask;
|
||||
|
||||
genvar curr_t;
|
||||
for (curr_t = 0; curr_t < `NT; curr_t=curr_t+1) begin
|
||||
wire local_write = write_enable & VX_writeback_inter.wb_valid[curr_t];
|
||||
assign write_bit_mask[curr_t] = {32{~local_write}};
|
||||
end
|
||||
|
||||
wire going_to_write = write_enable & (|VX_writeback_inter.wb_valid);
|
||||
|
||||
|
||||
// wire[`NT_M1:0][31:0] write_bit_mask;
|
||||
wire cenb = !going_to_write;
|
||||
|
||||
// genvar curr_t;
|
||||
// for (curr_t = 0; curr_t < `NT; curr_t=curr_t+1) begin
|
||||
// wire local_write = write_enable & VX_writeback_inter.wb_valid[curr_t];
|
||||
// assign write_bit_mask[curr_t] = {32{~local_write}};
|
||||
// end
|
||||
wire cena_1 = (VX_gpr_read.rs1 == 0);
|
||||
wire cena_2 = (VX_gpr_read.rs2 == 0);
|
||||
|
||||
// wire going_to_write = write_enable & (|VX_writeback_inter.wb_valid);
|
||||
// wire[127:0] write_bit_mask = {{32{~(VX_writeback_inter.wb_valid[3])}}, {32{~(VX_writeback_inter.wb_valid[2])}}, {32{~(VX_writeback_inter.wb_valid[1])}}, {32{~(VX_writeback_inter.wb_valid[0])}}};
|
||||
/* verilator lint_off PINCONNECTEMPTY */
|
||||
rf2_32x128_wm1 first_ram (
|
||||
.CENYA(),
|
||||
.AYA(),
|
||||
.CENYB(),
|
||||
.WENYB(),
|
||||
.AYB(),
|
||||
.QA(out_a_reg_data),
|
||||
.SOA(),
|
||||
.SOB(),
|
||||
.CLKA(clk),
|
||||
.CENA(cena_1),
|
||||
.AA(VX_gpr_read.rs1),
|
||||
.CLKB(clk),
|
||||
.CENB(cenb),
|
||||
.WENB(write_bit_mask),
|
||||
.AB(VX_writeback_inter.rd),
|
||||
.DB(VX_writeback_inter.write_data),
|
||||
.EMAA(3'b011),
|
||||
.EMASA(1'b0),
|
||||
.EMAB(3'b011),
|
||||
.TENA(1'b1),
|
||||
.TCENA(1'b0),
|
||||
.TAA(5'b0),
|
||||
.TENB(1'b1),
|
||||
.TCENB(1'b0),
|
||||
.TWENB(128'b0),
|
||||
.TAB(5'b0),
|
||||
.TDB(128'b0),
|
||||
.RET1N(1'b1),
|
||||
.SIA(2'b0),
|
||||
.SEA(1'b0),
|
||||
.DFTRAMBYP(1'b0),
|
||||
.SIB(2'b0),
|
||||
.SEB(1'b0),
|
||||
.COLLDISN(1'b1)
|
||||
);
|
||||
/* verilator lint_on PINCONNECTEMPTY */
|
||||
|
||||
|
||||
// wire cenb = !going_to_write;
|
||||
|
||||
// wire cena_1 = (VX_gpr_read.rs1 == 0);
|
||||
// wire cena_2 = (VX_gpr_read.rs2 == 0);
|
||||
|
||||
// // wire[127:0] write_bit_mask = {{32{~(VX_writeback_inter.wb_valid[3])}}, {32{~(VX_writeback_inter.wb_valid[2])}}, {32{~(VX_writeback_inter.wb_valid[1])}}, {32{~(VX_writeback_inter.wb_valid[0])}}};
|
||||
// /* verilator lint_off PINCONNECTEMPTY */
|
||||
// rf2_32x128_wm1 first_ram (
|
||||
// .CENYA(),
|
||||
// .AYA(),
|
||||
// .CENYB(),
|
||||
// .WENYB(),
|
||||
// .AYB(),
|
||||
// .QA(out_a_reg_data),
|
||||
// .SOA(),
|
||||
// .SOB(),
|
||||
// .CLKA(clk),
|
||||
// .CENA(cena_1),
|
||||
// .AA(VX_gpr_read.rs1),
|
||||
// .CLKB(clk),
|
||||
// .CENB(cenb),
|
||||
// .WENB(write_bit_mask),
|
||||
// .AB(VX_writeback_inter.rd),
|
||||
// .DB(VX_writeback_inter.write_data),
|
||||
// .EMAA(3'b011),
|
||||
// .EMASA(1'b0),
|
||||
// .EMAB(3'b011),
|
||||
// .TENA(1'b1),
|
||||
// .TCENA(1'b0),
|
||||
// .TAA(5'b0),
|
||||
// .TENB(1'b1),
|
||||
// .TCENB(1'b0),
|
||||
// .TWENB(128'b0),
|
||||
// .TAB(5'b0),
|
||||
// .TDB(128'b0),
|
||||
// .RET1N(1'b1),
|
||||
// .SIA(2'b0),
|
||||
// .SEA(1'b0),
|
||||
// .DFTRAMBYP(1'b0),
|
||||
// .SIB(2'b0),
|
||||
// .SEB(1'b0),
|
||||
// .COLLDISN(1'b1)
|
||||
// );
|
||||
// /* verilator lint_on PINCONNECTEMPTY */
|
||||
|
||||
// /* verilator lint_off PINCONNECTEMPTY */
|
||||
// rf2_32x128_wm1 second_ram (
|
||||
// .CENYA(),
|
||||
// .AYA(),
|
||||
// .CENYB(),
|
||||
// .WENYB(),
|
||||
// .AYB(),
|
||||
// .QA(out_b_reg_data),
|
||||
// .SOA(),
|
||||
// .SOB(),
|
||||
// .CLKA(clk),
|
||||
// .CENA(cena_2),
|
||||
// .AA(VX_gpr_read.rs2),
|
||||
// .CLKB(clk),
|
||||
// .CENB(cenb),
|
||||
// .WENB(write_bit_mask),
|
||||
// .AB(VX_writeback_inter.rd),
|
||||
// .DB(VX_writeback_inter.write_data),
|
||||
// .EMAA(3'b011),
|
||||
// .EMASA(1'b0),
|
||||
// .EMAB(3'b011),
|
||||
// .TENA(1'b1),
|
||||
// .TCENA(1'b0),
|
||||
// .TAA(5'b0),
|
||||
// .TENB(1'b1),
|
||||
// .TCENB(1'b0),
|
||||
// .TWENB(128'b0),
|
||||
// .TAB(5'b0),
|
||||
// .TDB(128'b0),
|
||||
// .RET1N(1'b1),
|
||||
// .SIA(2'b0),
|
||||
// .SEA(1'b0),
|
||||
// .DFTRAMBYP(1'b0),
|
||||
// .SIB(2'b0),
|
||||
// .SEB(1'b0),
|
||||
// .COLLDISN(1'b1)
|
||||
// );
|
||||
// /* verilator lint_on PINCONNECTEMPTY */
|
||||
/* verilator lint_off PINCONNECTEMPTY */
|
||||
rf2_32x128_wm1 second_ram (
|
||||
.CENYA(),
|
||||
.AYA(),
|
||||
.CENYB(),
|
||||
.WENYB(),
|
||||
.AYB(),
|
||||
.QA(out_b_reg_data),
|
||||
.SOA(),
|
||||
.SOB(),
|
||||
.CLKA(clk),
|
||||
.CENA(cena_2),
|
||||
.AA(VX_gpr_read.rs2),
|
||||
.CLKB(clk),
|
||||
.CENB(cenb),
|
||||
.WENB(write_bit_mask),
|
||||
.AB(VX_writeback_inter.rd),
|
||||
.DB(VX_writeback_inter.write_data),
|
||||
.EMAA(3'b011),
|
||||
.EMASA(1'b0),
|
||||
.EMAB(3'b011),
|
||||
.TENA(1'b1),
|
||||
.TCENA(1'b0),
|
||||
.TAA(5'b0),
|
||||
.TENB(1'b1),
|
||||
.TCENB(1'b0),
|
||||
.TWENB(128'b0),
|
||||
.TAB(5'b0),
|
||||
.TDB(128'b0),
|
||||
.RET1N(1'b1),
|
||||
.SIA(2'b0),
|
||||
.SEA(1'b0),
|
||||
.DFTRAMBYP(1'b0),
|
||||
.SIB(2'b0),
|
||||
.SEB(1'b0),
|
||||
.COLLDISN(1'b1)
|
||||
);
|
||||
/* verilator lint_on PINCONNECTEMPTY */
|
||||
`endif
|
||||
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -82,7 +82,7 @@ module VX_gpr_stage (
|
|||
wire flush_rest = schedule_delay;
|
||||
|
||||
|
||||
wire stall_lsu = is_lsu && memory_delay;
|
||||
wire stall_lsu = memory_delay;
|
||||
wire flush_lsu = schedule_delay && !stall_lsu;
|
||||
|
||||
|
||||
|
|
|
|||
268
rtl/cache/VX_cache_data.v
vendored
268
rtl/cache/VX_cache_data.v
vendored
|
|
@ -27,167 +27,169 @@ module VX_cache_data (
|
|||
wire currently_writing = (|we);
|
||||
wire update_dirty = ((!dirty_use) && currently_writing) || (evict);
|
||||
|
||||
/////////////////
|
||||
|
||||
// (3:0) 4 bytes
|
||||
reg[`NUM_WORDS_PER_BLOCK-1:0][31:0] data[NUMBER_INDEXES-1:0]; // Actual Data
|
||||
reg[16:0] tag[NUMBER_INDEXES-1:0];
|
||||
reg valid[NUMBER_INDEXES-1:0];
|
||||
reg dirty[NUMBER_INDEXES-1:0];
|
||||
|
||||
|
||||
// 16 bytes
|
||||
assign data_use = data[addr]; // Read Port
|
||||
assign tag_use = tag[addr];
|
||||
assign valid_use = valid[addr];
|
||||
assign dirty_use = dirty[addr];
|
||||
|
||||
wire dirt_new = evict ? 0 : (|we);
|
||||
|
||||
integer f;
|
||||
always @(posedge clk) begin : dirty_update
|
||||
if (update_dirty) dirty[addr] <= dirt_new; // WRite Port
|
||||
end
|
||||
|
||||
always @(posedge clk) begin : data_update
|
||||
for (f = 0; f < `NUM_WORDS_PER_BLOCK; f = f + 1) begin
|
||||
if (we[f]) data[addr][f] <= data_write[f];
|
||||
end
|
||||
end
|
||||
`ifndef SYN
|
||||
|
||||
always @(posedge clk) begin : tag_update
|
||||
if (evict) tag[addr] <= tag_write;
|
||||
end
|
||||
|
||||
always @(posedge clk) begin : valid_update
|
||||
if (evict) valid[addr] <= 1;
|
||||
end
|
||||
// (3:0) 4 bytes
|
||||
reg[`NUM_WORDS_PER_BLOCK-1:0][31:0] data[NUMBER_INDEXES-1:0]; // Actual Data
|
||||
reg[16:0] tag[NUMBER_INDEXES-1:0];
|
||||
reg valid[NUMBER_INDEXES-1:0];
|
||||
reg dirty[NUMBER_INDEXES-1:0];
|
||||
|
||||
|
||||
//////////////////////////////
|
||||
// 16 bytes
|
||||
assign data_use = data[addr]; // Read Port
|
||||
assign tag_use = tag[addr];
|
||||
assign valid_use = valid[addr];
|
||||
assign dirty_use = dirty[addr];
|
||||
|
||||
|
||||
// wire cena = 1;
|
||||
integer f;
|
||||
always @(posedge clk) begin : dirty_update
|
||||
if (update_dirty) dirty[addr] <= dirt_new; // WRite Port
|
||||
end
|
||||
|
||||
// wire cenb_d = (|we);
|
||||
// wire[`NUM_WORDS_PER_BLOCK-1:0][31:0] wdata_d = data_write;
|
||||
// wire[`NUM_WORDS_PER_BLOCK-1:0][31:0] write_bit_mask_d;
|
||||
// wire[`NUM_WORDS_PER_BLOCK-1:0][31:0] data_out_d;
|
||||
// genvar cur_b;
|
||||
// for (cur_b = 0; cur_b < `NUM_WORDS_PER_BLOCK; cur_b=cur_b+1) begin
|
||||
// assign write_bit_mask_d[cur_b] = {32{~we[cur_b]}};
|
||||
// end
|
||||
// assign data_use = data_out_d;
|
||||
always @(posedge clk) begin : data_update
|
||||
for (f = 0; f < `NUM_WORDS_PER_BLOCK; f = f + 1) begin
|
||||
if (we[f]) data[addr][f] <= data_write[f];
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin : tag_update
|
||||
if (evict) tag[addr] <= tag_write;
|
||||
end
|
||||
|
||||
always @(posedge clk) begin : valid_update
|
||||
if (evict) valid[addr] <= 1;
|
||||
end
|
||||
|
||||
`else
|
||||
|
||||
|
||||
// // Using ASIC MEM
|
||||
// /* verilator lint_off PINCONNECTEMPTY */
|
||||
// rf2_256x128_wm1 data (
|
||||
// .CENYA(),
|
||||
// .AYA(),
|
||||
// .CENYB(),
|
||||
// .WENYB(),
|
||||
// .AYB(),
|
||||
// .QA(data_out_d),
|
||||
// .SOA(),
|
||||
// .SOB(),
|
||||
// .CLKA(clk),
|
||||
// .CENA(cena),
|
||||
// .AA(addr),
|
||||
// .CLKB(clk),
|
||||
// .CENB(cenb_d),
|
||||
// .WENB(write_bit_mask_d),
|
||||
// .AB(addr),
|
||||
// .DB(wdata_d),
|
||||
// .EMAA(3'b011),
|
||||
// .EMASA(1'b0),
|
||||
// .EMAB(3'b011),
|
||||
// .TENA(1'b1),
|
||||
// .TCENA(1'b0),
|
||||
// .TAA(5'b0),
|
||||
// .TENB(1'b1),
|
||||
// .TCENB(1'b0),
|
||||
// .TWENB(128'b0),
|
||||
// .TAB(5'b0),
|
||||
// .TDB(128'b0),
|
||||
// .RET1N(1'b1),
|
||||
// .SIA(2'b0),
|
||||
// .SEA(1'b0),
|
||||
// .DFTRAMBYP(1'b0),
|
||||
// .SIB(2'b0),
|
||||
// .SEB(1'b0),
|
||||
// .COLLDISN(1'b1)
|
||||
// );
|
||||
// /* verilator lint_on PINCONNECTEMPTY */
|
||||
wire cena = 1;
|
||||
|
||||
wire cenb_d = (|we);
|
||||
wire[`NUM_WORDS_PER_BLOCK-1:0][31:0] wdata_d = data_write;
|
||||
wire[`NUM_WORDS_PER_BLOCK-1:0][31:0] write_bit_mask_d;
|
||||
wire[`NUM_WORDS_PER_BLOCK-1:0][31:0] data_out_d;
|
||||
genvar cur_b;
|
||||
for (cur_b = 0; cur_b < `NUM_WORDS_PER_BLOCK; cur_b=cur_b+1) begin
|
||||
assign write_bit_mask_d[cur_b] = {32{~we[cur_b]}};
|
||||
end
|
||||
assign data_use = data_out_d;
|
||||
|
||||
|
||||
// Using ASIC MEM
|
||||
/* verilator lint_off PINCONNECTEMPTY */
|
||||
rf2_256x128_wm1 data (
|
||||
.CENYA(),
|
||||
.AYA(),
|
||||
.CENYB(),
|
||||
.WENYB(),
|
||||
.AYB(),
|
||||
.QA(data_out_d),
|
||||
.SOA(),
|
||||
.SOB(),
|
||||
.CLKA(clk),
|
||||
.CENA(cena),
|
||||
.AA(addr),
|
||||
.CLKB(clk),
|
||||
.CENB(cenb_d),
|
||||
.WENB(write_bit_mask_d),
|
||||
.AB(addr),
|
||||
.DB(wdata_d),
|
||||
.EMAA(3'b011),
|
||||
.EMASA(1'b0),
|
||||
.EMAB(3'b011),
|
||||
.TENA(1'b1),
|
||||
.TCENA(1'b0),
|
||||
.TAA(5'b0),
|
||||
.TENB(1'b1),
|
||||
.TCENB(1'b0),
|
||||
.TWENB(128'b0),
|
||||
.TAB(5'b0),
|
||||
.TDB(128'b0),
|
||||
.RET1N(1'b1),
|
||||
.SIA(2'b0),
|
||||
.SEA(1'b0),
|
||||
.DFTRAMBYP(1'b0),
|
||||
.SIB(2'b0),
|
||||
.SEB(1'b0),
|
||||
.COLLDISN(1'b1)
|
||||
);
|
||||
/* verilator lint_on PINCONNECTEMPTY */
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
// wire[16:0] old_tag;
|
||||
// wire old_valid;
|
||||
// wire old_dirty;
|
||||
wire[16:0] old_tag;
|
||||
wire old_valid;
|
||||
wire old_dirty;
|
||||
|
||||
// wire[16:0] new_tag = evict ? tag_write : old_tag;
|
||||
// wire new_valid = evict ? 1 : old_valid;
|
||||
// wire new_dirty = update_dirty ? new_dirty : old_dirty;
|
||||
wire[16:0] new_tag = evict ? tag_write : old_tag;
|
||||
wire new_valid = evict ? 1 : old_valid;
|
||||
wire new_dirty = update_dirty ? dirt_new : old_dirty;
|
||||
|
||||
|
||||
// wire cenb_m = (evict || update_dirty);
|
||||
// wire[19-1:0][31:0] write_bit_mask_m = cenb_m ? 19'b0 : 19'b1;
|
||||
wire cenb_m = (evict || update_dirty);
|
||||
wire[19-1:0][31:0] write_bit_mask_m = cenb_m ? 19'b0 : 19'b1;
|
||||
|
||||
|
||||
|
||||
|
||||
// wire[`NUM_WORDS_PER_BLOCK-1:0][31:0] wdata_m = {new_tag, new_dirty, new_valid};
|
||||
// wire[`NUM_WORDS_PER_BLOCK-1:0][31:0] data_out_m;
|
||||
wire[`NUM_WORDS_PER_BLOCK-1:0][31:0] wdata_m = {new_tag, new_dirty, new_valid};
|
||||
wire[`NUM_WORDS_PER_BLOCK-1:0][31:0] data_out_m;
|
||||
|
||||
// assign {old_tag, old_dirty, old_valid} = data_out_m;
|
||||
assign {old_tag, old_dirty, old_valid} = data_out_m;
|
||||
|
||||
|
||||
// assign dirty_use = old_dirty;
|
||||
// assign valid_use = old_valid;
|
||||
// assign tag_use = old_tag;
|
||||
assign dirty_use = old_dirty;
|
||||
assign valid_use = old_valid;
|
||||
assign tag_use = old_tag;
|
||||
|
||||
// /* verilator lint_off PINCONNECTEMPTY */
|
||||
// rf2_256x19_wm0 meta (
|
||||
// .CENYA(),
|
||||
// .AYA(),
|
||||
// .CENYB(),
|
||||
// // .WENYB(),
|
||||
// .AYB(),
|
||||
// .QA(data_out_m),
|
||||
// .SOA(),
|
||||
// .SOB(),
|
||||
// .CLKA(clk),
|
||||
// .CENA(cena),
|
||||
// .AA(addr),
|
||||
// .CLKB(clk),
|
||||
// .CENB(cenb_m),
|
||||
// // .WENB(write_bit_mask_m),
|
||||
// .AB(addr),
|
||||
// .DB(wdata_m),
|
||||
// .EMAA(3'b011),
|
||||
// .EMASA(1'b0),
|
||||
// .EMAB(3'b011),
|
||||
// .TENA(1'b1),
|
||||
// .TCENA(1'b0),
|
||||
// .TAA(5'b0),
|
||||
// .TENB(1'b1),
|
||||
// .TCENB(1'b0),
|
||||
// // .TWENB(128'b0),
|
||||
// .TAB(5'b0),
|
||||
// .TDB(128'b0),
|
||||
// .RET1N(1'b1),
|
||||
// .SIA(2'b0),
|
||||
// .SEA(1'b0),
|
||||
// .DFTRAMBYP(1'b0),
|
||||
// .SIB(2'b0),
|
||||
// .SEB(1'b0),
|
||||
// .COLLDISN(1'b1)
|
||||
// );
|
||||
// /* verilator lint_on PINCONNECTEMPTY */
|
||||
/* verilator lint_off PINCONNECTEMPTY */
|
||||
rf2_256x19_wm0 meta (
|
||||
.CENYA(),
|
||||
.AYA(),
|
||||
.CENYB(),
|
||||
// .WENYB(),
|
||||
.AYB(),
|
||||
.QA(data_out_m),
|
||||
.SOA(),
|
||||
.SOB(),
|
||||
.CLKA(clk),
|
||||
.CENA(cena),
|
||||
.AA(addr),
|
||||
.CLKB(clk),
|
||||
.CENB(cenb_m),
|
||||
// .WENB(write_bit_mask_m),
|
||||
.AB(addr),
|
||||
.DB(wdata_m),
|
||||
.EMAA(3'b011),
|
||||
.EMASA(1'b0),
|
||||
.EMAB(3'b011),
|
||||
.TENA(1'b1),
|
||||
.TCENA(1'b0),
|
||||
.TAA(5'b0),
|
||||
.TENB(1'b1),
|
||||
.TCENB(1'b0),
|
||||
// .TWENB(128'b0),
|
||||
.TAB(5'b0),
|
||||
.TDB(128'b0),
|
||||
.RET1N(1'b1),
|
||||
.SIA(2'b0),
|
||||
.SEA(1'b0),
|
||||
.DFTRAMBYP(1'b0),
|
||||
.SIB(2'b0),
|
||||
.SEB(1'b0),
|
||||
.COLLDISN(1'b1)
|
||||
);
|
||||
/* verilator lint_on PINCONNECTEMPTY */
|
||||
|
||||
|
||||
`endif
|
||||
|
||||
endmodule
|
||||
|
|
@ -1,7 +0,0 @@
|
|||
# Dynamic Instructions: 14
|
||||
# of total cycles: 26
|
||||
# of forwarding stalls: 0
|
||||
# of branch stalls: 0
|
||||
# CPI: 1.85714
|
||||
# time to simulate: 6.95313e-310 milliseconds
|
||||
# GRADE: Failed on test: 4294967295
|
||||
|
|
@ -16,73 +16,84 @@ module VX_priority_encoder_sm
|
|||
// To SM Module
|
||||
output reg[NB:0] out_valid,
|
||||
output reg[NB:0][31:0] out_address,
|
||||
output reg[NB:0][31:0] out_data,
|
||||
output reg[NB:0][31:0] out_data,
|
||||
|
||||
// To Processor
|
||||
output wire[NB:0][1:0] req_num,
|
||||
output reg stall,
|
||||
output wire send_data // Finished all of the requests
|
||||
output wire send_data // Finished all of the requests
|
||||
);
|
||||
|
||||
wire[NB:0][`NT_M1:0] bank_valids;
|
||||
wire[NB:0][`NT_M1:0] temp_bank_valids;
|
||||
reg[NB:0][`NT_M1:0] temp_valid; // State - If there's any ones here, then stall
|
||||
wire[NB:0] temp_stall;
|
||||
integer counter[NB:0] ;
|
||||
wire[NB:0][`NT_M1:0] mask;
|
||||
wire[NB:0] update_temp_valid;
|
||||
reg[NB:0] req_done;
|
||||
reg[`NT_M1:0] left_requests;
|
||||
|
||||
VX_bank_valids #(.NB(NB), .BITS_PER_BANK(BITS_PER_BANK)) vx_bank_valid(
|
||||
.in_valids(in_valid),
|
||||
.in_addr(in_address),
|
||||
.bank_valids(bank_valids)
|
||||
);
|
||||
|
||||
genvar j;
|
||||
for(j=0; j <= NB; j++) begin
|
||||
assign temp_stall[j] = ($countones(temp_valid[j]) != 0);
|
||||
assign temp_bank_valids[j] = (temp_stall[j] || req_done[j]) ? temp_valid[j] : bank_valids[j];
|
||||
assign update_temp_valid[j] = !req_done[j] && ($countones(bank_valids[j]) > 1);
|
||||
|
||||
VX_generic_priority_encoder #(.N(4)) vx_priority_encoder(
|
||||
.valids(temp_bank_valids[j]),
|
||||
.index(req_num[j]),
|
||||
.found(out_valid[j])
|
||||
);
|
||||
|
||||
VX_set_bit vx_set_bit(
|
||||
.index(req_num[j]),
|
||||
.mask (mask[j])
|
||||
);
|
||||
|
||||
assign out_address[j] = out_valid[j] ? in_address[req_num[j]] : 0;
|
||||
assign out_data[j] = out_valid[j] ? in_data[req_num[j]] : 0;
|
||||
end
|
||||
wire[`NT_M1:0] use_valid;
|
||||
|
||||
|
||||
assign stall = |temp_stall;
|
||||
assign send_data = &req_done;
|
||||
wire requests_left = (|left_requests);
|
||||
|
||||
genvar i;
|
||||
always @(posedge clk) begin
|
||||
for(i = 0; i <= NB; i = i+1) begin
|
||||
if (update_temp_valid[i]) begin
|
||||
counter[i] <= counter[i] + 1;
|
||||
if(counter[i] == 0) temp_valid[i] <= bank_valids[i] & mask[i];
|
||||
else if (counter[i] > 0) temp_valid[i] <= temp_bank_valids[i] & mask[i];
|
||||
end
|
||||
if(($countones(in_valid) > 0) && ($countones(bank_valids[i]) == 0)) begin
|
||||
req_done[i] <= 1;
|
||||
end
|
||||
else if((counter[i][2:0] == ($countones(bank_valids[i])-1))) begin
|
||||
req_done[i] <= 1;
|
||||
counter[i] <= 0;
|
||||
end
|
||||
else begin
|
||||
req_done[i] <= 0;
|
||||
assign use_valid = (requests_left) ? left_requests : in_valid;
|
||||
|
||||
|
||||
wire[NB:0][`NT_M1:0] bank_valids;
|
||||
VX_bank_valids #(.NB(NB), .BITS_PER_BANK(BITS_PER_BANK)) vx_bank_valid(
|
||||
.in_valids(use_valid),
|
||||
.in_addr(in_address),
|
||||
.bank_valids(bank_valids)
|
||||
);
|
||||
|
||||
wire[NB:0] more_than_one_valid;
|
||||
|
||||
genvar curr_bank;
|
||||
for (curr_bank = 0; curr_bank <= NB; curr_bank = curr_bank + 1)
|
||||
begin
|
||||
assign more_than_one_valid[curr_bank] = $countones(bank_valids[curr_bank]) > 1;
|
||||
end
|
||||
|
||||
|
||||
assign stall = (|more_than_one_valid);
|
||||
assign send_data = (!stall) && (|in_valid); // change
|
||||
|
||||
wire[NB:0][1:0] internal_req_num;
|
||||
wire[NB:0] internal_out_valid;
|
||||
|
||||
|
||||
// There's one or less valid per bank
|
||||
genvar curr_bank_o;
|
||||
for (curr_bank_o = 0; curr_bank_o <= NB; curr_bank_o = curr_bank_o + 1)
|
||||
begin
|
||||
|
||||
VX_generic_priority_encoder #(.N(4)) vx_priority_encoder(
|
||||
.valids(bank_valids[curr_bank_o]),
|
||||
.index(internal_req_num[curr_bank_o]),
|
||||
.found(internal_out_valid[curr_bank_o])
|
||||
);
|
||||
assign out_address[curr_bank_o] = internal_out_valid[curr_bank_o] ? in_address[internal_req_num[curr_bank_o]] : 0;
|
||||
assign out_data[curr_bank_o] = internal_out_valid[curr_bank_o] ? in_data[internal_req_num[curr_bank_o]] : 0;
|
||||
end
|
||||
|
||||
reg[`NT_M1:0] serviced;
|
||||
genvar curr_b;
|
||||
always @(*) begin
|
||||
serviced = 0;
|
||||
for (curr_b = 0; curr_b <= NB; curr_b=curr_b+1) begin
|
||||
serviced[internal_req_num[curr_b]] = 1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
assign req_num = internal_req_num;
|
||||
assign out_valid = internal_out_valid;
|
||||
|
||||
|
||||
wire[`NT_M1:0] serviced_qual = in_valid & (serviced);
|
||||
|
||||
wire[`NT_M1:0] new_left_requests = (left_requests == 0) ? (in_valid & ~serviced_qual) : (left_requests & ~ serviced_qual);
|
||||
|
||||
// wire[`NT_M1:0] new_left_requests = left_requests & ~(serviced_qual);
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (!stall) left_requests <= 0;
|
||||
else left_requests <= new_left_requests;
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
|
@ -9,73 +9,78 @@ module VX_shared_memory_block (
|
|||
|
||||
);
|
||||
|
||||
logic [3:0][31:0] shared_memory[127:0];
|
||||
|
||||
//wire need_to_write = (|we);
|
||||
`ifndef SYN
|
||||
|
||||
always @(posedge clk) begin
|
||||
if(shm_write) begin
|
||||
if (we == 2'b00) shared_memory[addr][0][31:0] <= wdata[0][31:0];
|
||||
if (we == 2'b01) shared_memory[addr][1][31:0] <= wdata[1][31:0];
|
||||
if (we == 2'b10) shared_memory[addr][2][31:0] <= wdata[2][31:0];
|
||||
if (we == 2'b11) shared_memory[addr][3][31:0] <= wdata[3][31:0];
|
||||
logic [3:0][31:0] shared_memory[127:0];
|
||||
|
||||
//wire need_to_write = (|we);
|
||||
|
||||
always @(posedge clk) begin
|
||||
if(shm_write) begin
|
||||
if (we == 2'b00) shared_memory[addr][0][31:0] <= wdata[0][31:0];
|
||||
if (we == 2'b01) shared_memory[addr][1][31:0] <= wdata[1][31:0];
|
||||
if (we == 2'b10) shared_memory[addr][2][31:0] <= wdata[2][31:0];
|
||||
if (we == 2'b11) shared_memory[addr][3][31:0] <= wdata[3][31:0];
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
assign data_out = shm_write ? 0 : shared_memory[addr];
|
||||
assign data_out = shm_write ? 0 : shared_memory[addr];
|
||||
|
||||
`else
|
||||
|
||||
wire cena = 1;
|
||||
wire cenb = shm_write;
|
||||
|
||||
wire[3:0][31:0] write_bit_mask;
|
||||
|
||||
assign write_bit_mask[0] = (we == 2'b00) ? 1 : {32{1'b0}};
|
||||
assign write_bit_mask[1] = (we == 2'b01) ? 1 : {32{1'b0}};
|
||||
assign write_bit_mask[2] = (we == 2'b10) ? 1 : {32{1'b0}};
|
||||
assign write_bit_mask[3] = (we == 2'b11) ? 1 : {32{1'b0}};
|
||||
|
||||
// Using ASIC MEM
|
||||
/* verilator lint_off PINCONNECTEMPTY */
|
||||
rf2_128x128_wm1 first_ram (
|
||||
.CENYA(),
|
||||
.AYA(),
|
||||
.CENYB(),
|
||||
.WENYB(),
|
||||
.AYB(),
|
||||
.QA(data_out),
|
||||
.SOA(),
|
||||
.SOB(),
|
||||
.CLKA(clk),
|
||||
.CENA(cena),
|
||||
.AA(addr),
|
||||
.CLKB(clk),
|
||||
.CENB(cenb),
|
||||
.WENB(write_bit_mask),
|
||||
.AB(addr),
|
||||
.DB(wdata),
|
||||
.EMAA(3'b011),
|
||||
.EMASA(1'b0),
|
||||
.EMAB(3'b011),
|
||||
.TENA(1'b1),
|
||||
.TCENA(1'b0),
|
||||
.TAA(5'b0),
|
||||
.TENB(1'b1),
|
||||
.TCENB(1'b0),
|
||||
.TWENB(128'b0),
|
||||
.TAB(5'b0),
|
||||
.TDB(128'b0),
|
||||
.RET1N(1'b1),
|
||||
.SIA(2'b0),
|
||||
.SEA(1'b0),
|
||||
.DFTRAMBYP(1'b0),
|
||||
.SIB(2'b0),
|
||||
.SEB(1'b0),
|
||||
.COLLDISN(1'b1)
|
||||
);
|
||||
/* verilator lint_on PINCONNECTEMPTY */
|
||||
|
||||
|
||||
|
||||
|
||||
// wire cena = 1;
|
||||
// wire cenb = shm_write;
|
||||
|
||||
// wire[3:0][31:0] write_bit_mask;
|
||||
|
||||
// assign write_bit_mask[0] = (we == 2'b00) ? 1 : {32{1'b0}};
|
||||
// assign write_bit_mask[1] = (we == 2'b01) ? 1 : {32{1'b0}};
|
||||
// assign write_bit_mask[2] = (we == 2'b10) ? 1 : {32{1'b0}};
|
||||
// assign write_bit_mask[3] = (we == 2'b11) ? 1 : {32{1'b0}};
|
||||
|
||||
// // Using ASIC MEM
|
||||
// /* verilator lint_off PINCONNECTEMPTY */
|
||||
// rf2_128x128_wm1 first_ram (
|
||||
// .CENYA(),
|
||||
// .AYA(),
|
||||
// .CENYB(),
|
||||
// .WENYB(),
|
||||
// .AYB(),
|
||||
// .QA(data_out),
|
||||
// .SOA(),
|
||||
// .SOB(),
|
||||
// .CLKA(clk),
|
||||
// .CENA(cena),
|
||||
// .AA(addr),
|
||||
// .CLKB(clk),
|
||||
// .CENB(cenb),
|
||||
// .WENB(write_bit_mask),
|
||||
// .AB(addr),
|
||||
// .DB(wdata),
|
||||
// .EMAA(3'b011),
|
||||
// .EMASA(1'b0),
|
||||
// .EMAB(3'b011),
|
||||
// .TENA(1'b1),
|
||||
// .TCENA(1'b0),
|
||||
// .TAA(5'b0),
|
||||
// .TENB(1'b1),
|
||||
// .TCENB(1'b0),
|
||||
// .TWENB(128'b0),
|
||||
// .TAB(5'b0),
|
||||
// .TDB(128'b0),
|
||||
// .RET1N(1'b1),
|
||||
// .SIA(2'b0),
|
||||
// .SEA(1'b0),
|
||||
// .DFTRAMBYP(1'b0),
|
||||
// .SIB(2'b0),
|
||||
// .SEB(1'b0),
|
||||
// .COLLDISN(1'b1)
|
||||
// );
|
||||
// /* verilator lint_on PINCONNECTEMPTY */
|
||||
`endif
|
||||
|
||||
endmodule
|
||||
|
|
@ -1 +1 @@
|
|||
#define VCD_OFF
|
||||
#define VCD_OUTPUT
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue