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This commit is contained in:
trmontgomery 2020-07-13 23:51:26 -04:00
parent 121cc5a826
commit 172e6d09af
10 changed files with 4061 additions and 3349 deletions
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BIN
hw/unit_tests/cache/obj_dir/VVX_cache vendored
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814
hw/unit_tests/cache/obj_dir/VVX_cache.cpp vendored
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@ -13,7 +13,7 @@ CData/*1:0*/ VVX_cache::__Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_ba
CData/*0:0*/ VVX_cache::__Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[16];
IData/*31:0*/ VVX_cache::__Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[16];
CData/*1:0*/ VVX_cache::__Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[16];
CData/*0:0*/ VVX_cache::__Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[16];
CData/*0:0*/ VVX_cache::__Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__grant_valid[16];
IData/*31:0*/ VVX_cache::__Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[16];
CData/*1:0*/ VVX_cache::__Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[16];
CData/*0:0*/ VVX_cache::__Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[16];
@ -1307,8 +1307,8 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) {
vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index
= vlTOPp->__Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index
[vlTOPp->__Vtableidx3];
vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid
= vlTOPp->__Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid
vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__grant_valid
= vlTOPp->__Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__grant_valid
[vlTOPp->__Vtableidx3];
vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i
= vlTOPp->__Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i
@ -2944,8 +2944,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) {
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))))
: VL_ULL(0));
vlTOPp->core_rsp_valid = 0U;
if ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid)
& (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid))
if (((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)
& ((0xffU & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[0U])
== ((0xa7U >= (0xffU & ((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))
@ -2971,115 +2970,100 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) {
| ((IData)(1U) <<
(3U & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid))));
}
if ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid)
& ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)
>> 1U)) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U]
<< 0x16U) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[1U]
>> 0xaU)))
== ((0xa7U >= (0xffU & ((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))
? (0xffU & (((0U == (0x1fU
& ((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))
? 0U : (
vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[
((IData)(1U)
+
(7U
& (((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))
>> 5U)))]
<<
((IData)(0x20U)
-
(0x1fU
& ((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))))
| (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[
(7U & (
((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))
>> 5U))]
>> (0x1fU
& ((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))))
: 0U)))) {
if ((((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)
>> 1U) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U]
<< 0x16U) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[1U]
>> 0xaU)))
== ((0xa7U >= (0xffU & ((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))
? (0xffU & (((0U == (0x1fU
& ((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))
? 0U : (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[
((IData)(1U)
+ (7U
& (((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))
>> 5U)))]
<< ((IData)(0x20U)
-
(0x1fU
& ((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))))
| (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[
(7U & (((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))
>> 5U))]
>> (0x1fU &
((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))))
: 0U)))) {
vlTOPp->core_rsp_valid = ((IData)(vlTOPp->core_rsp_valid)
| ((IData)(1U) <<
(3U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid)
>> 2U))));
}
if ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid)
& ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)
>> 2U)) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U]
<< 0xcU) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U]
>> 0x14U)))
== ((0xa7U >= (0xffU & ((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))
? (0xffU & (((0U == (0x1fU
& ((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))
? 0U : (
vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[
((IData)(1U)
+
(7U
& (((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))
>> 5U)))]
<<
((IData)(0x20U)
-
(0x1fU
& ((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))))
| (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[
(7U & (
((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))
>> 5U))]
>> (0x1fU
& ((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))))
: 0U)))) {
if ((((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)
>> 2U) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U]
<< 0xcU) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U]
>> 0x14U)))
== ((0xa7U >= (0xffU & ((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))
? (0xffU & (((0U == (0x1fU
& ((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))
? 0U : (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[
((IData)(1U)
+ (7U
& (((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))
>> 5U)))]
<< ((IData)(0x20U)
-
(0x1fU
& ((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))))
| (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[
(7U & (((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))
>> 5U))]
>> (0x1fU &
((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))))
: 0U)))) {
vlTOPp->core_rsp_valid = ((IData)(vlTOPp->core_rsp_valid)
| ((IData)(1U) <<
(3U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid)
>> 4U))));
}
if ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid)
& ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)
>> 3U)) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[4U]
<< 2U) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U]
>> 0x1eU)))
== ((0xa7U >= (0xffU & ((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))
? (0xffU & (((0U == (0x1fU
& ((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))
? 0U : (
vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[
((IData)(1U)
+
(7U
& (((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))
>> 5U)))]
<<
((IData)(0x20U)
-
(0x1fU
& ((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))))
| (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[
(7U & (
((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))
>> 5U))]
>> (0x1fU
& ((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))))
: 0U)))) {
if ((((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)
>> 3U) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[4U]
<< 2U) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U]
>> 0x1eU)))
== ((0xa7U >= (0xffU & ((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))
? (0xffU & (((0U == (0x1fU
& ((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))
? 0U : (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[
((IData)(1U)
+ (7U
& (((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))
>> 5U)))]
<< ((IData)(0x20U)
-
(0x1fU
& ((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))))
| (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[
(7U & (((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))
>> 5U))]
>> (0x1fU &
((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))))
: 0U)))) {
vlTOPp->core_rsp_valid = ((IData)(vlTOPp->core_rsp_valid)
| ((IData)(1U) <<
(3U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid)
@ -3089,8 +3073,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) {
vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data[1U] = 0U;
vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data[2U] = 0U;
vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data[3U] = 0U;
if ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid)
& (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid))
if (((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)
& ((0xffU & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[0U])
== ((0xa7U >= (0xffU & ((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))
@ -3116,121 +3099,105 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) {
<< 5U)), vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data,
vlTOPp->VX_cache__DOT__per_bank_core_rsp_data[0U]);
}
if ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid)
& ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)
>> 1U)) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U]
<< 0x16U) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[1U]
>> 0xaU)))
== ((0xa7U >= (0xffU & ((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))
? (0xffU & (((0U == (0x1fU
& ((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))
? 0U : (
vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[
((IData)(1U)
+
(7U
& (((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))
>> 5U)))]
<<
((IData)(0x20U)
-
(0x1fU
& ((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))))
| (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[
(7U & (
((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))
>> 5U))]
>> (0x1fU
& ((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))))
: 0U)))) {
if ((((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)
>> 1U) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U]
<< 0x16U) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[1U]
>> 0xaU)))
== ((0xa7U >= (0xffU & ((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))
? (0xffU & (((0U == (0x1fU
& ((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))
? 0U : (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[
((IData)(1U)
+ (7U
& (((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))
>> 5U)))]
<< ((IData)(0x20U)
-
(0x1fU
& ((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))))
| (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[
(7U & (((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))
>> 5U))]
>> (0x1fU &
((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))))
: 0U)))) {
VL_ASSIGNSEL_WIII(32,(0x60U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid)
<< 3U)), vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data,
vlTOPp->VX_cache__DOT__per_bank_core_rsp_data[1U]);
}
if ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid)
& ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)
>> 2U)) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U]
<< 0xcU) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U]
>> 0x14U)))
== ((0xa7U >= (0xffU & ((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))
? (0xffU & (((0U == (0x1fU
& ((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))
? 0U : (
vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[
((IData)(1U)
+
(7U
& (((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))
>> 5U)))]
<<
((IData)(0x20U)
-
(0x1fU
& ((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))))
| (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[
(7U & (
((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))
>> 5U))]
>> (0x1fU
& ((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))))
: 0U)))) {
if ((((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)
>> 2U) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U]
<< 0xcU) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U]
>> 0x14U)))
== ((0xa7U >= (0xffU & ((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))
? (0xffU & (((0U == (0x1fU
& ((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))
? 0U : (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[
((IData)(1U)
+ (7U
& (((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))
>> 5U)))]
<< ((IData)(0x20U)
-
(0x1fU
& ((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))))
| (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[
(7U & (((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))
>> 5U))]
>> (0x1fU &
((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))))
: 0U)))) {
VL_ASSIGNSEL_WIII(32,(0x60U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid)
<< 1U)), vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data,
vlTOPp->VX_cache__DOT__per_bank_core_rsp_data[2U]);
}
if ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid)
& ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)
>> 3U)) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[4U]
<< 2U) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U]
>> 0x1eU)))
== ((0xa7U >= (0xffU & ((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))
? (0xffU & (((0U == (0x1fU
& ((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))
? 0U : (
vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[
((IData)(1U)
+
(7U
& (((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))
>> 5U)))]
<<
((IData)(0x20U)
-
(0x1fU
& ((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))))
| (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[
(7U & (
((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))
>> 5U))]
>> (0x1fU
& ((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))))
: 0U)))) {
if ((((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)
>> 3U) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[4U]
<< 2U) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U]
>> 0x1eU)))
== ((0xa7U >= (0xffU & ((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))
? (0xffU & (((0U == (0x1fU
& ((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))
? 0U : (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[
((IData)(1U)
+ (7U
& (((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))
>> 5U)))]
<< ((IData)(0x20U)
-
(0x1fU
& ((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))))
| (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[
(7U & (((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))
>> 5U))]
>> (0x1fU &
((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))))
: 0U)))) {
VL_ASSIGNSEL_WIII(32,(0x60U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid)
>> 1U)), vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data,
vlTOPp->VX_cache__DOT__per_bank_core_rsp_data[3U]);
}
vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual
= ((0xeU & (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual))
| (((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid)
& (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid))
| ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)
& ((0xffU & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[0U])
== ((0xa7U >= (0xffU & ((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))
@ -3256,8 +3223,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) {
: 0U))));
vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual
= ((0xdU & (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual))
| (0xfffffffeU & ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid)
<< 1U) & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid))
| (0xfffffffeU & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)
& (((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U]
<< 0x16U)
| (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[1U]
@ -3298,8 +3264,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) {
: 0U)) << 1U))));
vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual
= ((0xbU & (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual))
| (0xfffffffcU & ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid)
<< 2U) & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid))
| (0xfffffffcU & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)
& (((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U]
<< 0xcU)
| (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U]
@ -3340,8 +3305,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) {
: 0U)) << 2U))));
vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual
= ((7U & (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual))
| (0xfffffff8U & ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid)
<< 3U) & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid))
| (0xfffffff8U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)
& (((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[4U]
<< 2U)
| (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U]
@ -19351,8 +19315,8 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym
vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index
= vlTOPp->__Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index
[vlTOPp->__Vtableidx3];
vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid
= vlTOPp->__Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid
vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__grant_valid
= vlTOPp->__Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__grant_valid
[vlTOPp->__Vtableidx3];
vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i
= vlTOPp->__Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i
@ -20069,8 +20033,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))))
: VL_ULL(0));
vlTOPp->core_rsp_valid = 0U;
if ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid)
& (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid))
if (((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)
& ((0xffU & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[0U])
== ((0xa7U >= (0xffU & ((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))
@ -20096,115 +20059,100 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym
| ((IData)(1U) <<
(3U & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid))));
}
if ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid)
& ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)
>> 1U)) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U]
<< 0x16U) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[1U]
>> 0xaU)))
== ((0xa7U >= (0xffU & ((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))
? (0xffU & (((0U == (0x1fU
& ((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))
? 0U : (
vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[
((IData)(1U)
+
(7U
& (((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))
>> 5U)))]
<<
((IData)(0x20U)
-
(0x1fU
& ((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))))
| (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[
(7U & (
((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))
>> 5U))]
>> (0x1fU
& ((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))))
: 0U)))) {
if ((((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)
>> 1U) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U]
<< 0x16U) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[1U]
>> 0xaU)))
== ((0xa7U >= (0xffU & ((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))
? (0xffU & (((0U == (0x1fU
& ((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))
? 0U : (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[
((IData)(1U)
+ (7U
& (((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))
>> 5U)))]
<< ((IData)(0x20U)
-
(0x1fU
& ((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))))
| (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[
(7U & (((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))
>> 5U))]
>> (0x1fU &
((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))))
: 0U)))) {
vlTOPp->core_rsp_valid = ((IData)(vlTOPp->core_rsp_valid)
| ((IData)(1U) <<
(3U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid)
>> 2U))));
}
if ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid)
& ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)
>> 2U)) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U]
<< 0xcU) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U]
>> 0x14U)))
== ((0xa7U >= (0xffU & ((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))
? (0xffU & (((0U == (0x1fU
& ((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))
? 0U : (
vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[
((IData)(1U)
+
(7U
& (((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))
>> 5U)))]
<<
((IData)(0x20U)
-
(0x1fU
& ((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))))
| (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[
(7U & (
((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))
>> 5U))]
>> (0x1fU
& ((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))))
: 0U)))) {
if ((((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)
>> 2U) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U]
<< 0xcU) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U]
>> 0x14U)))
== ((0xa7U >= (0xffU & ((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))
? (0xffU & (((0U == (0x1fU
& ((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))
? 0U : (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[
((IData)(1U)
+ (7U
& (((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))
>> 5U)))]
<< ((IData)(0x20U)
-
(0x1fU
& ((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))))
| (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[
(7U & (((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))
>> 5U))]
>> (0x1fU &
((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))))
: 0U)))) {
vlTOPp->core_rsp_valid = ((IData)(vlTOPp->core_rsp_valid)
| ((IData)(1U) <<
(3U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid)
>> 4U))));
}
if ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid)
& ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)
>> 3U)) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[4U]
<< 2U) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U]
>> 0x1eU)))
== ((0xa7U >= (0xffU & ((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))
? (0xffU & (((0U == (0x1fU
& ((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))
? 0U : (
vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[
((IData)(1U)
+
(7U
& (((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))
>> 5U)))]
<<
((IData)(0x20U)
-
(0x1fU
& ((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))))
| (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[
(7U & (
((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))
>> 5U))]
>> (0x1fU
& ((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))))
: 0U)))) {
if ((((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)
>> 3U) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[4U]
<< 2U) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U]
>> 0x1eU)))
== ((0xa7U >= (0xffU & ((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))
? (0xffU & (((0U == (0x1fU
& ((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))
? 0U : (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[
((IData)(1U)
+ (7U
& (((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))
>> 5U)))]
<< ((IData)(0x20U)
-
(0x1fU
& ((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))))
| (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[
(7U & (((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))
>> 5U))]
>> (0x1fU &
((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))))
: 0U)))) {
vlTOPp->core_rsp_valid = ((IData)(vlTOPp->core_rsp_valid)
| ((IData)(1U) <<
(3U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid)
@ -20214,8 +20162,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym
vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data[1U] = 0U;
vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data[2U] = 0U;
vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data[3U] = 0U;
if ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid)
& (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid))
if (((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)
& ((0xffU & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[0U])
== ((0xa7U >= (0xffU & ((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))
@ -20241,113 +20188,98 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym
<< 5U)), vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data,
vlTOPp->VX_cache__DOT__per_bank_core_rsp_data[0U]);
}
if ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid)
& ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)
>> 1U)) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U]
<< 0x16U) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[1U]
>> 0xaU)))
== ((0xa7U >= (0xffU & ((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))
? (0xffU & (((0U == (0x1fU
& ((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))
? 0U : (
vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[
((IData)(1U)
+
(7U
& (((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))
>> 5U)))]
<<
((IData)(0x20U)
-
(0x1fU
& ((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))))
| (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[
(7U & (
((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))
>> 5U))]
>> (0x1fU
& ((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))))
: 0U)))) {
if ((((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)
>> 1U) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U]
<< 0x16U) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[1U]
>> 0xaU)))
== ((0xa7U >= (0xffU & ((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))
? (0xffU & (((0U == (0x1fU
& ((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))
? 0U : (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[
((IData)(1U)
+ (7U
& (((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))
>> 5U)))]
<< ((IData)(0x20U)
-
(0x1fU
& ((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))))
| (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[
(7U & (((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))
>> 5U))]
>> (0x1fU &
((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))))
: 0U)))) {
VL_ASSIGNSEL_WIII(32,(0x60U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid)
<< 3U)), vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data,
vlTOPp->VX_cache__DOT__per_bank_core_rsp_data[1U]);
}
if ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid)
& ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)
>> 2U)) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U]
<< 0xcU) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U]
>> 0x14U)))
== ((0xa7U >= (0xffU & ((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))
? (0xffU & (((0U == (0x1fU
& ((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))
? 0U : (
vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[
((IData)(1U)
+
(7U
& (((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))
>> 5U)))]
<<
((IData)(0x20U)
-
(0x1fU
& ((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))))
| (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[
(7U & (
((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))
>> 5U))]
>> (0x1fU
& ((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))))
: 0U)))) {
if ((((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)
>> 2U) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U]
<< 0xcU) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U]
>> 0x14U)))
== ((0xa7U >= (0xffU & ((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))
? (0xffU & (((0U == (0x1fU
& ((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))
? 0U : (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[
((IData)(1U)
+ (7U
& (((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))
>> 5U)))]
<< ((IData)(0x20U)
-
(0x1fU
& ((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))))
| (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[
(7U & (((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))
>> 5U))]
>> (0x1fU &
((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))))
: 0U)))) {
VL_ASSIGNSEL_WIII(32,(0x60U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid)
<< 1U)), vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data,
vlTOPp->VX_cache__DOT__per_bank_core_rsp_data[2U]);
}
if ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid)
& ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)
>> 3U)) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[4U]
<< 2U) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U]
>> 0x1eU)))
== ((0xa7U >= (0xffU & ((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))
? (0xffU & (((0U == (0x1fU
& ((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))
? 0U : (
vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[
((IData)(1U)
+
(7U
& (((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))
>> 5U)))]
<<
((IData)(0x20U)
-
(0x1fU
& ((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))))
| (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[
(7U & (
((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))
>> 5U))]
>> (0x1fU
& ((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))))
: 0U)))) {
if ((((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)
>> 3U) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[4U]
<< 2U) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U]
>> 0x1eU)))
== ((0xa7U >= (0xffU & ((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))
? (0xffU & (((0U == (0x1fU
& ((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))
? 0U : (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[
((IData)(1U)
+ (7U
& (((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))
>> 5U)))]
<< ((IData)(0x20U)
-
(0x1fU
& ((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))))
| (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[
(7U & (((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))
>> 5U))]
>> (0x1fU &
((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))))
: 0U)))) {
VL_ASSIGNSEL_WIII(32,(0x60U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid)
>> 1U)), vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data,
vlTOPp->VX_cache__DOT__per_bank_core_rsp_data[3U]);
@ -20358,8 +20290,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym
| ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)));
vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual
= ((0xeU & (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual))
| (((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid)
& (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid))
| ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)
& ((0xffU & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[0U])
== ((0xa7U >= (0xffU & ((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))
@ -20385,8 +20316,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym
: 0U))));
vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual
= ((0xdU & (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual))
| (0xfffffffeU & ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid)
<< 1U) & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid))
| (0xfffffffeU & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)
& (((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U]
<< 0x16U)
| (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[1U]
@ -20427,8 +20357,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym
: 0U)) << 1U))));
vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual
= ((0xbU & (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual))
| (0xfffffffcU & ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid)
<< 2U) & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid))
| (0xfffffffcU & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)
& (((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U]
<< 0xcU)
| (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U]
@ -20469,8 +20398,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym
: 0U)) << 2U))));
vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual
= ((7U & (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual))
| (0xfffffff8U & ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid)
<< 3U) & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid))
| (0xfffffff8U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)
& (((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[4U]
<< 2U)
| (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U]
@ -27083,9 +27011,9 @@ void VVX_cache::_ctor_var_reset() {
VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i = VL_RAND_RESET_I(32);
VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__grant_onehot_r = VL_RAND_RESET_I(4);
VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i = VL_RAND_RESET_I(32);
VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual = VL_RAND_RESET_I(4);
VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index = VL_RAND_RESET_I(2);
VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid = VL_RAND_RESET_I(1);
VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual = VL_RAND_RESET_I(4);
VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__grant_valid = VL_RAND_RESET_I(1);
VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__requests_use = VL_RAND_RESET_I(4);
VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__update_value = VL_RAND_RESET_I(4);
VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__refill = VL_RAND_RESET_I(1);
@ -28079,22 +28007,22 @@ void VVX_cache::_ctor_var_reset() {
__Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[13] = 0U;
__Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[14] = 1U;
__Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[15] = 0U;
__Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[0] = 0U;
__Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[1] = 1U;
__Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[2] = 1U;
__Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[3] = 1U;
__Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[4] = 1U;
__Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[5] = 1U;
__Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[6] = 1U;
__Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[7] = 1U;
__Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[8] = 1U;
__Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[9] = 1U;
__Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[10] = 1U;
__Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[11] = 1U;
__Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[12] = 1U;
__Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[13] = 1U;
__Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[14] = 1U;
__Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[15] = 1U;
__Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__grant_valid[0] = 0U;
__Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__grant_valid[1] = 1U;
__Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__grant_valid[2] = 1U;
__Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__grant_valid[3] = 1U;
__Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__grant_valid[4] = 1U;
__Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__grant_valid[5] = 1U;
__Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__grant_valid[6] = 1U;
__Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__grant_valid[7] = 1U;
__Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__grant_valid[8] = 1U;
__Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__grant_valid[9] = 1U;
__Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__grant_valid[10] = 1U;
__Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__grant_valid[11] = 1U;
__Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__grant_valid[12] = 1U;
__Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__grant_valid[13] = 1U;
__Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__grant_valid[14] = 1U;
__Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__grant_valid[15] = 1U;
__Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[0] = 0xffffffffU;
__Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[1] = 0xffffffffU;
__Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[2] = 0xffffffffU;

6
hw/unit_tests/cache/obj_dir/VVX_cache.h vendored
View file

@ -117,9 +117,9 @@ VL_MODULE(VVX_cache) {
CData/*0:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r;
CData/*3:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r;
CData/*3:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__grant_onehot_r;
CData/*3:0*/ VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual;
CData/*1:0*/ VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index;
CData/*0:0*/ VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid;
CData/*3:0*/ VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual;
CData/*0:0*/ VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__grant_valid;
CData/*3:0*/ VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__requests_use;
CData/*3:0*/ VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__update_value;
CData/*0:0*/ VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__refill;
@ -864,7 +864,7 @@ VL_MODULE(VVX_cache) {
static CData/*0:0*/ __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[16];
static IData/*31:0*/ __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[16];
static CData/*1:0*/ __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[16];
static CData/*0:0*/ __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[16];
static CData/*0:0*/ __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__grant_valid[16];
static IData/*31:0*/ __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[16];
static CData/*1:0*/ __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[16];
static CData/*0:0*/ __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[16];

BIN
hw/unit_tests/cache/obj_dir/VVX_cache__ALL.a vendored
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BIN
hw/unit_tests/cache/obj_dir/VVX_cache__ALLcls.o vendored
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BIN
hw/unit_tests/cache/obj_dir/VVX_cache__ALLsup.o vendored
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8
hw/unit_tests/cache/obj_dir/VVX_cache__Trace.cpp vendored
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@ -564,10 +564,10 @@ void VVX_cache::traceChgThis__4(VVX_cache__Syms* __restrict vlSymsp, VerilatedVc
& ((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))))
: VL_ULL(0))),42);
vcdp->chgBus(c+2265,(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual),4);
vcdp->chgBus(c+2273,(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index),2);
vcdp->chgBit(c+2281,(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid));
vcdp->chgBus(c+2289,(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r),4);
vcdp->chgBus(c+2265,(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index),2);
vcdp->chgBus(c+2273,(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual),4);
vcdp->chgBus(c+2281,(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r),4);
vcdp->chgBit(c+2289,(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__grant_valid));
vcdp->chgBus(c+2297,((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__requests_use)
& (~ (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r)))
| (((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__refill_original)

25
hw/unit_tests/cache/obj_dir/VVX_cache__Trace__Slow.cpp vendored
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@ -490,28 +490,27 @@ void VVX_cache::traceInitThis__1(VVX_cache__Syms* __restrict vlSymsp, VerilatedV
vcdp->declArray(c+2217,"VX_cache cache_core_rsp_merge core_rsp_data", false,-1, 127,0);
vcdp->declQuad(c+2249,"VX_cache cache_core_rsp_merge core_rsp_tag", false,-1, 41,0);
vcdp->declBit(c+24673,"VX_cache cache_core_rsp_merge core_rsp_ready", false,-1);
vcdp->declBus(c+2265,"VX_cache cache_core_rsp_merge per_bank_core_rsp_pop_unqual", false,-1, 3,0);
vcdp->declBus(c+2273,"VX_cache cache_core_rsp_merge main_bank_index", false,-1, 1,0);
vcdp->declBit(c+2281,"VX_cache cache_core_rsp_merge grant_valid", false,-1);
vcdp->declBus(c+2265,"VX_cache cache_core_rsp_merge main_bank_index", false,-1, 1,0);
vcdp->declBus(c+2273,"VX_cache cache_core_rsp_merge per_bank_core_rsp_pop_unqual", false,-1, 3,0);
vcdp->declBus(c+25129,"VX_cache cache_core_rsp_merge i", false,-1, 31,0);
vcdp->declBus(c+25081,"VX_cache cache_core_rsp_merge sel_bank N", false,-1, 31,0);
vcdp->declBit(c+24489,"VX_cache cache_core_rsp_merge sel_bank clk", false,-1);
vcdp->declBit(c+24497,"VX_cache cache_core_rsp_merge sel_bank reset", false,-1);
vcdp->declBus(c+1097,"VX_cache cache_core_rsp_merge sel_bank requests", false,-1, 3,0);
vcdp->declBus(c+2273,"VX_cache cache_core_rsp_merge sel_bank grant_index", false,-1, 1,0);
vcdp->declBus(c+2289,"VX_cache cache_core_rsp_merge sel_bank grant_onehot", false,-1, 3,0);
vcdp->declBit(c+2281,"VX_cache cache_core_rsp_merge sel_bank grant_valid", false,-1);
vcdp->declBus(c+2265,"VX_cache cache_core_rsp_merge sel_bank grant_index", false,-1, 1,0);
vcdp->declBus(c+2281,"VX_cache cache_core_rsp_merge sel_bank grant_onehot", false,-1, 3,0);
vcdp->declBit(c+2289,"VX_cache cache_core_rsp_merge sel_bank grant_valid", false,-1);
vcdp->declBus(c+10577,"VX_cache cache_core_rsp_merge sel_bank genblk2 requests_use", false,-1, 3,0);
vcdp->declBus(c+2297,"VX_cache cache_core_rsp_merge sel_bank genblk2 update_value", false,-1, 3,0);
vcdp->declBus(c+2305,"VX_cache cache_core_rsp_merge sel_bank genblk2 late_value", false,-1, 3,0);
vcdp->declBit(c+10585,"VX_cache cache_core_rsp_merge sel_bank genblk2 refill", false,-1);
vcdp->declBus(c+1097,"VX_cache cache_core_rsp_merge sel_bank genblk2 refill_value", false,-1, 3,0);
vcdp->declBus(c+10593,"VX_cache cache_core_rsp_merge sel_bank genblk2 refill_original", false,-1, 3,0);
vcdp->declBus(c+2289,"VX_cache cache_core_rsp_merge sel_bank genblk2 grant_onehot_r", false,-1, 3,0);
vcdp->declBus(c+2281,"VX_cache cache_core_rsp_merge sel_bank genblk2 grant_onehot_r", false,-1, 3,0);
vcdp->declBus(c+25081,"VX_cache cache_core_rsp_merge sel_bank genblk2 priority_encoder N", false,-1, 31,0);
vcdp->declBus(c+10577,"VX_cache cache_core_rsp_merge sel_bank genblk2 priority_encoder data_in", false,-1, 3,0);
vcdp->declBus(c+2273,"VX_cache cache_core_rsp_merge sel_bank genblk2 priority_encoder data_out", false,-1, 1,0);
vcdp->declBit(c+2281,"VX_cache cache_core_rsp_merge sel_bank genblk2 priority_encoder valid_out", false,-1);
vcdp->declBus(c+2265,"VX_cache cache_core_rsp_merge sel_bank genblk2 priority_encoder data_out", false,-1, 1,0);
vcdp->declBit(c+2289,"VX_cache cache_core_rsp_merge sel_bank genblk2 priority_encoder valid_out", false,-1);
vcdp->declBus(c+2313,"VX_cache cache_core_rsp_merge sel_bank genblk2 priority_encoder i", false,-1, 31,0);
vcdp->declBus(c+25081,"VX_cache snp_rsp_arb NUM_BANKS", false,-1, 31,0);
vcdp->declBus(c+25073,"VX_cache snp_rsp_arb BANK_LINE_SIZE", false,-1, 31,0);
@ -3414,10 +3413,10 @@ void VVX_cache::traceFullThis__1(VVX_cache__Syms* __restrict vlSymsp, VerilatedV
& ((IData)(0x2aU)
* (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))))
: VL_ULL(0))),42);
vcdp->fullBus(c+2265,(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual),4);
vcdp->fullBus(c+2273,(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index),2);
vcdp->fullBit(c+2281,(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid));
vcdp->fullBus(c+2289,(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r),4);
vcdp->fullBus(c+2265,(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index),2);
vcdp->fullBus(c+2273,(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual),4);
vcdp->fullBus(c+2281,(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r),4);
vcdp->fullBit(c+2289,(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__grant_valid));
vcdp->fullBus(c+2297,((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__requests_use)
& (~ (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r)))
| (((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__refill_original)

42
hw/unit_tests/cache/obj_dir/VVX_cache__verFiles.dat vendored
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@ -1,7 +1,7 @@
# DESCRIPTION: Verilator output: Timestamp data for --skip-identical. Delete at will.
C "--language 1800-2009 --assert -Wall --trace -Wno-DECLFILENAME --x-initial unique -exe cachesim.cpp testbench.cpp -I../../rtl/ -I../../rtl/cache -I../../rtl/libs -DNDEBUG -cc VX_cache.v -DCACHE_SIZE=4096 -DWORD_SIZE=4 -DBANK_LINE_SIZE=16 -DNUM_BANKS=4 -DCREQ_SIZE=4 -DMRVQ_SIZE=16 -DDFPQ_SIZE=16 -DSNRQ_SIZE=16 -DCWBQ_SIZE=4 -DDWBQ_SIZE=4 -DFQQ_SIZE=4 -CFLAGS -std=c++11 -fms-extensions -I../.. -DNDEBUG -DCACHE_SIZE=4096 -DWORD_SIZE=4 -DBANK_LINE_SIZE=16 -DNUM_BANKS=4 -DCREQ_SIZE=4 -DMRVQ_SIZE=16 -DDFPQ_SIZE=16 -DSNRQ_SIZE=16 -DCWBQ_SIZE=4 -DDWBQ_SIZE=4 -DFQQ_SIZE=4 --exe cachesim.cpp testbench.cpp"
S 6992 4983715 1593571269 845187304 1593571269 845187304 "../../rtl//VX_config.vh"
S 8927 4983721 1593571269 845187304 1593571269 845187304 "../../rtl//VX_define.vh"
S 7349 4983714 1594698569 774801969 1594698569 774801969 "../../rtl//VX_config.vh"
S 9046 4983721 1594698569 778802144 1594698569 778802144 "../../rtl//VX_define.vh"
S 16028 4983736 1593571269 849188141 1593571269 849188141 "../../rtl//VX_scope.vh"
S 147 4980795 1592347024 921834494 1592347024 921834494 "../../rtl//VX_user_config.vh"
S 34555 4983741 1593571269 849188141 1593571269 849188141 "../../rtl/cache/VX_bank.v"
@ -9,29 +9,29 @@ S 6128 4983742 1593571269 849188141 1593571269 849188141 "../../rtl/
S 22942 4985366 1594500482 317211549 1594500482 317211549 "../../rtl/cache/VX_cache.v"
S 2842 4983744 1593571269 849188141 1593571269 849188141 "../../rtl/cache/VX_cache_config.vh"
S 1745 4983745 1593571269 849188141 1593571269 849188141 "../../rtl/cache/VX_cache_core_req_bank_sel.v"
S 3719 4983746 1593571269 849188141 1593571269 849188141 "../../rtl/cache/VX_cache_core_rsp_merge.v"
S 3649 4983746 1594698569 778802144 1594698569 778802144 "../../rtl/cache/VX_cache_core_rsp_merge.v"
S 3602 4983747 1593571269 849188141 1593571269 849188141 "../../rtl/cache/VX_cache_dram_fill_arb.v"
S 4396 4985343 1593571951 15994059 1593571951 7993214 "../../rtl/cache/VX_cache_dram_req_arb.v"
S 7305 4983749 1593571269 849188141 1593571269 849188141 "../../rtl/cache/VX_cache_miss_resrv.v"
S 7304 4983749 1594698569 778802144 1594698569 778802144 "../../rtl/cache/VX_cache_miss_resrv.v"
S 1996 4983748 1593571988 408039126 1593571988 396037801 "../../rtl/cache/VX_prefetcher.v"
S 5064 4983751 1593571269 849188141 1593571269 849188141 "../../rtl/cache/VX_snp_forwarder.v"
S 5067 4983751 1594698569 778802144 1594698569 778802144 "../../rtl/cache/VX_snp_forwarder.v"
S 1210 4983752 1593571269 849188141 1593571269 849188141 "../../rtl/cache/VX_snp_rsp_arb.v"
S 8840 4983753 1593571269 849188141 1593571269 849188141 "../../rtl/cache/VX_tag_data_access.v"
S 3211 4983754 1593571269 849188141 1593571269 849188141 "../../rtl/cache/VX_tag_data_structure.v"
S 1865 4983777 1593571269 849188141 1593571269 849188141 "../../rtl/libs/VX_fair_arbiter.v"
S 1022 4983778 1593571269 849188141 1593571269 849188141 "../../rtl/libs/VX_fixed_arbiter.v"
S 5974 4983779 1593571269 849188141 1593571269 849188141 "../../rtl/libs/VX_generic_queue.v"
S 582 4983780 1593571269 849188141 1593571269 849188141 "../../rtl/libs/VX_generic_register.v"
S 1552 4983782 1593571269 849188141 1593571269 849188141 "../../rtl/libs/VX_indexable_queue.v"
S 491 4983785 1593571269 849188141 1593571269 849188141 "../../rtl/libs/VX_priority_encoder.v"
S 1861 4983777 1594698569 778802144 1594698569 778802144 "../../rtl/libs/VX_fair_arbiter.v"
S 1022 4983778 1594698569 778802144 1594698569 778802144 "../../rtl/libs/VX_fixed_arbiter.v"
S 5977 4983779 1594698569 778802144 1594698569 778802144 "../../rtl/libs/VX_generic_queue.v"
S 586 4983780 1594698569 778802144 1594698569 778802144 "../../rtl/libs/VX_generic_register.v"
S 1560 4983782 1594698569 778802144 1594698569 778802144 "../../rtl/libs/VX_indexable_queue.v"
S 495 4983785 1594698569 778802144 1594698569 778802144 "../../rtl/libs/VX_priority_encoder.v"
S 8183216 2503059 1591812755 756668753 1591812755 756668753 "/usr/local/bin/verilator_bin"
T 3001929 4983824 1594500491 517601979 1594500491 517601979 "obj_dir/VVX_cache.cpp"
T 93468 4983825 1594500491 473600112 1594500491 473600112 "obj_dir/VVX_cache.h"
T 2104 4983826 1594500491 517601979 1594500491 517601979 "obj_dir/VVX_cache.mk"
T 8694 4983827 1594500491 449599094 1594500491 449599094 "obj_dir/VVX_cache__Syms.cpp"
T 4866 4983828 1594500491 449599094 1594500491 449599094 "obj_dir/VVX_cache__Syms.h"
T 429460 4983829 1594500491 469599943 1594500491 469599943 "obj_dir/VVX_cache__Trace.cpp"
T 700979 4983830 1594500491 461599603 1594500491 461599603 "obj_dir/VVX_cache__Trace__Slow.cpp"
T 1118 4980960 1594500491 517601979 1594500491 517601979 "obj_dir/VVX_cache__ver.d"
T 0 0 1594500491 517601979 1594500491 517601979 "obj_dir/VVX_cache__verFiles.dat"
T 1315 4983831 1594500491 517601979 1594500491 517601979 "obj_dir/VVX_cache_classes.mk"
T 2996411 4983824 1594698591 263742640 1594698591 263742640 "obj_dir/VVX_cache.cpp"
T 93498 4983825 1594698591 211740363 1594698591 211740363 "obj_dir/VVX_cache.h"
T 2104 4983826 1594698591 263742640 1594698591 263742640 "obj_dir/VVX_cache.mk"
T 8694 4983827 1594698591 179738962 1594698591 179738962 "obj_dir/VVX_cache__Syms.cpp"
T 4866 4983828 1594698591 179738962 1594698591 179738962 "obj_dir/VVX_cache__Syms.h"
T 429475 4983829 1594698591 207740187 1594698591 207740187 "obj_dir/VVX_cache__Trace.cpp"
T 700909 4983830 1594698591 195739663 1594698591 195739663 "obj_dir/VVX_cache__Trace__Slow.cpp"
T 1118 4980960 1594698591 263742640 1594698591 263742640 "obj_dir/VVX_cache__ver.d"
T 0 0 1594698591 263742640 1594698591 263742640 "obj_dir/VVX_cache__verFiles.dat"
T 1315 4983831 1594698591 263742640 1594698591 263742640 "obj_dir/VVX_cache_classes.mk"

6515
hw/unit_tests/cache/trace.vcd vendored
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