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Merge remote-tracking branch 'origin/master' into graphics

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This commit is contained in:
Blaise Tine 2021-03-15 18:23:28 -04:00
commit 17424ad554
1 changed files with 5 additions and 6 deletions
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11
hw/rtl/VX_writeback.v
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@ -88,12 +88,11 @@ module VX_writeback #(
.data_out ({writeback_if.valid, writeback_if.wid, writeback_if.PC, writeback_if.tmask, writeback_if.rd, writeback_if.data, writeback_if.eop})
);
assign ld_commit_if.ready = !stall;
assign fpu_commit_if.ready = !stall && !ld_valid;
assign csr_commit_if.ready = !stall && !ld_valid && !fpu_valid;
assign alu_commit_if.ready = !stall && !ld_valid && !fpu_valid && !csr_valid;
// if not TEX instruction, no writeback and commit is ready
assign gpu_commit_if.ready = (!stall && !ld_valid && !fpu_valid && !csr_valid && !alu_valid) || !gpu_commit_if.wb ;
assign ld_commit_if.ready = !(ld_commit_if.wb && (stall));
assign fpu_commit_if.ready = !(fpu_commit_if.wb && (stall || ld_valid));
assign csr_commit_if.ready = !(csr_commit_if.wb && (stall || ld_valid || fpu_valid));
assign alu_commit_if.ready = !(alu_commit_if.wb && (stall || ld_valid || fpu_valid || csr_valid));
assign gpu_commit_if.ready = !(gpu_commit_if.wb && (stall || ld_valid || fpu_valid || csr_valid || alu_valid));
// special workaround to get RISC-V tests Pass/Fail status
reg [31:0] last_wb_value [`NUM_REGS-1:0] /* verilator public */;