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https://github.com/vortexgpgpu/vortex.git
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minor update
This commit is contained in:
Blaise Tine
parent
9797c6c48a
commit
177f0efc59
2 changed files with 48 additions and 46 deletions
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@ -59,18 +59,17 @@ module VX_operands import VX_gpu_pkg::*; #(
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wire [NUM_SRC_OPDS-1:0][BANK_SEL_WIDTH-1:0] req_bank_idx;
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wire [NUM_BANKS-1:0] gpr_rd_valid, gpr_rd_ready;
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wire [NUM_BANKS-1:0] gpr_rd_valid_st1;
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wire [NUM_BANKS-1:0] gpr_rd_valid_st1, gpr_rd_valid_st2;
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wire [NUM_BANKS-1:0][PER_BANK_ADDRW-1:0] gpr_rd_addr, gpr_rd_addr_st1;
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wire [NUM_BANKS-1:0][`NUM_THREADS-1:0][`XLEN-1:0] gpr_rd_data;
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wire [NUM_BANKS-1:0][REQ_SEL_WIDTH-1:0] gpr_rd_req_idx, gpr_rd_req_idx_st1;
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wire [NUM_BANKS-1:0][`NUM_THREADS-1:0][`XLEN-1:0] gpr_rd_data_st2;
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wire [NUM_BANKS-1:0][REQ_SEL_WIDTH-1:0] gpr_rd_req_idx, gpr_rd_req_idx_st1, gpr_rd_req_idx_st2;
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wire pipe_valid_st1, pipe_ready_st1;
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wire pipe_valid_st1, pipe_ready_st1, pipe_in_ready;
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wire pipe_valid_st2, pipe_ready_st2;
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wire [META_DATAW-1:0] pipe_data, pipe_data_st1, pipe_data_st2;
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reg [NUM_SRC_OPDS-1:0][`NUM_THREADS-1:0][`XLEN-1:0] gpr_rd_data_st1;
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wire [NUM_SRC_OPDS-1:0][`NUM_THREADS-1:0][`XLEN-1:0] gpr_rd_data_st2;
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wire [NUM_SRC_OPDS-1:0][`NUM_THREADS-1:0][`XLEN-1:0] src_data_st1, src_data_st2, src_data_m_st2;
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reg [NUM_SRC_OPDS-1:0][`NUM_THREADS-1:0][`XLEN-1:0] src_data_m_st2;
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wire [NUM_SRC_OPDS-1:0][`NUM_THREADS-1:0][`XLEN-1:0] src_data_st1, src_data_st2;
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reg [NUM_SRC_OPDS-1:0] data_fetched_n;
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wire [NUM_SRC_OPDS-1:0] data_fetched_st1;
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@ -123,15 +122,8 @@ module VX_operands import VX_gpu_pkg::*; #(
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.ready_out (gpr_rd_ready)
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);
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wire pipe_in_ready = pipe_ready_st1 || ~pipe_valid_st1;
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assign gpr_rd_ready = {NUM_BANKS{pipe_in_ready}};
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assign scoreboard_if.ready = pipe_in_ready && ~has_collision_n;
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wire pipe_fire_st1 = pipe_valid_st1 && pipe_ready_st1;
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wire pipe_fire_st2 = pipe_valid_st2 && pipe_ready_st2;
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always @(*) begin
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has_collision_n = 0;
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for (integer i = 0; i < NUM_SRC_OPDS; ++i) begin
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@ -164,47 +156,54 @@ module VX_operands import VX_gpu_pkg::*; #(
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scoreboard_if.data.uuid
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};
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VX_pipe_register #(
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.DATAW (1 + NUM_SRC_OPDS + NUM_BANKS + META_DATAW + 1 + NUM_BANKS * (PER_BANK_ADDRW + REQ_SEL_WIDTH)),
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.RESETW (1 + NUM_SRC_OPDS)
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assign scoreboard_if.ready = pipe_in_ready && ~has_collision_n;
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wire pipe_fire_st1 = pipe_valid_st1 && pipe_ready_st1;
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wire pipe_fire_st2 = pipe_valid_st2 && pipe_ready_st2;
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VX_pipe_buffer #(
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.DATAW (NUM_SRC_OPDS + NUM_BANKS + META_DATAW + 1 + NUM_BANKS * (PER_BANK_ADDRW + REQ_SEL_WIDTH)),
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.RESETW (NUM_SRC_OPDS)
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) pipe_reg1 (
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.clk (clk),
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.reset (reset),
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.enable (pipe_in_ready),
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.data_in ({scoreboard_if.valid, data_fetched_n, gpr_rd_valid, pipe_data, has_collision_n, gpr_rd_addr, gpr_rd_req_idx}),
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.data_out ({pipe_valid_st1, data_fetched_st1, gpr_rd_valid_st1, pipe_data_st1, has_collision_st1, gpr_rd_addr_st1, gpr_rd_req_idx_st1})
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.valid_in (scoreboard_if.valid),
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.ready_in (pipe_in_ready),
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.data_in ({data_fetched_n, gpr_rd_valid, pipe_data, has_collision_n, gpr_rd_addr, gpr_rd_req_idx}),
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.data_out ({data_fetched_st1, gpr_rd_valid_st1, pipe_data_st1, has_collision_st1, gpr_rd_addr_st1, gpr_rd_req_idx_st1}),
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.valid_out(pipe_valid_st1),
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.ready_out(pipe_ready_st1)
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);
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assign pipe_ready_st1 = pipe_ready_st2 || ~pipe_valid_st2;
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always @(*) begin
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gpr_rd_data_st1 = '0;
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for (integer b = 0; b < NUM_BANKS; ++b) begin
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if (gpr_rd_valid_st1[b]) begin
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gpr_rd_data_st1[gpr_rd_req_idx_st1[b]] = gpr_rd_data[b];
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end
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end
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end
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assign src_data_m_st2 = src_data_st2 | gpr_rd_data_st2;
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assign src_data_st1 = pipe_fire_st2 ? '0 : src_data_m_st2;
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wire pipe_valid2_st1 = pipe_valid_st1 && ~has_collision_st1;
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`RESET_RELAY (pipe2_reset, reset); // needed for pipe_reg2's wide RESETW
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VX_pipe_register #(
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.DATAW (1 + NUM_SRC_OPDS * REGS_DATAW + NUM_SRC_OPDS * REGS_DATAW + META_DATAW),
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.RESETW (1 + NUM_SRC_OPDS * REGS_DATAW)
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VX_pipe_buffer #(
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.DATAW (NUM_SRC_OPDS * REGS_DATAW + NUM_BANKS + META_DATAW + NUM_BANKS * REQ_SEL_WIDTH),
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.RESETW (NUM_SRC_OPDS * REGS_DATAW)
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) pipe_reg2 (
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.clk (clk),
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.reset (pipe2_reset),
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.enable (pipe_ready_st1),
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.data_in ({pipe_valid2_st1, src_data_st1, gpr_rd_data_st1, pipe_data_st1}),
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.data_out ({pipe_valid_st2, src_data_st2, gpr_rd_data_st2, pipe_data_st2})
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.valid_in (pipe_valid2_st1),
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.ready_in (pipe_ready_st1),
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.data_in ({src_data_st1, gpr_rd_valid_st1, pipe_data_st1, gpr_rd_req_idx_st1}),
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.data_out ({src_data_st2, gpr_rd_valid_st2, pipe_data_st2, gpr_rd_req_idx_st2}),
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.valid_out(pipe_valid_st2),
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.ready_out(pipe_ready_st2)
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);
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always @(*) begin
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src_data_m_st2 = src_data_st2;
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for (integer b = 0; b < NUM_BANKS; ++b) begin
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if (gpr_rd_valid_st2[b]) begin
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src_data_m_st2[gpr_rd_req_idx_st2[b]] = gpr_rd_data_st2[b];
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end
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end
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end
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VX_elastic_buffer #(
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.DATAW (DATAW),
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.SIZE (`TO_OUT_BUF_SIZE(OUT_BUF)),
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@ -264,6 +263,8 @@ module VX_operands import VX_gpu_pkg::*; #(
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VX_dp_ram #(
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.DATAW (REGS_DATAW),
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.SIZE (PER_BANK_REGS * PER_ISSUE_WARPS),
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.READ_ENABLE (1),
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.OUT_REG (1),
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.WRENW (BYTEENW),
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`ifdef GPR_RESET
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.RESET_RAM (1),
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@ -278,7 +279,7 @@ module VX_operands import VX_gpu_pkg::*; #(
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.waddr (gpr_wr_addr),
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.wdata (writeback_if.data.data),
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.raddr (gpr_rd_addr_st1[b]),
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.rdata (gpr_rd_data[b])
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.rdata (gpr_rd_data_st2[b])
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);
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end
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@ -163,12 +163,13 @@ module VX_local_mem import VX_gpu_pkg::*; #(
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for (genvar i = 0; i < NUM_BANKS; ++i) begin
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wire bank_rsp_valid, bank_rsp_ready;
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wire [WORD_WIDTH-1:0] bank_rsp_data;
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VX_sp_ram #(
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.DATAW (WORD_WIDTH),
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.SIZE (WORDS_PER_BANK),
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.WRENW (WORD_SIZE),
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.READ_ENABLE (1),
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.OUT_REG (1),
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.NO_RWCHECK (1)
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) data_store (
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.clk (clk),
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@ -178,7 +179,7 @@ module VX_local_mem import VX_gpu_pkg::*; #(
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.wren (per_bank_req_byteen[i]),
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.addr (per_bank_req_addr[i]),
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.wdata (per_bank_req_data[i]),
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.rdata (bank_rsp_data)
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.rdata (per_bank_rsp_data[i])
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);
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// read-during-write hazard detection
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@ -194,20 +195,20 @@ module VX_local_mem import VX_gpu_pkg::*; #(
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end
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wire is_rdw_hazard = last_wr_valid && ~per_bank_req_rw[i] && (per_bank_req_addr[i] == last_wr_addr);
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// drop write response and stall on read-during-write hazard
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// drop write response
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assign bank_rsp_valid = per_bank_req_valid[i] && ~per_bank_req_rw[i] && ~is_rdw_hazard;
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assign per_bank_req_ready[i] = (bank_rsp_ready || per_bank_req_rw[i]) && ~is_rdw_hazard;
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// register BRAM output
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VX_pipe_buffer #(
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.DATAW (REQ_SEL_WIDTH + WORD_WIDTH + TAG_WIDTH)
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.DATAW (REQ_SEL_WIDTH + TAG_WIDTH)
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) bram_buf (
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.clk (clk),
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.reset (reset),
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.valid_in (bank_rsp_valid),
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.ready_in (bank_rsp_ready),
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.data_in ({per_bank_req_idx[i], bank_rsp_data, per_bank_req_tag[i]}),
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.data_out ({per_bank_rsp_idx[i], per_bank_rsp_data[i], per_bank_rsp_tag[i]}),
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.data_in ({per_bank_req_idx[i], per_bank_req_tag[i]}),
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.data_out ({per_bank_rsp_idx[i], per_bank_rsp_tag[i]}),
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.valid_out (per_bank_rsp_valid[i]),
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.ready_out (per_bank_rsp_ready[i])
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);
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