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fifoqueue area optimization

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This commit is contained in:
tinebp 2024-11-21 16:47:00 -08:00
parent 8d8769c710
commit 180735c531
1 changed files with 4 additions and 8 deletions
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12
hw/rtl/libs/VX_fifo_queue.sv
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@ -90,9 +90,6 @@ module VX_fifo_queue #(
end
end
wire going_empty = (ALM_EMPTY == 1) ? alm_empty : (size[ADDRW-1:0] == ADDRW'(1));
wire bypass = push && (empty || (going_empty && pop));
VX_dp_ram #(
.DATAW (DATAW),
.SIZE (DEPTH),
@ -101,7 +98,7 @@ module VX_fifo_queue #(
) dp_ram (
.clk (clk),
.reset (reset),
.read (~bypass),
.read (1'b1),
.write (push),
.wren (1'b1),
.raddr (rd_ptr_r),
@ -112,11 +109,10 @@ module VX_fifo_queue #(
if (OUT_REG != 0) begin : g_out_reg
reg [DATAW-1:0] data_out_r;
wire going_empty = (ALM_EMPTY == 1) ? alm_empty : (size[ADDRW-1:0] == ADDRW'(1));
always @(posedge clk) begin
if (bypass) begin
data_out_r <= data_in;
end else if (pop) begin
data_out_r <= data_out_w;
if (pop || (push && empty)) begin
data_out_r <= (empty || going_empty) ? data_in : data_out_w;
end
end
assign data_out = data_out_r;