mirror of
https://github.com/vortexgpgpu/vortex.git
synced 2025-04-23 21:39:10 -04:00
fixed interface modports
This commit is contained in:
Blaise Tine
parent
132260d84c
commit
18c1dc2f0e
7 changed files with 86 additions and 46 deletions
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@ -3,9 +3,6 @@
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# exit when any command fails
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set -e
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# build sources
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make -s
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coverage()
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{
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echo "begin coverage tests..."
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@ -24,11 +24,51 @@ module VX_issue #(
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VX_gpu_req_if.master gpu_req_if
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);
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VX_ibuffer_if ibuffer_if();
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VX_ibuffer_if execute_if();
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VX_gpr_req_if gpr_req_if();
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VX_gpr_rsp_if gpr_rsp_if();
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wire scoreboard_delay;
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VX_gpr_req_if gpr_req_if();
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assign gpr_req_if.wid = ibuffer_if.wid;
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assign gpr_req_if.rs1 = ibuffer_if.rs1;
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assign gpr_req_if.rs2 = ibuffer_if.rs2;
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assign gpr_req_if.rs3 = ibuffer_if.rs3;
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VX_writeback_if sboard_wb_if();
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assign sboard_wb_if.valid = writeback_if.valid;
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assign sboard_wb_if.wid = writeback_if.wid;
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assign sboard_wb_if.PC = writeback_if.PC;
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assign sboard_wb_if.rd = writeback_if.rd;
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assign sboard_wb_if.eop = writeback_if.eop;
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assign sboard_wb_if.ready = writeback_if.ready;
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VX_ibuffer_if sboard_ib_if();
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assign sboard_ib_if.valid = ibuffer_if.valid && idmux_ib_if.ready;
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assign sboard_ib_if.wid = ibuffer_if.wid;
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assign sboard_ib_if.PC = ibuffer_if.PC;
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assign sboard_ib_if.wb = ibuffer_if.wb;
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assign sboard_ib_if.rd = ibuffer_if.rd;
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assign sboard_ib_if.rd_n = ibuffer_if.rd_n;
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assign sboard_ib_if.rs1_n = ibuffer_if.rs1_n;
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assign sboard_ib_if.rs2_n = ibuffer_if.rs2_n;
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assign sboard_ib_if.rs3_n = ibuffer_if.rs3_n;
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assign sboard_ib_if.wid_n = ibuffer_if.wid_n;
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VX_ibuffer_if idmux_ib_if();
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assign idmux_ib_if.valid = ibuffer_if.valid && sboard_ib_if.ready;
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assign idmux_ib_if.wid = ibuffer_if.wid;
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assign idmux_ib_if.tmask = ibuffer_if.tmask;
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assign idmux_ib_if.PC = ibuffer_if.PC;
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assign idmux_ib_if.ex_type = ibuffer_if.ex_type;
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assign idmux_ib_if.op_type = ibuffer_if.op_type;
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assign idmux_ib_if.op_mod = ibuffer_if.op_mod;
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assign idmux_ib_if.wb = ibuffer_if.wb;
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assign idmux_ib_if.rd = ibuffer_if.rd;
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assign idmux_ib_if.rs1 = ibuffer_if.rs1;
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assign idmux_ib_if.imm = ibuffer_if.imm;
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assign idmux_ib_if.use_PC = ibuffer_if.use_PC;
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assign idmux_ib_if.use_imm = ibuffer_if.use_imm;
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// issue the instruction
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assign ibuffer_if.ready = sboard_ib_if.ready && idmux_ib_if.ready;
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`RESET_RELAY (ibuf_reset);
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`RESET_RELAY (gpr_reset);
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@ -48,15 +88,9 @@ module VX_issue #(
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) scoreboard (
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.clk (clk),
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.reset (reset),
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.ibuffer_if (ibuffer_if),
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.writeback_if(writeback_if),
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.delay (scoreboard_delay)
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.ibuffer_if (sboard_ib_if),
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.writeback_if(sboard_wb_if)
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);
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assign gpr_req_if.wid = ibuffer_if.wid;
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assign gpr_req_if.rs1 = ibuffer_if.rs1;
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assign gpr_req_if.rs2 = ibuffer_if.rs2;
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assign gpr_req_if.rs3 = ibuffer_if.rs3;
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VX_gpr_stage #(
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.CORE_ID(CORE_ID)
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@ -68,24 +102,10 @@ module VX_issue #(
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.gpr_rsp_if (gpr_rsp_if)
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);
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assign execute_if.valid = ibuffer_if.valid && ~scoreboard_delay;
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assign execute_if.wid = ibuffer_if.wid;
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assign execute_if.tmask = ibuffer_if.tmask;
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assign execute_if.PC = ibuffer_if.PC;
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assign execute_if.ex_type = ibuffer_if.ex_type;
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assign execute_if.op_type = ibuffer_if.op_type;
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assign execute_if.op_mod = ibuffer_if.op_mod;
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assign execute_if.wb = ibuffer_if.wb;
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assign execute_if.rd = ibuffer_if.rd;
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assign execute_if.rs1 = ibuffer_if.rs1;
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assign execute_if.imm = ibuffer_if.imm;
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assign execute_if.use_PC = ibuffer_if.use_PC;
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assign execute_if.use_imm = ibuffer_if.use_imm;
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VX_instr_demux instr_demux (
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.clk (clk),
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.reset (demux_reset),
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.ibuffer_if (execute_if),
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.ibuffer_if (idmux_ib_if),
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.gpr_rsp_if (gpr_rsp_if),
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.alu_req_if (alu_req_if),
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.lsu_req_if (lsu_req_if),
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@ -94,10 +114,7 @@ module VX_issue #(
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.fpu_req_if (fpu_req_if),
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`endif
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.gpu_req_if (gpu_req_if)
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);
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// issue the instruction
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assign ibuffer_if.ready = !scoreboard_delay && execute_if.ready;
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);
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`SCOPE_ASSIGN (issue_fire, ibuffer_if.valid && ibuffer_if.ready);
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`SCOPE_ASSIGN (issue_wid, ibuffer_if.wid);
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@ -115,7 +132,7 @@ module VX_issue #(
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`SCOPE_ASSIGN (issue_use_pc, ibuffer_if.use_PC);
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`SCOPE_ASSIGN (issue_use_imm, ibuffer_if.use_imm);
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`SCOPE_ASSIGN (scoreboard_delay, scoreboard_delay);
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`SCOPE_ASSIGN (execute_delay, ~execute_if.ready);
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`SCOPE_ASSIGN (execute_delay, ~idmux_ib_if.ready);
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`SCOPE_ASSIGN (gpr_rsp_a, gpr_rsp_if.rs1_data);
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`SCOPE_ASSIGN (gpr_rsp_b, gpr_rsp_if.rs2_data);
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`SCOPE_ASSIGN (gpr_rsp_c, gpr_rsp_if.rs3_data);
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@ -22,19 +22,19 @@ module VX_pipeline #(
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input wire dcache_rsp_valid,
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input wire [`NUM_THREADS-1:0] dcache_rsp_tmask,
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input wire [`NUM_THREADS-1:0][31:0] dcache_rsp_data,
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input wire [`DCACHE_CORE_TAG_WIDTH-1:0] dcache_rsp_tag,
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input wire [`DCACHE_CORE_TAG_WIDTH-1:0] dcache_rsp_tag,
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output wire dcache_rsp_ready,
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// Icache core request
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output wire icache_req_valid,
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output wire [29:0] icache_req_addr,
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output wire [`ICACHE_CORE_TAG_WIDTH-1:0] icache_req_tag,
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output wire [`ICACHE_CORE_TAG_WIDTH-1:0] icache_req_tag,
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input wire icache_req_ready,
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// Icache core response
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input wire icache_rsp_valid,
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input wire [31:0] icache_rsp_data,
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input wire [`ICACHE_CORE_TAG_WIDTH-1:0] icache_rsp_tag,
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input wire [`ICACHE_CORE_TAG_WIDTH-1:0] icache_rsp_tag,
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output wire icache_rsp_ready,
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`ifdef PERF_ENABLE
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@ -3,12 +3,11 @@
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module VX_scoreboard #(
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parameter CORE_ID = 0
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) (
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input wire clk,
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input wire reset,
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input wire clk,
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input wire reset,
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VX_ibuffer_if.slave ibuffer_if,
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VX_writeback_if.slave writeback_if,
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output wire delay
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VX_ibuffer_if.scoreboard ibuffer_if,
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VX_writeback_if.scoreboard writeback_if
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);
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reg [`NUM_WARPS-1:0][`NUM_REGS-1:0] inuse_regs, inuse_regs_n;
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@ -43,7 +42,12 @@ module VX_scoreboard #(
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deq_inuse_rs3 <= inuse_regs_n[ibuffer_if.wid_n][ibuffer_if.rs3_n];
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end
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assign delay = deq_inuse_rd | deq_inuse_rs1 | deq_inuse_rs2 | deq_inuse_rs3;
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assign writeback_if.ready = 1'b1;
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assign ibuffer_if.ready = ~(deq_inuse_rd
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| deq_inuse_rs1
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| deq_inuse_rs2
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| deq_inuse_rs3);
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`UNUSED_VAR (writeback_if.PC)
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5
hw/rtl/cache/VX_shared_mem.v
vendored
5
hw/rtl/cache/VX_shared_mem.v
vendored
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@ -157,7 +157,8 @@ module VX_shared_mem #(
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.valid_out (creq_out_valid)
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);
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wire crsq_last_read;
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wire crsq_in_valid, crsq_in_ready;
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wire crsq_last_read;
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assign creq_out_ready = core_req_writeonly
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|| (crsq_in_ready && crsq_last_read);
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@ -195,8 +196,6 @@ module VX_shared_mem #(
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wire [CORE_TAG_WIDTH-1:0] core_rsp_tag_in;
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reg [NUM_BANKS-1:0] bank_rsp_sel_r, bank_rsp_sel_n;
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wire crsq_in_valid, crsq_in_ready;
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wire crsq_in_fire = crsq_in_valid && crsq_in_ready;
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assign crsq_last_read = (bank_rsp_sel_n == core_req_read_mask);
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@ -76,6 +76,20 @@ interface VX_ibuffer_if ();
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input wid_n,
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output ready
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);
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modport scoreboard (
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input valid,
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input wid,
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input PC,
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input wb,
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input rd,
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input rd_n,
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input rs1_n,
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input rs2_n,
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input rs3_n,
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input wid_n,
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output ready
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);
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endinterface
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@ -36,6 +36,15 @@ interface VX_writeback_if ();
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output ready
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);
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modport scoreboard (
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input valid,
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input wid,
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input PC,
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input rd,
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input eop,
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output ready
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);
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endinterface
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`endif
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