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minor fixes

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This commit is contained in:
Blaise Tine 2023-06-25 07:54:28 -04:00
parent b645786ff0
commit 1a5382c48c
6 changed files with 68 additions and 55 deletions
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4
hw/rtl/afu/opae/vortex_afu.sv
View file

@ -96,7 +96,9 @@ module vortex_afu #(
8'(`NUM_THREADS),
8'(`IMPLEMENTATION_ID)};
wire [63:0] isa_caps = {32'(`MISA_EXT), 2'($clog2(`XLEN)-4), 30'(`MISA_STD)};
wire [63:0] isa_caps = {32'(`MISA_EXT),
2'($clog2(`XLEN)-4),
30'(`MISA_STD)};
reg [STATE_WIDTH-1:0] state;

12
hw/rtl/afu/xrt/VX_afu_ctrl.sv
View file

@ -127,8 +127,16 @@ module VX_afu_ctrl #(
RSTATE_DATA = 2'd1;
// device caps
wire [63:0] dev_caps = {24'b0, 8'(`NUM_CLUSTERS), 8'(`NUM_CORES), 8'(`NUM_WARPS), 8'(`NUM_THREADS), 8'(`IMPLEMENTATION_ID)};
wire [63:0] isa_caps = {32'(`MISA_EXT), 2'($clog2(`XLEN)-4), 30'(`MISA_STD)};
wire [63:0] dev_caps = {24'b0,
8'(`NUM_CLUSTERS),
8'(`NUM_CORES),
8'(`NUM_WARPS),
8'(`NUM_THREADS),
8'(`IMPLEMENTATION_ID)};
wire [63:0] isa_caps = {32'(`MISA_EXT),
2'($clog2(`XLEN)-4),
30'(`MISA_STD)};
reg [1:0] wstate;
reg [ADDR_BITS-1:0] waddr;

55
hw/rtl/core/VX_csr_data.sv
View file

@ -57,6 +57,7 @@ module VX_csr_data #(
`UNUSED_VAR (reset)
`UNUSED_VAR (write_wid)
`UNUSED_VAR (write_data)
// CSRs Write /////////////////////////////////////////////////////////////
@ -64,16 +65,6 @@ module VX_csr_data #(
reg [`NUM_WARPS-1:0][`INST_FRM_BITS+`FP_FLAGS_BITS-1:0] fcsr;
`endif
reg [31:0] csr_satp;
reg [31:0] csr_mstatus;
reg [31:0] csr_medeleg;
reg [31:0] csr_mideleg;
reg [31:0] csr_mie;
reg [31:0] csr_mtvec;
reg [31:0] csr_mepc;
reg [31:0] csr_pmpcfg;
reg [31:0] csr_pmpaddr;
always @(posedge clk) begin
`ifdef EXT_F_ENABLE
if (reset) begin
@ -81,7 +72,7 @@ module VX_csr_data #(
end else begin
if (fpu_to_csr_if.write_enable) begin
fcsr[fpu_to_csr_if.write_wid][`FP_FLAGS_BITS-1:0] <= fcsr[fpu_to_csr_if.write_wid][`FP_FLAGS_BITS-1:0]
| fpu_to_csr_if.write_fflags;
| fpu_to_csr_if.write_fflags;
end
end
`endif
@ -92,16 +83,16 @@ module VX_csr_data #(
`VX_CSR_FRM: fcsr[write_wid][`INST_FRM_BITS+`FP_FLAGS_BITS-1:`FP_FLAGS_BITS] <= write_data[`INST_FRM_BITS-1:0];
`VX_CSR_FCSR: fcsr[write_wid] <= write_data[`FP_FLAGS_BITS+`INST_FRM_BITS-1:0];
`endif
`VX_CSR_SATP: csr_satp <= write_data;
`VX_CSR_SATP,
`VX_CSR_MSTATUS,
`VX_CSR_MNSTATUS: csr_mstatus <= write_data;
`VX_CSR_MEDELEG: csr_medeleg <= write_data;
`VX_CSR_MIDELEG: csr_mideleg <= write_data;
`VX_CSR_MIE: csr_mie <= write_data;
`VX_CSR_MTVEC: csr_mtvec <= write_data;
`VX_CSR_MEPC: csr_mepc <= write_data;
`VX_CSR_PMPCFG0: csr_pmpcfg <= write_data;
`VX_CSR_PMPADDR0: csr_pmpaddr <= write_data;
`VX_CSR_MNSTATUS,
`VX_CSR_MEDELEG,
`VX_CSR_MIDELEG,
`VX_CSR_MIE,
`VX_CSR_MTVEC,
`VX_CSR_MEPC,
`VX_CSR_PMPCFG0,
`VX_CSR_PMPADDR0: /* do nothing!*/;
default: begin
`ASSERT(0, ("%t: *** invalid CSR write address: %0h (#%0d)", $time, write_addr, write_uuid));
end
@ -140,25 +131,21 @@ module VX_csr_data #(
`VX_CSR_MINSTRET : read_data_ro_r = 32'(commit_csr_if.instret[31:0]);
`VX_CSR_MINSTRET_H : read_data_ro_r = 32'(commit_csr_if.instret[`PERF_CTR_BITS-1:32]);
`VX_CSR_SATP : read_data_ro_r = 32'(csr_satp);
`VX_CSR_SATP,
`VX_CSR_MSTATUS,
`VX_CSR_MNSTATUS : read_data_ro_r = 32'(csr_mstatus);
`VX_CSR_MISA : read_data_ro_r = ((($clog2(`XLEN)-4) << (`XLEN-2)) | `MISA_STD);
`VX_CSR_MEDELEG : read_data_ro_r = 32'(csr_medeleg);
`VX_CSR_MIDELEG : read_data_ro_r = 32'(csr_mideleg);
`VX_CSR_MIE : read_data_ro_r = 32'(csr_mie);
`VX_CSR_MTVEC : read_data_ro_r = 32'(csr_mtvec);
`VX_CSR_MEPC : read_data_ro_r = 32'(csr_mepc);
`VX_CSR_PMPCFG0 : read_data_ro_r = 32'(csr_pmpcfg);
`VX_CSR_PMPADDR0 : read_data_ro_r = 32'(csr_pmpaddr);
`VX_CSR_MNSTATUS,
`VX_CSR_MEDELEG,
`VX_CSR_MIDELEG,
`VX_CSR_MIE,
`VX_CSR_MTVEC,
`VX_CSR_MEPC,
`VX_CSR_PMPCFG0,
`VX_CSR_PMPADDR0 : read_data_ro_r = 32'(0);
`VX_CSR_MVENDORID : read_data_ro_r = 32'(`VENDOR_ID);
`VX_CSR_MARCHID : read_data_ro_r = 32'(`ARCHITECTURE_ID);
`VX_CSR_MIMPID : read_data_ro_r = 32'(`IMPLEMENTATION_ID);
`VX_CSR_MHARTID : read_data_ro_r = 32'(`IMPLEMENTATION_ID);
`VX_CSR_MISA : read_data_ro_r = ((($clog2(`XLEN)-4) << (`XLEN-2)) | `MISA_STD);
default: begin
read_addr_valid_r = 0;

41
kernel/src/vx_spawn.c
View file

@ -47,11 +47,15 @@ inline int fast_log2(int x) {
}
static void __attribute__ ((noinline)) spawn_tasks_all_stub() {
int core_id = vx_cluster_id() * vx_num_cores() + vx_core_id();
int wid = vx_warp_id();
int tid = vx_thread_id();
int NT = vx_num_threads();
int NC = vx_num_cores();
int NT = vx_num_threads();
int gid = vx_cluster_id();
int cid = vx_core_id();
int wid = vx_warp_id();
int tid = vx_thread_id();
int core_id = gid * NC + cid;
wspawn_tasks_args_t* p_wspawn_args = (wspawn_tasks_args_t*)g_wspawn_args[core_id];
int wK = (p_wspawn_args->N * wid) + MIN(p_wspawn_args->R, wid);
@ -68,9 +72,14 @@ static void __attribute__ ((noinline)) spawn_tasks_all_stub() {
vx_barrier(0, p_wspawn_args->NW);
}
static void __attribute__ ((noinline)) spawn_tasks_rem_stub() {
int core_id = vx_cluster_id() * vx_num_cores() + vx_core_id();
static void __attribute__ ((noinline)) spawn_tasks_rem_stub() {
int NC = vx_num_cores();
int gid = vx_cluster_id();
int cid = vx_core_id();
int core_id = gid * NC + cid;
int hart_id = vx_hart_id();
wspawn_tasks_args_t* p_wspawn_args = (wspawn_tasks_args_t*)g_wspawn_args[core_id];
int task_id = p_wspawn_args->offset + hart_id;
(p_wspawn_args->callback)(task_id, p_wspawn_args->arg);
@ -159,10 +168,14 @@ void vx_spawn_tasks(int num_tasks, vx_spawn_tasks_cb callback , void * arg) {
///////////////////////////////////////////////////////////////////////////////
static void __attribute__ ((noinline)) spawn_kernel_all_stub() {
int core_id = vx_cluster_id() * vx_num_cores() + vx_core_id();
int wid = vx_warp_id();
int tid = vx_thread_id();
int NT = vx_num_threads();
int NC = vx_num_cores();
int NT = vx_num_threads();
int gid = vx_cluster_id();
int cid = vx_core_id();
int wid = vx_warp_id();
int tid = vx_thread_id();
int core_id = gid * NC + cid;
wspawn_kernel_args_t* p_wspawn_args = (wspawn_kernel_args_t*)g_wspawn_args[core_id];
@ -192,7 +205,11 @@ static void __attribute__ ((noinline)) spawn_kernel_all_stub() {
}
static void __attribute__ ((noinline)) spawn_kernel_rem_stub() {
int core_id = vx_cluster_id() * vx_num_cores() + vx_core_id();
int NC = vx_num_cores();
int gid = vx_cluster_id();
int cid = vx_core_id();
int core_id = gid * NC + cid;
int hart_id = vx_hart_id();
wspawn_kernel_args_t* p_wspawn_args = (wspawn_kernel_args_t*)g_wspawn_args[core_id];

7
runtime/opae/vortex.cpp
View file

@ -114,10 +114,10 @@ extern int vx_dev_caps(vx_device_h hdevice, uint32_t caps_id, uint64_t *value) {
*value = (device->dev_caps >> 16) & 0xff;
break;
case VX_CAPS_NUM_CORES:
*value = (device->dev_caps >> 32) & 0xff;
*value = (device->dev_caps >> 24) & 0xff;
break;
case VX_CAPS_NUM_CLUSTERS:
*value = (device->dev_caps >> 40) & 0xff;
*value = (device->dev_caps >> 32) & 0xff;
break;
case VX_CAPS_CACHE_LINE_SIZE:
*value = CACHE_BLOCK_SIZE;
@ -231,8 +231,7 @@ extern int vx_dev_open(vx_device_h* hdevice) {
return -1;
});
// Load device CAPS
// Load device CAPS
CHECK_ERR(api.fpgaReadMMIO64(device->fpga, 0, MMIO_DEV_CAPS, &device->dev_caps), {
api.fpgaClose(accel_handle);
return -1;

4
runtime/xrt/vortex.cpp
View file

@ -510,10 +510,10 @@ extern int vx_dev_caps(vx_device_h hdevice, uint32_t caps_id, uint64_t *value) {
*value = (device->dev_caps >> 16) & 0xff;
break;
case VX_CAPS_NUM_CORES:
*value = (device->dev_caps >> 32) & 0xff;
*value = (device->dev_caps >> 24) & 0xff;
break;
case VX_CAPS_NUM_CLUSTERS:
*value = (device->dev_caps >> 40) & 0xff;
*value = (device->dev_caps >> 32) & 0xff;
break;
case VX_CAPS_CACHE_LINE_SIZE:
*value = CACHE_BLOCK_SIZE;