minor update

hw/rtl/cache/VX_cache_bypass.sv

@@ -205,7 +205,7 @@ module VX_cache_bypass #(
                 .POS (TAG_SEL_IDX)
             ) mem_req_tag_in_nc_insert (
                 .data_in  (mem_bus_in_if.req_valid ? (MEM_TAG_OUT_WIDTH-1)'(mem_bus_in_if.req_data.tag) : (MEM_TAG_OUT_WIDTH-1)'(mem_req_tag_bypass)),
-                .sel_in   (~mem_bus_in_if.req_valid),
+                .ins_in   (~mem_bus_in_if.req_valid),
                 .data_out (mem_req_out_tag)
             );
         end else begin

hw/rtl/libs/VX_bits_insert.sv

@@ -20,19 +20,19 @@ module VX_bits_insert #(
     parameter POS = 0
 ) (
     input wire [N-1:0]      data_in,    
-    input wire [`UP(S)-1:0] sel_in,    
+    input wire [`UP(S)-1:0] ins_in,    
     output wire [N+S-1:0]   data_out
 ); 
     if (S == 0) begin
-        `UNUSED_VAR (sel_in)
+        `UNUSED_VAR (ins_in)
         assign data_out = data_in;
     end else begin
         if (POS == 0) begin
-            assign data_out = {data_in, sel_in};
+            assign data_out = {data_in, ins_in};
         end else if (POS == N) begin
-            assign data_out = {sel_in, data_in};
+            assign data_out = {ins_in, data_in};
         end else begin
-            assign data_out = {data_in[N-1:POS], sel_in, data_in[POS-1:0]};
+            assign data_out = {data_in[N-1:POS], ins_in, data_in[POS-1:0]};
         end
     end
 

hw/rtl/mem/VX_mem_arb.sv

@@ -79,7 +79,7 @@ module VX_mem_arb #(
             .POS (TAG_SEL_IDX)
         ) bits_insert (
             .data_in  (req_tag_out),
-            .sel_in   (req_sel_out[i]),
+            .ins_in   (req_sel_out[i]),
             .data_out (bus_out_if[i].req_data.tag)
         );
         assign bus_out_if[i].req_valid = req_valid_out[i];

kernel/src/vx_start.S

@@ -98,7 +98,7 @@ init_regs:
   li    sp, (STACK_BASE_ADDR & 0xffffffff)
   or    sp, sp, t0
 #else
-  li    sp, STACK_BASE_ADDR # load stack base address
+  li    sp, STACK_BASE_ADDR
 #endif
   csrr  t0, VX_CSR_MHARTID
   sll   t1, t0, STACK_LOG2_SIZE