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https://github.com/vortexgpgpu/vortex.git
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constant integration updates, cache bank incoming_fill optimization
This commit is contained in:
Blaise Tine
parent
2904f6441d
commit
1bc4b8e7a8
3 changed files with 135 additions and 51 deletions
13
.travis.yml
13
.travis.yml
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@ -1,7 +1,7 @@
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language: cpp
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dist: bionic
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os: linux
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compiler: clang
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compiler: gcc
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addons:
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apt:
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sources:
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@ -20,12 +20,19 @@ install:
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- export PATH=$VERILATOR_ROOT/bin:$PATH
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script:
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- make -j > /dev/null 2>&1
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- make -j
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- ci/test_runtime.sh
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- ci/test_driver.sh
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- ci/test_riscv_isa.sh
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- ci/test_opencl.sh
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- ci/blackbox.sh
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- ci/blackbox.sh -run_1c
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- ci/blackbox.sh -run_2c
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- ci/blackbox.sh -run_4c
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- ci/blackbox.sh -run_4c_l2
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- ci/blackbox.sh -run_8c_2l2
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- ci/blackbox.sh -run_16c_4l2_l3
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- ci/blackbox.sh -run_debug
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- ci/blackbox.sh -run_scope
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after_success:
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# Gather code coverage
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137
ci/blackbox.sh
137
ci/blackbox.sh
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@ -1,41 +1,112 @@
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#!/bin/sh
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# test single core
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make -C driver/opae/vlsim clean
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CONFIGS="-DNUM_CLUSTERS=1 -DNUM_CORES=1" make -C driver/opae/vlsim > /dev/null 2>&1
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make -C driver/tests/dogfood run-vlsim
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make -C benchmarks/opencl/sgemm run-vlsim
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run_1c()
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{
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# test single core
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make -C driver/opae/vlsim clean
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CONFIGS="-DNUM_CLUSTERS=1 -DNUM_CORES=1" make -C driver/opae/vlsim
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make -C driver/tests/dogfood run-vlsim
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make -C benchmarks/opencl/sgemm run-vlsim
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}
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# test 2 cores
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make -C driver/opae/vlsim clean
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CONFIGS="-DNUM_CLUSTERS=1 -DNUM_CORES=2 -DL2_ENABLE=0" make -C driver/opae/vlsim > /dev/null 2>&1
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make -C driver/tests/dogfood run-vlsim
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make -C benchmarks/opencl/sgemm run-vlsim
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run_2c()
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{
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# test 2 cores
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make -C driver/opae/vlsim clean
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CONFIGS="-DNUM_CLUSTERS=1 -DNUM_CORES=2 -DL2_ENABLE=0" make -C driver/opae/vlsim
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make -C driver/tests/dogfood run-vlsim
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make -C benchmarks/opencl/sgemm run-vlsim
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}
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# test 4 cores with L2
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make -C driver/opae/vlsim clean
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CONFIGS="-DNUM_CLUSTERS=1 -DNUM_CORES=4 -DL2_ENABLE=1" make -C driver/opae/vlsim > /dev/null 2>&1
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make -C driver/tests/dogfood run-vlsim
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make -C benchmarks/opencl/sgemm run-vlsim
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run_4c()
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{
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# test 4 cores
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make -C driver/opae/vlsim clean
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CONFIGS="-DNUM_CLUSTERS=1 -DNUM_CORES=4 -DL2_ENABLE=0" make -C driver/opae/vlsim
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make -C driver/tests/dogfood run-vlsim
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make -C benchmarks/opencl/sgemm run-vlsim
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}
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# test 8 cores with L2
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make -C driver/opae/vlsim clean
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CONFIGS="-DNUM_CLUSTERS=2 -DNUM_CORES=4 -DL2_ENABLE=1" make -C driver/opae/vlsim > /dev/null 2>&1
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make -C driver/tests/dogfood run-vlsim
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make -C benchmarks/opencl/sgemm run-vlsim
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run_4c_l2()
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{
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# test 4 cores with L2
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make -C driver/opae/vlsim clean
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CONFIGS="-DNUM_CLUSTERS=1 -DNUM_CORES=4 -DL2_ENABLE=1" make -C driver/opae/vlsim
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make -C driver/tests/dogfood run-vlsim
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make -C benchmarks/opencl/sgemm run-vlsim
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}
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# test 16 cores with L2 and L3
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make -C driver/opae/vlsim clean
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CONFIGS="-DNUM_CLUSTERS=4 -DNUM_CORES=4 -DL2_ENABLE=1 -DL3_ENABLE=1" make -C driver/opae/vlsim > /dev/null 2>&1
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make -C driver/tests/dogfood run-vlsim
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make -C benchmarks/opencl/sgemm run-vlsim
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run_8c_2l2()
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{
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# test 8 cores with 2xL2
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make -C driver/opae/vlsim clean
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CONFIGS="-DNUM_CLUSTERS=2 -DNUM_CORES=4 -DL2_ENABLE=1" make -C driver/opae/vlsim
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make -C driver/tests/dogfood run-vlsim
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make -C benchmarks/opencl/sgemm run-vlsim
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}
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# test debug build
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make -C driver/opae/vlsim clean
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DEBUG=1 CONFIGS="-DNUM_CLUSTERS=1 -DNUM_CORES=1" make -C driver/opae/vlsim > /dev/null 2>&1
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make -C driver/tests/demo run-vlsim
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run_16c_4l2_l3()
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{
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# test 16 cores with L2 and L3
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make -C driver/opae/vlsim clean
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CONFIGS="-DNUM_CLUSTERS=4 -DNUM_CORES=4 -DL2_ENABLE=1 -DL3_ENABLE=1" make -C driver/opae/vlsim
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make -C driver/tests/dogfood run-vlsim
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make -C benchmarks/opencl/sgemm run-vlsim
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}
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# test build with scope analyzer
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make -C driver/opae clean
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SCOPE=1 CONFIGS="-DNUM_CLUSTERS=1 -DNUM_CORES=1" make -C driver/opae > /dev/null 2>&1
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make -C driver/tests/demo run-vlsim
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run_debug()
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{
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# test debug build
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make -C driver/opae/vlsim clean
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DEBUG=1 CONFIGS="-DNUM_CLUSTERS=1 -DNUM_CORES=1" make -C driver/opae/vlsim
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make -C driver/tests/demo run-vlsim
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}
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run_scope()
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{
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# test build with scope analyzer
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make -C driver/opae clean
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SCOPE=1 CONFIGS="-DNUM_CLUSTERS=1 -DNUM_CORES=1" make -C driver/opae
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make -C driver/tests/demo run-vlsim
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}
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usage()
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{
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echo "usage: blackbox [[-run_1c] [-run_2c] [-run_4c] [-run_4c_l2] [-run_8c_2l2] [-run_16c_4l2_l3] [-run_debug] [-run_scope] [-all] [-h|--help]]"
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}
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while [ "$1" != "" ]; do
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case $1 in
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-run_1c ) run_1c
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;;
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-run_2c ) run_2c
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;;
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-run_4c ) run_4c
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;;
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-run_4c_l2 ) run_4c_l2
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;;
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-run_8c_2l2 ) run_8c_2l2
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;;
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-run_16c_4l2_l3 ) run_16c_4l2_l3
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;;
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-run_debug ) run_debug
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;;
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-run_scope ) run_scope
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;;
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-all ) run_1c
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run_2c
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run_4c
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run_4c_l2
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run_8c_2l2
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run_16c_4l2_l3
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run_debug
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run_scope
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;;
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-h | --help ) usage
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exit
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;;
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* ) usage
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exit 1
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esac
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shift
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done
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36
hw/rtl/cache/VX_bank.v
vendored
36
hw/rtl/cache/VX_bank.v
vendored
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@ -168,11 +168,10 @@ module VX_bank #(
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wire [`LINE_ADDR_WIDTH-1:0] dfpq_addr_st0;
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wire [`BANK_LINE_WIDTH-1:0] dfpq_filldata_st0;
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wire dram_rsp_fire = dram_rsp_valid && dram_rsp_ready;
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assign dram_rsp_ready = !dfpq_full;
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if (DRAM_ENABLE) begin
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wire dram_rsp_fire = dram_rsp_valid && dram_rsp_ready;
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VX_generic_queue #(
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.DATAW(`LINE_ADDR_WIDTH + $bits(dram_rsp_data)),
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.SIZE(DRFQ_SIZE)
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@ -535,9 +534,10 @@ module VX_bank #(
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wire snp_invalidate_st3;
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wire is_msrq_st3;
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wire send_core_rsp_st3;
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wire send_fill_req_st3;
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wire send_dwb_req_st3;
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wire do_writeback_st3;
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wire send_snp_rsp_st3;
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wire incoming_fill_st3;
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wire send_core_rsp_st2 = valid_st2 && !is_fill_st2 && !is_snp_st2 && !miss_st2 && !force_miss_st2;
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@ -549,17 +549,27 @@ module VX_bank #(
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&& (is_fill_st2
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|| (!force_miss_st2 && is_snp_st2));
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wire send_dwb_req_st2 = send_fill_req_st2 || do_writeback_st2;
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wire send_snp_rsp_st2 = valid_st2 && is_snp_st2 && !force_miss_st2;
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// check if a matching fill request is comming
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wire incoming_fill_dfp_st2 = dram_rsp_fire && (addr_st2 == dram_rsp_addr);
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wire incoming_fill_st0_st2 = !dfpq_empty && (addr_st2 == dfpq_addr_st0);
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wire incoming_fill_st1_st2 = is_fill_st1 && (addr_st2 == addr_st1);
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wire incoming_fill_st2 = incoming_fill_dfp_st2
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|| incoming_fill_st0_st2
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|| incoming_fill_st1_st2;
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VX_generic_register #(
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.N(1+ 1+ 1 + 1 + 1 + 1 + 1 + 1 + `LINE_ADDR_WIDTH + `UP(`WORD_SELECT_WIDTH) + `WORD_WIDTH + `WORD_WIDTH + `BANK_LINE_WIDTH + `TAG_SELECT_BITS + 1 + 1 + BANK_LINE_SIZE + `REQ_INST_META_WIDTH)
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.N(1+ 1+ 1 + 1 + 1 + 1 + 1 + 1 + 1 + `LINE_ADDR_WIDTH + `UP(`WORD_SELECT_WIDTH) + `WORD_WIDTH + `WORD_WIDTH + `BANK_LINE_WIDTH + `TAG_SELECT_BITS + 1 + 1 + BANK_LINE_SIZE + `REQ_INST_META_WIDTH)
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) pipe_reg2 (
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.clk (clk),
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.reset (reset),
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.stall (pipeline_stall),
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.flush (1'b0),
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.in ({is_msrq_st2, send_core_rsp_st2, send_fill_req_st2, do_writeback_st2, send_snp_rsp_st2, force_miss_st2, is_snp_st2, snp_invalidate_st2, valid_st2, addr_st2, wsel_st2, writeword_st2, readword_st2, readdata_st2, readtag_st2, miss_st2, dirtyb_st2, inst_meta_st2}),
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.out ({is_msrq_st3, send_core_rsp_st3, send_fill_req_st3, do_writeback_st3, send_snp_rsp_st3, force_miss_st3, is_snp_st3, snp_invalidate_st3, valid_st3, addr_st3, wsel_st3, writeword_st3, readword_st3, readdata_st3, readtag_st3, miss_st3, dirtyb_st3, inst_meta_st3})
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.in ({is_msrq_st2, incoming_fill_st2, send_core_rsp_st2, send_dwb_req_st2, do_writeback_st2, send_snp_rsp_st2, force_miss_st2, is_snp_st2, snp_invalidate_st2, valid_st2, addr_st2, wsel_st2, writeword_st2, readword_st2, readdata_st2, readtag_st2, miss_st2, dirtyb_st2, inst_meta_st2}),
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.out ({is_msrq_st3, incoming_fill_st3, send_core_rsp_st3, send_dwb_req_st3, do_writeback_st3, send_snp_rsp_st3, force_miss_st3, is_snp_st3, snp_invalidate_st3, valid_st3, addr_st3, wsel_st3, writeword_st3, readword_st3, readdata_st3, readtag_st3, miss_st3, dirtyb_st3, inst_meta_st3})
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);
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`ifdef DBG_CACHE_REQ_INFO
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@ -590,13 +600,9 @@ module VX_bank #(
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assign {req_tag_st3, req_rw_st3, req_byteen_st3, req_tid_st3} = inst_meta_st3;
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// check if a matching fill request is comming
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wire incoming_st0_fill_st3 = is_fill_st0 && (addr_st3 == dfpq_addr_st0);
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wire incoming_st1_fill_st3 = is_fill_st1 && (addr_st3 == addr_st1);
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wire incoming_st2_fill_st3 = is_fill_st2 && (addr_st3 == addr_st2);
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wire incoming_fill = incoming_st2_fill_st3
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|| incoming_st1_fill_st3
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|| incoming_st0_fill_st3;
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wire incoming_fill_dfp_st3 = dram_rsp_fire && (addr_st3 == dram_rsp_addr);
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wire incoming_fill = incoming_fill_dfp_st3
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|| incoming_fill_st3;
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if (DRAM_ENABLE) begin
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wire msrq_dequeue_st3 = valid_st3 && is_msrq_st3 && !msrq_push_unqual && !pipeline_stall;
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@ -732,12 +738,12 @@ module VX_bank #(
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wire dwbq_empty, dwbq_full;
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wire dwbq_push_unqual = send_fill_req_st3 || do_writeback_st3;
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wire dwbq_push_unqual = send_dwb_req_st3;
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assign dwbq_push_stall = dwbq_push_unqual && dwbq_full;
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wire dwbq_push = dwbq_push_unqual
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&& !(send_fill_req_st3 && incoming_fill) // not in 'dwbq_push_stall' to reduce clock delay
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&& (do_writeback_st3 || !incoming_fill) // not in 'dwbq_push_stall' to reduce clock delay
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&& !dwbq_full
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&& !msrq_push_stall
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&& !cwbq_push_stall
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