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erge branch 'develop' of https://github.com/vortexgpgpu/vortex into develop

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This commit is contained in:
Blaise Tine 2023-12-18 03:17:05 -08:00
commit 1be3778731
2 changed files with 33 additions and 29 deletions
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2
hw/rtl/VX_gpu_pkg.sv
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@ -224,7 +224,7 @@ package VX_gpu_pkg;
input logic [`NW_WIDTH-1:0] wid
);
if (ISSUE_WIS != 0) begin
wid_to_wis = wid[`NW_WIDTH-1:ISSUE_ISW];
wid_to_wis = ISSUE_WIS_W'(wid >> ISSUE_ISW);
end else begin
wid_to_wis = 0;
end

60
hw/rtl/core/VX_operands.sv
View file

@ -239,15 +239,18 @@ module VX_operands import VX_gpu_pkg::*; #(
// GPR banks
wire [RAM_ADDRW-1:0] gpr_rd_addr;
reg [RAM_ADDRW-1:0] gpr_rd_addr;
wire [RAM_ADDRW-1:0] gpr_wr_addr;
if (ISSUE_WIS != 0) begin
assign gpr_rd_addr = {gpr_rd_wis, gpr_rd_rid};
assign gpr_wr_addr = {writeback_if[i].data.wis, writeback_if[i].data.rd};
always @(posedge clk) begin
gpr_rd_addr <= {gpr_rd_wis_n, gpr_rd_rid_n};
end
end else begin
assign gpr_rd_addr = gpr_rd_rid;
assign gpr_wr_addr = writeback_if[i].data.rd;
always @(posedge clk) begin
gpr_rd_addr <= gpr_rd_rid_n;
end
end
`ifdef GPR_RESET
@ -258,30 +261,31 @@ module VX_operands import VX_gpu_pkg::*; #(
end
end
`endif
VX_dp_ram #(
.DATAW (`XLEN * `NUM_THREADS),
.SIZE (`NUM_REGS * ISSUE_RATIO),
.WRENW (`NUM_THREADS),
`ifdef GPR_RESET
.INIT_ENABLE (1),
.INIT_VALUE (0),
`endif
.NO_RWCHECK (1)
) gpr_ram (
.clk (clk),
.read (1'b1),
.wren (writeback_if[i].data.tmask),
`ifdef GPR_RESET
.write (wr_enabled && writeback_if[i].valid),
`else
.write (writeback_if[i].valid),
`endif
.waddr (gpr_wr_addr),
.wdata (writeback_if[i].data.data),
.raddr (gpr_rd_addr),
.rdata (gpr_rd_data)
);
for (genvar j = 0; j < `NUM_THREADS; ++j) begin
VX_dp_ram #(
.DATAW (`XLEN),
.SIZE (`NUM_REGS * ISSUE_RATIO),
`ifdef GPR_RESET
.INIT_ENABLE (1),
.INIT_VALUE (0),
`endif
.NO_RWCHECK (1)
) gpr_ram (
.clk (clk),
.read (1'b1),
`UNUSED_PIN (wren),
`ifdef GPR_RESET
.write (wr_enabled && writeback_if[i].valid && writeback_if[i].data.tmask[j]),
`else
.write (writeback_if[i].valid && writeback_if[i].data.tmask[j]),
`endif
.waddr (gpr_wr_addr),
.wdata (writeback_if[i].data.data[j]),
.raddr (gpr_rd_addr),
.rdata (gpr_rd_data[j])
);
end
end
endmodule