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ICache_In_Place
This commit is contained in:
Lyons, Ethan Tyler
GitHub Enterprise
parent
6c4cd2468f
commit
1c21110ffe
3 changed files with 177 additions and 48 deletions
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@ -15,7 +15,7 @@
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extern "C" {
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void load_file (char * filename);
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void ibus_driver (bool clk, unsigned pc_addr, unsigned * instruction);
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void ibus_driver (bool clk, unsigned o_m_read_addr, unsigned o_m_evict_addr, bool o_m_valid, svLogicVecVal * o_m_writedata, bool o_m_read_or_write, unsigned cache_banks, unsigned num_words_per_block, svLogicVecVal * i_m_readdata, bool * i_m_ready);
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void dbus_driver (bool clk, unsigned o_m_read_addr, unsigned o_m_evict_addr, bool o_m_valid, svLogicVecVal * o_m_writedata, bool o_m_read_or_write, unsigned cache_banks, unsigned num_words_per_block, svLogicVecVal * i_m_readdata, bool * i_m_ready);
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void io_handler (bool clk, bool io_valid, unsigned io_data);
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void gracefulExit(int);
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@ -24,6 +24,8 @@ extern "C" {
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RAM ram;
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bool refill;
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unsigned refill_addr;
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bool i_refill;
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unsigned i_refill_addr;
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unsigned num_cycles;
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@ -55,30 +57,125 @@ void load_file(char * filename)
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loadHexImpl(filename, &ram);
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// printf("Filename: %s\n", filename);
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refill = false;
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i_refill = false;
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}
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void ibus_driver(bool clk, unsigned pc_addr, unsigned * instruction)
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{
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// printf("Inside ibus_driver\n");
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void ibus_driver(bool clk, unsigned o_m_read_addr, unsigned o_m_evict_addr, bool o_m_valid, svLogicVecVal * o_m_writedata, bool o_m_read_or_write, unsigned cache_banks, unsigned num_words_per_block, svLogicVecVal * i_m_readdata, bool * i_m_ready)
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{
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// Default values
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{
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s_vpi_vecval * real_i_m_readdata = (s_vpi_vecval *) i_m_readdata;
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(*i_m_ready) = false;
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for (int i = 0; i < cache_banks; i++)
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{
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for (int j = 0; j < num_words_per_block; j++)
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{
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unsigned index = getIndex(i,j, num_words_per_block);
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real_i_m_readdata[index].aval = 0x506070;
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// svGetArrElemPtr2(i_m_readdata, i, j);
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// svPutLogicArrElem2VecVal(i_m_readdata, i, j);
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// i_m_readdata[getIndex(i,j, num_words_per_block)] = 0;
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}
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}
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}
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if (clk)
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{
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(*instruction) = 0;
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// Do nothing on positive edge
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}
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else
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{
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num_cycles++;
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uint32_t curr_inst = 0;
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curr_inst = 0xdeadbeef;
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uint32_t u_pc_addr = (uint32_t) (pc_addr);
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if (i_refill)
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{
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// svGetArrElemPtr2((*i_m_readdata), 0,0);
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// fprintf(stderr, "--------------------------------\n");
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i_refill = false;
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ram.getWord(u_pc_addr, &curr_inst);
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// printf("PC_addr: %x, instruction: %x\n", pc_addr, instruction);
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*i_m_ready = true;
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s_vpi_vecval * real_i_m_readdata = (s_vpi_vecval *) i_m_readdata;
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for (int curr_e = 0; curr_e < (cache_banks*num_words_per_block); curr_e++)
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{
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unsigned new_addr = i_refill_addr + (4*curr_e);
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unsigned addr_without_byte = new_addr >> 2;
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unsigned bits_per_bank = (int)log2(cache_banks);
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// unsigned maskbits_per_bank = calculate_bits_per_bank_num(bits_per_bank);
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unsigned maskbits_per_bank = cache_banks - 1;
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unsigned bank_num = addr_without_byte & maskbits_per_bank;
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unsigned addr_wihtout_bank = addr_without_byte >> bits_per_bank;
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unsigned offset_num = addr_wihtout_bank & (num_words_per_block-1);
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unsigned value;
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ram.getWord(new_addr, &value);
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fprintf(stdout, "-------- (%x) i_m_readdata[%d][%d] (%d) = %x\n", new_addr, bank_num, offset_num, curr_e, value);
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unsigned index = getIndex(bank_num,offset_num, num_words_per_block);
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// fprintf(stderr, "Index: %d (%d, %d) = %x\n", index, bank_num, offset_num, value);
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real_i_m_readdata[index].aval = value;
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}
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}
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else
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{
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if (o_m_valid)
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{
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s_vpi_vecval * real_o_m_writedata = (s_vpi_vecval *) o_m_writedata;
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if (o_m_read_or_write)
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{
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// fprintf(stderr, "++++++++++++++++++++++++++++++++\n");
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for (int curr_e = 0; curr_e < (cache_banks*num_words_per_block); curr_e++)
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{
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unsigned new_addr = (o_m_evict_addr) + (4*curr_e);
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unsigned addr_without_byte = new_addr >> 2;
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unsigned bits_per_bank = (int)log2(cache_banks);
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// unsigned maskbits_per_bank = calculate_bits_per_bank_num(bits_per_bank);
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unsigned maskbits_per_bank = cache_banks - 1;
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unsigned bank_num = addr_without_byte & maskbits_per_bank;
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unsigned addr_wihtout_bank = addr_without_byte >> bits_per_bank;
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unsigned offset_num = addr_wihtout_bank & (num_words_per_block-1);
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// unsigned offset_num = addr_wihtout_bank & 0x3;
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unsigned index = getIndex(bank_num,offset_num, num_words_per_block);
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unsigned new_value = real_o_m_writedata[index].aval;
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// new_value = (unsigned *) svGetArrElemPtr2(o_m_writedata, bank_num, offset_num);
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// new_value = getElem(o_m_writedata, index);
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// unsigned new_value = o_m_writedata[getIndex(bank_num,offset_num, num_words_per_block)];
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ram.writeWord( new_addr, &new_value);
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fprintf(stdout, "+++++++ (%x) writeback[%d][%d] (%d) = %x\n", new_addr, bank_num, offset_num, curr_e, new_value);
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}
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}
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// Respond next cycle
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i_refill = true;
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i_refill_addr = o_m_read_addr;
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}
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}
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(*instruction) = curr_inst;
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}
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}
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@ -1,8 +1,8 @@
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extern "C" {
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void load_file (char * filename);
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void ibus_driver (bool clk, unsigned pc_addr, unsigned * instruction);
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void dbus_driver (bool clk, unsigned o_m_read_addr, unsigned o_m_evict_addr, bool o_m_valid, svLogicVecVal * o_m_writedata, bool o_m_read_or_write, svOpenArrayHandle * i_m_readdata, bool * i_m_ready);
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void dbus_driver(bool clk, unsigned o_m_read_addr, unsigned o_m_evict_addr, bool o_m_valid, svLogicVecVal * o_m_writedata, bool o_m_read_or_write, unsigned cache_banks, unsigned num_words_per_block, svLogicVecVal * i_m_readdata, bool * i_m_ready);
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void ibus_driver(bool clk, unsigned o_m_read_addr, unsigned o_m_evict_addr, bool o_m_valid, svLogicVecVal * o_m_writedata, bool o_m_read_or_write, unsigned cache_banks, unsigned num_words_per_block, svLogicVecVal * i_m_readdata, bool * i_m_ready);
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void io_handler (bool clk, bool io_valid, unsigned io_data);
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void gracefulExit();
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}
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@ -10,8 +10,22 @@
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import "DPI-C" load_file = function void load_file(input string filename);
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/*
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import "DPI-C" ibus_driver = function void ibus_driver(input logic clk, input int pc_addr,
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output int instruction);
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*/
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import "DPI-C" ibus_driver = function void ibus_driver( input logic clk,
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input int o_m_read_addr,
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input int o_m_evict_addr,
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input logic o_m_valid,
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input reg[31:0] o_m_writedata[`ICACHE_BANKS - 1:0][`ICACHE_NUM_WORDS_PER_BLOCK-1:0],
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input logic o_m_read_or_write,
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input int cache_banks,
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input int words_per_block,
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// Rsp
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output reg[31:0] i_m_readdata[`ICACHE_BANKS - 1:0][`ICACHE_NUM_WORDS_PER_BLOCK-1:0],
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output logic i_m_ready);
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import "DPI-C" dbus_driver = function void dbus_driver( input logic clk,
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input int o_m_read_addr,
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@ -36,24 +50,35 @@ module vortex_tb (
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int cycle_num;
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reg clk;
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reg reset;
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reg[31:0] icache_response_instruction;
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reg[31:0] icache_request_pc_address;
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// IO
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reg io_valid;
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reg[31:0] io_data;
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// Req
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reg [31:0] o_m_read_addr;
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reg [31:0] o_m_evict_addr;
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reg o_m_valid;
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reg [31:0] o_m_writedata[`DCACHE_BANKS - 1:0][`DCACHE_NUM_WORDS_PER_BLOCK-1:0];
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reg o_m_read_or_write;
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reg clk;
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reg reset;
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reg[31:0] icache_response_instruction;
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reg[31:0] icache_request_pc_address;
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// IO
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reg io_valid;
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reg[31:0] io_data;
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// Req
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reg [31:0] o_m_read_addr_d;
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reg [31:0] o_m_evict_addr_d;
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reg o_m_valid_d;
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reg [31:0] o_m_writedata_d[`DCACHE_BANKS - 1:0][`DCACHE_NUM_WORDS_PER_BLOCK-1:0];
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reg o_m_read_or_write_d;
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// Rsp
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reg [31:0] i_m_readdata[`DCACHE_BANKS - 1:0][`DCACHE_NUM_WORDS_PER_BLOCK -1:0];
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reg i_m_ready;
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reg out_ebreak;
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// Rsp
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reg [31:0] i_m_readdata_d[`DCACHE_BANKS - 1:0][`DCACHE_NUM_WORDS_PER_BLOCK-1:0];
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reg i_m_ready_d;
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// Req
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reg [31:0] o_m_read_addr_i;
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reg [31:0] o_m_evict_addr_i;
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reg o_m_valid_i;
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reg [31:0] o_m_writedata_i[`ICACHE_BANKS - 1:0][`ICACHE_NUM_WORDS_PER_BLOCK-1:0];
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reg o_m_read_or_write_i;
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// Rsp
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reg [31:0] i_m_readdata_i[`ICACHE_BANKS - 1:0][`ICACHE_NUM_WORDS_PER_BLOCK-1:0];
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reg i_m_ready_i;
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reg out_ebreak;
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reg[31:0] hi;
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@ -73,25 +98,32 @@ module vortex_tb (
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end
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Vortex vortex(
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.clk (clk),
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.reset (reset),
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.icache_response_instruction(icache_response_instruction),
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.icache_request_pc_address (icache_request_pc_address),
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.io_valid (io_valid),
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.io_data (io_data),
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.o_m_read_addr (o_m_read_addr),
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.o_m_evict_addr (o_m_evict_addr),
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.o_m_valid (o_m_valid),
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.o_m_writedata (o_m_writedata),
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.o_m_read_or_write (o_m_read_or_write),
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.i_m_readdata (i_m_readdata),
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.i_m_ready (i_m_ready),
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.out_ebreak (out_ebreak)
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.clk (clk),
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.reset (reset),
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.icache_response_instruction (icache_response_instruction),
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.icache_request_pc_address (icache_request_pc_address),
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.io_valid (io_valid),
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.io_data (io_data),
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.o_m_read_addr_d (o_m_read_addr_d),
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.o_m_evict_addr_d (o_m_evict_addr_d),
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.o_m_valid_d (o_m_valid_d),
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.o_m_writedata_d (o_m_writedata_d),
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.o_m_read_or_write_d (o_m_read_or_write_d),
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.i_m_readdata_d (i_m_readdata_d),
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.i_m_ready_d (i_m_ready_d),
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.o_m_read_addr_i (o_m_read_addr_i),
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.o_m_evict_addr_i (o_m_evict_addr_i),
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.o_m_valid_i (o_m_valid_i),
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.o_m_writedata_i (o_m_writedata_i),
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.o_m_read_or_write_i (o_m_read_or_write_i),
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.i_m_readdata_i (i_m_readdata_i),
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.i_m_ready_i (i_m_ready_i),
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.out_ebreak (out_ebreak)
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);
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always @(negedge clk) begin
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ibus_driver(clk, icache_request_pc_address, icache_response_instruction);
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dbus_driver(clk, o_m_read_addr, o_m_evict_addr, o_m_valid, o_m_writedata, o_m_read_or_write, `DCACHE_BANKS, `DCACHE_NUM_WORDS_PER_BLOCK, i_m_readdata, i_m_ready);
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ibus_driver(clk, o_m_read_addr_i, o_m_evict_addr_i, o_m_valid_i, o_m_writedata_i, o_m_read_or_write_i, `ICACHE_BANKS, `ICACHE_NUM_WORDS_PER_BLOCK, i_m_readdata_i, i_m_ready_i);
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dbus_driver(clk, o_m_read_addr_d, o_m_evict_addr_d, o_m_valid_d, o_m_writedata_d, o_m_read_or_write_d, `DCACHE_BANKS, `DCACHE_NUM_WORDS_PER_BLOCK, i_m_readdata_d, i_m_ready_d);
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io_handler (clk, io_valid, io_data);
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end
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