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FIxed first circular issue
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felsabbagh3
parent
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19 changed files with 2302 additions and 2799 deletions
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:10097000032704FD23A6E700EFF01F882324A4FE2D
|
||||
:10098000032704FD832784FEB357F7022326F4FED2
|
||||
:10099000032704FD832784FEB377F70263880700EB
|
||||
:1009A0008327C4FE938717002326F4FEB7670281CE
|
||||
:1009B0009387871B0327C4FE23A8E700032704FDB2
|
||||
:1009C000832784FE6362F702B76702819386871BE1
|
||||
:1009D000B7170080138607A4832584FE032504FD32
|
||||
:1009E000EFF01FA96F000002B76702819386871B93
|
||||
:1009F000B7170080138607A4832504FD032504FD93
|
||||
:100A0000EFF01FA7EFF0CFFE2322A4FE032704FD83
|
||||
:100A1000832744FE63F8E700032544FEEFF05FB44C
|
||||
:100A20006F00C000032504FDEFF09FB3130000002A
|
||||
:100A30008320C102032481021301010367800000A7
|
||||
:100A4000130101FA232E1104232C8104130401063F
|
||||
:100A50002326A4FA2324B4FAEFF09FBF232CA4FC8E
|
||||
:100A6000832784FD83A70700232AF4FC832784FDC2
|
||||
:100A700083A747002328F4FC832784FD83A78700EE
|
||||
:100A80002326F4FC832784FD83A707012326F4FE95
|
||||
:100A90000327C4FE8327C4FAB307F7022324F4FE16
|
||||
:100AA0008327C4FE639A0700930710002326F4FEF1
|
||||
:100AB0008327C4FA2324F4FE832784FD83A7C70079
|
||||
:100AC0002324F4FC232204FE6F00800D232004FE67
|
||||
:100AD000232E04FC6F008007032784FA832784FCFD
|
||||
:100AE000B307F7020327C4FDB307F7002322F4FC82
|
||||
:100AF000032784FC8327C4FDB307F702032784FE82
|
||||
:100B0000B307F7002320F4FC832744FC93972700C6
|
||||
:100B1000032744FDB307F70003A70700832704FC5E
|
||||
:100B200093972700832604FDB387F60083A7070069
|
||||
:100B3000B307F702032704FEB307F7002320F4FEF0
|
||||
:100B40008327C4FD93871700232EF4FC0327C4FDDD
|
||||
:100B5000832784FCE362F7F8032784FA832784FC65
|
||||
:100B60003307F702832784FEB307F700232EF4FA36
|
||||
:100B70008327C4FB939727000327C4FCB307F70020
|
||||
:100B8000032704FE23A0E700832784FE9387170032
|
||||
:100B90002324F4FE832744FE938717002322F4FEC8
|
||||
:100BA000832744FE0327C4FEE3E2E7F213000000BC
|
||||
:100BB0008320C1050324810513010106678000001D
|
||||
:100BC000130101FC232E1102232C810213040104C2
|
||||
:100BD000232EA4FC232CB4FC232AC4FC2328D4FCFD
|
||||
:100BE0002326E4FCB76702810327C4FD23A6E71C84
|
||||
:100BF000B76702819387C71C032784FD23A2E70000
|
||||
:100C0000B76702819387C71C032744FD23A4E7002D
|
||||
:100C1000B76702819387C71C0327C4FC23A6E7009C
|
||||
:100C2000B76702819387C71C032704FD23A8E70049
|
||||
:100C3000EFF08FDC2324A4FE0327C4FC832784FE6B
|
||||
:100C4000B357F7022326F4FE0327C4FC832784FE50
|
||||
:100C5000B377F702638807008327C4FE93871700E2
|
||||
:100C60002326F4FEB76702819387C71C0327C4FEBF
|
||||
:100C700023AAE7000327C4FC832784FE6362F702EC
|
||||
:100C8000B76702819386C71CB7170080138687CF8A
|
||||
:100C9000832584FE032504FDEFF08FFD6F00000225
|
||||
:100CA000B76702819386C71CB7170080138687CF6A
|
||||
:100CB0008325C4FC032504FDEFF08FFBEFF04FD339
|
||||
:100CC0002322A4FE032704FD832744FE63F8E700E4
|
||||
:100CD000032544FEEFF0DF886F00C000032504FD0C
|
||||
:100CE000EFF01F88130000008320C1030324810359
|
||||
:100CF0001301010467800000130101FB2326110486
|
||||
:100D00002324810413040105232EA4FA232CB4FA0E
|
||||
:100D1000EFF01F942320A4FE832704FE83A707007F
|
||||
:100D2000232EF4FC832704FE83A74700232CF4FC26
|
||||
:100D3000832704FE83A78700232AF4FC832704FE6D
|
||||
:100D400083A747012326F4FE0327C4FE8327C4FBA1
|
||||
:100D5000B307F7022324F4FE8327C4FE639A070037
|
||||
:100D6000930710002326F4FE8327C4FB2324F4FEFC
|
||||
:100D7000832704FE83A7C7002328F4FC232204FE54
|
||||
:100D80006F00000C032784FB832704FD3307F70261
|
||||
:100D9000832784FEB307F7002326F4FC032784FE91
|
||||
:100DA000832704FDB337F70093F7F70F2324F4FCF0
|
||||
:100DB000832784FC93B71700A303F4FC834774FCD8
|
||||
:100DC000138F0700B7170080938FC7E26B200F00C7
|
||||
:100DD0007B70FF018327C4FC939727000327C4FD82
|
||||
:100DE000B307F70083A607008327C4FC9397270067
|
||||
:100DF000032784FDB307F70003A707008327C4FC7C
|
||||
:100E000093972700032644FDB307F6003387E600D7
|
||||
:100E100023A0E700832784FE938717002324F4FE92
|
||||
:100E2000B7170080138E07E367000E001300000061
|
||||
:100E30006B300000832744FE938717002322F4FEC3
|
||||
:100E4000832744FE0327C4FEE3EEE7F2130000000D
|
||||
:100E50008320C1040324810413010105678000007D
|
||||
:100E6000130101FC232E1102232C8102130401041F
|
||||
:100E7000232EA4FC232CB4FC232AC4FC2328D4FC5A
|
||||
:100E80002326E4FCB76702810327C4FD23A6E71CE1
|
||||
:100E9000B76702819387C71C032784FD23A2E7005D
|
||||
:100EA000B76702819387C71C032744FD23A4E7008B
|
||||
:100EB000B76702819387C71C0327C4FC23A6E700FA
|
||||
:100EC000B76702819387C71C032704FD23A8E700A7
|
||||
:100ED000EFF08FB22324A4FE0327C4FC832784FEF3
|
||||
:100EE000B357F7022326F4FE0327C4FC832784FEAE
|
||||
:100EF000B377F702638807008327C4FE9387170040
|
||||
:100F00002326F4FEB76702819387C71C0327C4FE1C
|
||||
:100F100023AAE7000327C4FC832784FE6362F70249
|
||||
:100F2000B76702819386C71CB7170080138687F9BD
|
||||
:100F3000832584FE032504FDEFF08FD36F000002AC
|
||||
:100F4000B76702819386C71CB7170080138687F99D
|
||||
:100F50008325C4FC032504FDEFF08FD1EFF04FA9EA
|
||||
:100F60002322A4FE032704FD832744FE63F8E70041
|
||||
:100F7000032544FEEFF0CFDE6F00C000032504FD23
|
||||
:100F8000EFF00FDE130000008320C1030324810370
|
||||
:100F90001301010467800000130101FB23261104E3
|
||||
:100FA0002324810413040105232EA4FA232CB4FA6C
|
||||
:100FB000EFF00FEA2320A4FE832704FE83A7070097
|
||||
:100FC000232EF4FC832704FE83A74700232CF4FC84
|
||||
:100FD000832704FE83A78700232AF4FC832704FECB
|
||||
:100FE00083A747012326F4FE0327C4FE8327C4FBFF
|
||||
:100FF000B307F7022324F4FE8327C4FE639A070095
|
||||
:10100000930710002326F4FE8327C4FB2324F4FE59
|
||||
:10101000832704FE83A7C7002328F4FC232204FEB1
|
||||
:101020006F00000C032784FB832704FD3307F702BE
|
||||
:10103000832784FEB307F7002326F4FC032784FEEE
|
||||
:10104000832704FDB337F70093F7F70F2324F4FC4D
|
||||
:10105000832784FC93B71700A303F4FC834774FC35
|
||||
:10106000138F0700B7170080938FC70C6B200F00FA
|
||||
:101070007B70FF018327C4FC939727000327C4FDDF
|
||||
:10108000B307F70083A607008327C4FC93972700C4
|
||||
:10109000032784FDB307F70003A707008327C4FCD9
|
||||
:1010A00093972700032644FDB307F6003387E640F5
|
||||
:1010B00023A0E700832784FE938717002324F4FEF0
|
||||
:1010C000B7170080138E070D67000E001300000095
|
||||
:1010D0006B300000832744FE938717002322F4FE21
|
||||
:1010E000832744FE0327C4FEE3EEE7F2130000006B
|
||||
:1010F0008320C104032481041301010567800000DB
|
||||
:10110000130101FC232E1102232C8102130401047C
|
||||
:10111000232EA4FC232CB4FC232AC4FC2328D4FCB7
|
||||
:101120002326E4FCB76702810327C4FD23A2E71E40
|
||||
:10113000B76702819387471E032784FD23A2E70038
|
||||
:10114000B76702819387471E032744FD23A4E70066
|
||||
:10115000B76702819387471E0327C4FC23A6E700D5
|
||||
:10116000B76702819387471E032704FD23A8E70082
|
||||
:10117000EFF08F882324A4FE0327C4FC832784FE7A
|
||||
:10118000B357F7022326F4FE0327C4FC832784FE0B
|
||||
:10119000B377F702638807008327C4FE938717009D
|
||||
:1011A0002326F4FEB76702819387471E0327C4FEF8
|
||||
:1011B00023AAE7000327C4FC832784FE6362F702A7
|
||||
:1011C000B76702819386471EB7170080138687236F
|
||||
:1011D000832584FE032504FDEFF08FA96F00000234
|
||||
:1011E000B76702819386471EB7170080138687234F
|
||||
:1011F0008325C4FC032504FDEFF08FA7EFE05FFF1C
|
||||
:101200002322A4FE032704FD832744FE63F8E7009E
|
||||
:10121000032544FEEFF0CFB46F00C000032504FDAA
|
||||
:10122000EFF00FB4130000008320C10303248103F7
|
||||
:101230001301010467800000130101FB2326110440
|
||||
:101240002324810413040105232EA4FA232CB4FAC9
|
||||
:10125000EFF00FC02320A4FE832704FE83A707001E
|
||||
:10126000232EF4FC832704FE83A7470083A70700EF
|
||||
:10127000232CF4FC832704FE83A78700232AF4FC95
|
||||
:10128000832704FE83A747012326F4FE0327C4FE19
|
||||
:101290008327C4FBB307F7022324F4FE8327C4FE8D
|
||||
:1012A000639A0700930710002326F4FE8327C4FBEC
|
||||
:1012B0002324F4FE832704FE83A7C7002328F4FC1D
|
||||
:1012C000232204FE6F00000B032784FB832704FD09
|
||||
:1012D0003307F702832784FEB307F7002326F4FCC5
|
||||
:1012E000032784FE832704FDB337F70093F7F70F36
|
||||
:1012F0002324F4FC832784FC93B71700A303F4FC96
|
||||
:10130000834774FC138F0700B7170080938F07364D
|
||||
:101310006B200F007B70FF018327C4FC939727008D
|
||||
:101320000327C4FDB307F70083A607008327C4FC87
|
||||
:1013300093972700032744FDB307F700032784FD95
|
||||
:101340003387E60023A0E700832784FE93871700F6
|
||||
:101350002324F4FEB7170080138E473667000E0073
|
||||
:10136000130000006B300000832744FE93871700B2
|
||||
:101370002322F4FE832744FE0327C4FEE3E6E7F4BA
|
||||
:10138000130000008320C10403248104130101051C
|
||||
:1013900067800000130101FC232E1102232C81021F
|
||||
:1013A00013040104232EA4FC232CB4FC232AC4FC24
|
||||
:1013B0002328D4FC2326E4FCB76702810327C4FD5D
|
||||
:1013C00023A2E71EB76702819387471E032784FD88
|
||||
:1013D00023A2E700B76702819387471E032744FDD6
|
||||
:1013E00023A4E700B76702819387471E0327C4FC45
|
||||
:1013F00023A6E700B76702819387471E032704FDF2
|
||||
:1014000023A8E700EFE05FDF2324A4FE0327C4FC4A
|
||||
:10141000832784FEB357F7022326F4FE0327C4FC78
|
||||
:10142000832784FEB377F702638807008327C4FE0F
|
||||
:10143000938717002326F4FEB76702819387471E20
|
||||
:101440000327C4FE23AAE7000327C4FC832784FEE6
|
||||
:101450006362F702B76702819386471EB717008061
|
||||
:101460001386C74C832584FE032504FDEFF04F80CF
|
||||
:101470006F000002B76702819386471EB71700808E
|
||||
:101480001386C74C8325C4FC032504FDEFE05FFEF3
|
||||
:10149000EFE01FD62322A4FE032704FD832744FE8A
|
||||
:1014A00063F8E700032544FEEFF08F8B6F00C00068
|
||||
:1014B000032504FDEFF0CF8A130000008320C10351
|
||||
:1014C000032481031301010467800000130101FB61
|
||||
:1014D000232611042324810413040105232EA4FAD6
|
||||
:1014E000232CB4FAEFF0CF962320A4FE832704FE2A
|
||||
:1014F00083A70700232EF4FC832704FE83A747005D
|
||||
:1015000083A70700232CF4FC832704FE83A787000E
|
||||
:10151000232AF4FC832704FE83A747012326F4FE35
|
||||
:101520000327C4FE8327C4FBB307F7022324F4FE7A
|
||||
:101530008327C4FE639A0700930710002326F4FE56
|
||||
:101540008327C4FB2324F4FE832704FE83A7C7005C
|
||||
:101550002328F4FC232204FE6F00000B032784FBE6
|
||||
:10156000832704FD3307F702832784FEB307F700C0
|
||||
:101570002326F4FC032784FE832704FDB337F700FA
|
||||
:1015800093F7F70F2324F4FC832784FC93B7170009
|
||||
:10159000A303F4FC834774FC138F0700B717008084
|
||||
:1015A000938F475F6B200F007B70FF018327C4FC84
|
||||
:1015B000939727000327C4FDB307F70083A607000E
|
||||
:1015C0008327C4FC93972700032744FDB307F70044
|
||||
:1015D000032784FD3387E60223A0E700832784FEE8
|
||||
:1015E000938717002324F4FEB7170080138E875FBC
|
||||
:1015F00067000E00130000006B300000832744FEDC
|
||||
:10160000938717002322F4FE832744FE0327C4FE9A
|
||||
:10161000E3E6E7F4130000008320C10403248104FF
|
||||
:101620001301010567800000130101FD23268102DB
|
||||
:1016300013040103232EA4FC232604FE6F000001E3
|
||||
:101640008327C4FE938717002326F4FE0327C4FED6
|
||||
:101650008327C4FDE346F7FE130000000324C10204
|
||||
:101660001301010367800000130101FD232611020D
|
||||
:101670002324810213040103232EA4FC232CB4FC95
|
||||
:10168000B76702811387C71F8327C4FDB307F7001D
|
||||
:10169000130710002380E7008327C4FD6390070C25
|
||||
:1016A000A30104FE232604FE6F00800A232604FE05
|
||||
:1016B000232404FE6F004003B76702811387C71F0E
|
||||
:1016C000832784FEB307F70083C7070063880700FA
|
||||
:1016D0008327C4FE938717002326F4FE832784FE06
|
||||
:1016E000938717002324F4FE032784FE832784FDB9
|
||||
:1016F000E344F7FC0327C4FE832784FD631AF70441
|
||||
:10170000232204FE6F000004B76702811387C71FFE
|
||||
:10171000832744FEB307F70023800700B7970281B1
|
||||
:10172000130710002382E72C13056004EFF0DFEFAE
|
||||
:10173000B79702812382072C832744FE93871700E3
|
||||
:101740002322F4FE032744FE832784FDE34EF7FAA9
|
||||
:10175000834734FEE39C07F46F004002130000004F
|
||||
:10176000B797028183C7472C93C7170093F7F70FEA
|
||||
:10177000E39807FE13054006EFF01FEB130000008F
|
||||
:101780008320C1020324810213010103678000004A
|
||||
:10179000130101FF232681001304010193070000B8
|
||||
:1017A0001308000013850700930508000324C100F7
|
||||
:1017B0001301010167800000130101FE232E810047
|
||||
:1017C00013040102232604FE6F008004B767028120
|
||||
:1017D0000327C4FE131727009387C721B307F70019
|
||||
:1017E0001307300023A0E700B77702810327C4FE68
|
||||
:1017F000131727009387C721B307F70013072000AB
|
||||
:1018000023A0E7008327C4FE938717002326F4FE56
|
||||
:101810000327C4FE9307F00FE3DAE7FA1300000092
|
||||
:101820000324C1011301010267800000130101FDBF
|
||||
:10183000232611022324810213040103232EA4FC76
|
||||
:10184000B707008113858711EFE0DFF8232604FE38
|
||||
:101850006F0080058327C4FE638E07008327C4FEC4
|
||||
:1018600093F7F70063980700B70700811385C71344
|
||||
:10187000EFE05FF68327C4FE939727000327C4FD9C
|
||||
:10188000B307F70083A7070013850700EFE05FF8B1
|
||||
:10189000B707008113850714EFE0DFF38327C4FE49
|
||||
:1018A000938717002326F4FE0327C4FE9307F00F47
|
||||
:1018B000E3D2E7FAB707008113854714EFE09FF101
|
||||
:1018C000130000008320C1020324810213010103DD
|
||||
:1018D00067800000130101FF2326110023248100EB
|
||||
:1018E00013040101EFF05FEDB76702811385C72193
|
||||
:1018F000EFF0DFF393070000138507008320C1009A
|
||||
:0C19000003248100130101016780000036
|
||||
:02000004810079
|
||||
:10000000300000003100000032000000330000002A
|
||||
:10001000340000003500000036000000370000000A
|
||||
|
|
|
|||
|
|
@ -6,7 +6,7 @@
|
|||
.type _start, @function
|
||||
.global _start
|
||||
_start:
|
||||
la a0, 0xFF003300
|
||||
la a0, 0x020000
|
||||
li a1, 7
|
||||
sw a1, 4(a0)
|
||||
nop
|
||||
|
|
|
|||
12
rtl/Makefile
12
rtl/Makefile
|
|
@ -11,18 +11,20 @@ EXE=--exe ./simulate/test_bench.cpp
|
|||
|
||||
COMP=--compiler gcc
|
||||
|
||||
WNO=-Wno-UNOPTFLAT -Wno-UNDRIVEN --Wno-PINMISSING -Wno-STMTDLY -Wno-WIDTH -Wno-UNSIGNED
|
||||
# WNO=-Wno-UNDRIVEN --Wno-PINMISSING -Wno-STMTDLY -Wno-WIDTH -Wno-UNSIGNED
|
||||
WNO=
|
||||
|
||||
LIGHTW=-Wno-UNOPTFLAT
|
||||
LIGHTW=
|
||||
# LIGHTW=-Wno-UNOPTFLAT
|
||||
# LIB=-LDFLAGS '-L/usr/local/systemc/'
|
||||
LIB=
|
||||
|
||||
CF=-CFLAGS '-std=c++11 -O3'
|
||||
|
||||
DEB=--prof-cfuncs -DVL_DEBUG=1 --coverage --trace
|
||||
DEB=--trace --prof-cfuncs -DVL_DEBUG=1
|
||||
|
||||
|
||||
MAKECPP=(cd obj_dir && make -j -f VVortex.mk)
|
||||
MAKECPP=(cd obj_dir && make -j -f VVortex.mk OPT='-DVL_DEBUG' VL_DEBUG=1 DVL_DEBUG=1)
|
||||
|
||||
# -LDFLAGS '-lsystemc'
|
||||
VERILATOR:
|
||||
|
|
@ -35,7 +37,7 @@ VERILATORnoWarnings:
|
|||
|
||||
compdebug:
|
||||
echo "#define VCD_OUTPUT" > simulate/tb_debug.h
|
||||
verilator $(COMP) -cc $(FILE) $(INCLUDE) $(EXE) $(LIB) -CFLAGS '-std=c++11 -DVL_DEBUG' $(WNO) $(DEB)
|
||||
verilator_bin_dbg $(COMP) -cc $(FILE) $(INCLUDE) $(EXE) $(LIB) -CFLAGS '-std=c++11 -DVL_DEBUG' $(WNO) $(DEB)
|
||||
|
||||
RUNFILE: VERILATOR
|
||||
$(MAKECPP)
|
||||
|
|
|
|||
|
|
@ -72,7 +72,8 @@ VX_gpr_stage VX_gpr_stage(
|
|||
|
||||
|
||||
VX_lsu load_store_unit(
|
||||
// .clk (clk),
|
||||
.clk (clk),
|
||||
.reset (reset),
|
||||
.VX_lsu_req (VX_lsu_req),
|
||||
.VX_mem_wb (VX_mem_wb),
|
||||
.VX_dcache_rsp(VX_dcache_rsp),
|
||||
|
|
|
|||
|
|
@ -11,6 +11,7 @@
|
|||
|
||||
// `define SYN 1
|
||||
|
||||
`define CACHE_NUM_BANKS 8
|
||||
|
||||
`define NUMBER_BANKS 8
|
||||
`define NUM_WORDS_PER_BLOCK 4
|
||||
|
|
|
|||
|
|
@ -17,9 +17,7 @@ module VX_dmem_controller (
|
|||
wire[`NT_M1:0] sm_driver_in_valid = VX_dcache_req.out_cache_driver_in_valid & {`NT{to_shm}};
|
||||
wire[`NT_M1:0] cache_driver_in_valid = VX_dcache_req.out_cache_driver_in_valid & {`NT{~to_shm}};
|
||||
|
||||
// Cache don't understand
|
||||
wire initial_request = (|cache_driver_in_valid);
|
||||
wire read_or_write = (VX_dcache_req.out_cache_driver_in_mem_write != `NO_MEM_WRITE);
|
||||
wire read_or_write = (VX_dcache_req.out_cache_driver_in_mem_write != `NO_MEM_WRITE) && (|cache_driver_in_valid);
|
||||
|
||||
|
||||
|
||||
|
|
@ -58,7 +56,8 @@ module VX_dmem_controller (
|
|||
.i_p_read_or_write (read_or_write),
|
||||
.o_p_readdata (cache_driver_out_data),
|
||||
.o_p_delay (cache_delay),
|
||||
.o_m_addr (VX_dram_req_rsp.o_m_addr),
|
||||
.o_m_evict_addr (VX_dram_req_rsp.o_m_evict_addr),
|
||||
.o_m_read_addr (VX_dram_req_rsp.o_m_read_addr),
|
||||
.o_m_valid (VX_dram_req_rsp.o_m_valid),
|
||||
.o_m_writedata (VX_dram_req_rsp.o_m_writedata),
|
||||
.o_m_read_or_write (VX_dram_req_rsp.o_m_read_or_write),
|
||||
|
|
@ -68,8 +67,7 @@ module VX_dmem_controller (
|
|||
|
||||
|
||||
assign VX_dcache_rsp.in_cache_driver_out_data = to_shm ? sm_driver_out_data : cache_driver_out_data;
|
||||
// assign VX_dcache_rsp.delay = sm_delay;
|
||||
assign VX_dcache_rsp.delay = sm_delay || (!cache_delay);
|
||||
assign VX_dcache_rsp.delay = sm_delay || cache_delay;
|
||||
|
||||
|
||||
endmodule
|
||||
|
|
@ -25,10 +25,6 @@ VX_inst_meta_inter fe_inst_meta_fd();
|
|||
VX_frE_to_bckE_req_inter VX_frE_to_bckE_req();
|
||||
VX_inst_meta_inter fd_inst_meta_de();
|
||||
|
||||
// From decode
|
||||
wire decode_branch_stall;
|
||||
|
||||
|
||||
wire total_freeze = schedule_delay;
|
||||
|
||||
/* verilator lint_off UNUSED */
|
||||
|
|
|
|||
37
rtl/VX_lsu.v
37
rtl/VX_lsu.v
|
|
@ -3,7 +3,8 @@
|
|||
|
||||
|
||||
module VX_lsu (
|
||||
// input wire clk,
|
||||
input wire clk,
|
||||
input wire reset,
|
||||
VX_lsu_req_inter VX_lsu_req,
|
||||
|
||||
// Write back to GPR
|
||||
|
|
@ -14,7 +15,7 @@ module VX_lsu (
|
|||
output wire out_delay
|
||||
);
|
||||
|
||||
// VX_inst_mem_wb_inter VX_mem_wb_temp();
|
||||
VX_inst_mem_wb_inter VX_mem_wb_temp();
|
||||
|
||||
assign out_delay = VX_dcache_rsp.delay;
|
||||
|
||||
|
|
@ -33,32 +34,32 @@ module VX_lsu (
|
|||
for (index = 0; index <= `NT_M1; index = index + 1) begin
|
||||
assign VX_dcache_req.out_cache_driver_in_address[index] = address[index];
|
||||
assign VX_dcache_req.out_cache_driver_in_data[index] = VX_lsu_req.store_data[index];
|
||||
assign VX_dcache_req.out_cache_driver_in_valid[index] = (VX_lsu_req.valid[index] && !VX_dcache_rsp.delay);
|
||||
assign VX_dcache_req.out_cache_driver_in_valid[index] = (VX_lsu_req.valid[index]);
|
||||
|
||||
assign VX_mem_wb.loaded_data[index] = VX_dcache_rsp.in_cache_driver_out_data[index];
|
||||
assign VX_mem_wb_temp.loaded_data[index] = VX_dcache_rsp.in_cache_driver_out_data[index];
|
||||
end
|
||||
|
||||
assign VX_dcache_req.out_cache_driver_in_mem_read = VX_lsu_req.mem_read;
|
||||
assign VX_dcache_req.out_cache_driver_in_mem_write = VX_lsu_req.mem_write;
|
||||
|
||||
|
||||
assign VX_mem_wb.rd = VX_lsu_req.rd;
|
||||
assign VX_mem_wb.wb = VX_lsu_req.wb;
|
||||
assign VX_mem_wb.wb_valid = VX_lsu_req.valid;
|
||||
assign VX_mem_wb.wb_warp_num = VX_lsu_req.warp_num;
|
||||
assign VX_mem_wb_temp.rd = VX_lsu_req.rd;
|
||||
assign VX_mem_wb_temp.wb = VX_lsu_req.wb;
|
||||
assign VX_mem_wb_temp.wb_valid = VX_lsu_req.valid;
|
||||
assign VX_mem_wb_temp.wb_warp_num = VX_lsu_req.warp_num;
|
||||
|
||||
|
||||
|
||||
// wire zero_temp = 0;
|
||||
// VX_generic_register #(.N(256)) register_wb_data
|
||||
// (
|
||||
// .clk (clk),
|
||||
// .reset(zero_temp),
|
||||
// .stall(zero_temp),
|
||||
// .flush(zero_temp),
|
||||
// .in ({VX_mem_wb_temp.loaded_data, VX_mem_wb_temp.rd, VX_mem_wb_temp.wb, VX_mem_wb_temp.wb_valid, VX_mem_wb_temp.wb_warp_num}),
|
||||
// .out ({VX_mem_wb.loaded_data , VX_mem_wb.rd , VX_mem_wb.wb , VX_mem_wb.wb_valid , VX_mem_wb.wb_warp_num })
|
||||
// );
|
||||
wire zero_temp = 0;
|
||||
VX_generic_register #(.N(142)) register_wb_data
|
||||
(
|
||||
.clk (clk),
|
||||
.reset(reset),
|
||||
.stall(zero_temp),
|
||||
.flush(out_delay),
|
||||
.in ({VX_mem_wb_temp.loaded_data, VX_mem_wb_temp.rd, VX_mem_wb_temp.wb, VX_mem_wb_temp.wb_valid, VX_mem_wb_temp.wb_warp_num}),
|
||||
.out ({VX_mem_wb.loaded_data , VX_mem_wb.rd , VX_mem_wb.wb , VX_mem_wb.wb_valid , VX_mem_wb.wb_warp_num })
|
||||
);
|
||||
|
||||
|
||||
endmodule // Memory
|
||||
|
|
|
|||
|
|
@ -10,16 +10,15 @@ module VX_priority_encoder_w_mask
|
|||
);
|
||||
|
||||
integer i;
|
||||
always @(*) begin
|
||||
always @(valids) begin
|
||||
index = 0;
|
||||
found = 0;
|
||||
mask = 0;
|
||||
for (i = 0; i < N; i=i+1)
|
||||
begin
|
||||
if (!found && valids[i]) begin
|
||||
for (i = 0; i < N; i=i+1) begin
|
||||
if (valids[i]) begin
|
||||
index = i[$clog2(N)-1:0];
|
||||
found = 1;
|
||||
mask[i[$clog2(N)-1:0]] = 1;
|
||||
mask[i[$clog2(N)-1:0]] = 1 << i;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
|
|
|||
32
rtl/Vortex.v
32
rtl/Vortex.v
|
|
@ -8,7 +8,8 @@ module Vortex(
|
|||
input wire[31:0] icache_response_instruction,
|
||||
output wire[31:0] icache_request_pc_address,
|
||||
// Req
|
||||
output reg [31:0] o_m_addr,
|
||||
output reg [31:0] o_m_read_addr,
|
||||
output reg [31:0] o_m_evict_addr,
|
||||
output reg o_m_valid,
|
||||
output reg [31:0] o_m_writedata[`NUMBER_BANKS - 1:0][`NUM_WORDS_PER_BLOCK-1:0],
|
||||
output reg o_m_read_or_write,
|
||||
|
|
@ -16,32 +17,9 @@ module Vortex(
|
|||
// Rsp
|
||||
input wire [31:0] i_m_readdata[`NUMBER_BANKS - 1:0][`NUM_WORDS_PER_BLOCK-1:0],
|
||||
input wire i_m_ready,
|
||||
// Remove Start
|
||||
input wire[31:0] in_cache_driver_out_data[`NT_M1:0],
|
||||
output wire[31:0] out_cache_driver_in_address[`NT_M1:0],
|
||||
output wire[2:0] out_cache_driver_in_mem_read,
|
||||
output wire[2:0] out_cache_driver_in_mem_write,
|
||||
output wire out_cache_driver_in_valid[`NT_M1:0],
|
||||
output wire[31:0] out_cache_driver_in_data[`NT_M1:0],
|
||||
// Remove end
|
||||
output wire out_ebreak
|
||||
output wire out_ebreak
|
||||
);
|
||||
|
||||
// assign out_cache_driver_in_address = 0;
|
||||
assign out_cache_driver_in_mem_read = `NO_MEM_READ;
|
||||
assign out_cache_driver_in_mem_write = `NO_MEM_WRITE;
|
||||
// assign out_cache_driver_in_valid = 0;
|
||||
// assign out_cache_driver_in_data = 0;
|
||||
|
||||
// assign out_cache_driver_in_address = VX_dcache_req.out_cache_driver_in_address;
|
||||
// assign out_cache_driver_in_mem_read = VX_dcache_req.out_cache_driver_in_mem_read;
|
||||
// assign out_cache_driver_in_mem_write = VX_dcache_req.out_cache_driver_in_mem_write;
|
||||
// assign out_cache_driver_in_valid = VX_dcache_req.out_cache_driver_in_valid;
|
||||
// assign out_cache_driver_in_data = VX_dcache_req.out_cache_driver_in_data;
|
||||
|
||||
// assign VX_dcache_rsp.in_cache_driver_out_data = in_cache_driver_out_data;
|
||||
|
||||
|
||||
// Dcache Interface
|
||||
|
||||
VX_dcache_response_inter VX_dcache_rsp();
|
||||
|
|
@ -50,7 +28,8 @@ VX_dcache_request_inter VX_dcache_req();
|
|||
|
||||
VX_dram_req_rsp_inter VX_dram_req_rsp();
|
||||
|
||||
assign o_m_addr = VX_dram_req_rsp.o_m_addr;
|
||||
assign o_m_read_addr = VX_dram_req_rsp.o_m_read_addr;
|
||||
assign o_m_evict_addr = VX_dram_req_rsp.o_m_evict_addr;
|
||||
assign o_m_valid = VX_dram_req_rsp.o_m_valid;
|
||||
assign o_m_read_or_write = VX_dram_req_rsp.o_m_read_or_write;
|
||||
|
||||
|
|
@ -61,7 +40,6 @@ genvar curr_word;
|
|||
for (curr_bank = 0; curr_bank < `NUMBER_BANKS; curr_bank = curr_bank + 1) begin
|
||||
|
||||
for (curr_word = 0; curr_word < `NUM_WORDS_PER_BLOCK; curr_word = curr_word + 1) begin
|
||||
|
||||
assign o_m_writedata[curr_bank][curr_word] = VX_dram_req_rsp.o_m_writedata[curr_bank][curr_word];
|
||||
assign VX_dram_req_rsp.i_m_readdata[curr_bank][curr_word] = i_m_readdata[curr_bank][curr_word];
|
||||
|
||||
|
|
|
|||
3
rtl/cache/VX_Cache_Bank.v
vendored
3
rtl/cache/VX_Cache_Bank.v
vendored
|
|
@ -46,7 +46,7 @@ module VX_Cache_Bank
|
|||
// Inputs
|
||||
input wire clk;
|
||||
input wire [3:0] state;
|
||||
//input wire write_from_mem;
|
||||
//input wire write_from_mem;
|
||||
|
||||
// Reading Data
|
||||
input wire[$clog2(NUMBER_INDEXES)-1:0] actual_index;
|
||||
|
|
@ -118,7 +118,6 @@ module VX_Cache_Bank
|
|||
.evict (write_from_mem),
|
||||
.data_write(data_write),
|
||||
.tag_write (o_tag),
|
||||
|
||||
// Outputs
|
||||
.tag_use (tag_use),
|
||||
.data_use (data_use),
|
||||
|
|
|
|||
67
rtl/cache/VX_d_cache.v
vendored
67
rtl/cache/VX_d_cache.v
vendored
|
|
@ -10,7 +10,7 @@
|
|||
|
||||
`include "../VX_define.v"
|
||||
//`include "VX_priority_encoder.v"
|
||||
`include "VX_Cache_Bank.v"
|
||||
// `include "VX_Cache_Bank.v"
|
||||
//`include "cache_set.v"
|
||||
|
||||
|
||||
|
|
@ -102,7 +102,6 @@ module VX_d_cache(clk,
|
|||
|
||||
|
||||
|
||||
reg[`NT_M1:0] threads_serviced_Qual;
|
||||
|
||||
VX_cache_bank_valid #(.NUMBER_BANKS(NUMBER_BANKS)) multip_banks(
|
||||
.i_p_valid (use_valid),
|
||||
|
|
@ -111,38 +110,52 @@ module VX_d_cache(clk,
|
|||
);
|
||||
|
||||
|
||||
reg detect_bank_conflict;
|
||||
genvar bank_ind;
|
||||
for (bank_ind = 0; bank_ind < NUMBER_BANKS; bank_ind=bank_ind+1)
|
||||
begin
|
||||
assign detect_bank_conflict = detect_bank_conflict | ($countones(thread_track_banks[bank_ind]) > 1);
|
||||
|
||||
VX_priority_encoder_w_mask #(.N(`NT)) choose_thread(
|
||||
.valids(thread_track_banks[bank_ind]),
|
||||
.mask (use_mask_per_bank[bank_ind]),
|
||||
.index (index_per_bank[bank_ind]),
|
||||
.found (valid_per_bank[bank_ind])
|
||||
);
|
||||
reg[`NT_M1:0] threads_serviced_Qual;
|
||||
// reg detect_bank_conflict;
|
||||
// genvar bank_ind;
|
||||
// always @(*) begin
|
||||
// for (bank_ind = 0; bank_ind < NUMBER_BANKS; bank_ind=bank_ind+1)
|
||||
// begin
|
||||
// detect_bank_conflict = detect_bank_conflict | ($countones(thread_track_banks[bank_ind]) > 1);
|
||||
|
||||
////////////////
|
||||
|
||||
assign new_final_data_read[index_per_bank[bank_ind]] = hit_per_bank[bank_ind] ? readdata_per_bank[bank_ind] : 0;
|
||||
|
||||
assign threads_serviced_per_bank[bank_ind] = use_mask_per_bank[bank_ind] & {`NT{hit_per_bank[bank_ind]}};
|
||||
|
||||
end
|
||||
// end
|
||||
// end
|
||||
|
||||
genvar bid;
|
||||
for (bid = 0; bid < NUMBER_BANKS; bid=bid+1)
|
||||
begin
|
||||
assign threads_serviced_Qual = threads_serviced_Qual | threads_serviced_per_bank[bid];
|
||||
wire[`NT_M1:0] use_threads_track_banks = thread_track_banks[bid];
|
||||
VX_priority_encoder_w_mask #(.N(`NT)) choose_thread(
|
||||
.valids(use_threads_track_banks),
|
||||
.mask (use_mask_per_bank[bid]),
|
||||
.index (index_per_bank[bid]),
|
||||
.found (valid_per_bank[bid])
|
||||
);
|
||||
|
||||
assign new_final_data_read[index_per_bank[bid]] = hit_per_bank[bid] ? readdata_per_bank[bid] : 0;
|
||||
|
||||
assign threads_serviced_per_bank[bid] = use_mask_per_bank[bid] & {`NT{hit_per_bank[bid]}};
|
||||
end
|
||||
|
||||
|
||||
wire[NUMBER_BANKS - 1 : 0] detect_bank_miss = (valid_per_bank & ~hit_per_bank);
|
||||
// genvar tid;
|
||||
|
||||
assign threads_serviced_Qual = threads_serviced_per_bank[0] | threads_serviced_per_bank[1] | threads_serviced_per_bank[2] | threads_serviced_per_bank[3] | threads_serviced_per_bank[4] | threads_serviced_per_bank[5] | threads_serviced_per_bank[6] | threads_serviced_per_bank[7];
|
||||
// for(tid = 0; tid )
|
||||
wire[NUMBER_BANKS - 1 : 0] detect_bank_miss;
|
||||
// genvar bbid;
|
||||
// always @(*) begin
|
||||
// for (bbid = 0; bbid < NUMBER_BANKS; bbid=bbid+1)
|
||||
// begin
|
||||
// assign threads_serviced_Qual = threads_serviced_Qual | threads_serviced_per_bank[bbid];
|
||||
// end
|
||||
// end
|
||||
|
||||
|
||||
assign detect_bank_miss = (valid_per_bank & ~hit_per_bank);
|
||||
|
||||
wire delay;
|
||||
assign delay = (new_stored_valid != 0); // add other states
|
||||
assign delay = (new_stored_valid != 0) || (state != CACHE_IDLE); // add other states
|
||||
|
||||
assign o_p_delay = delay;
|
||||
|
||||
|
|
@ -173,7 +186,7 @@ module VX_d_cache(clk,
|
|||
always @(posedge clk) begin
|
||||
state <= new_state;
|
||||
|
||||
if (state == CACHE_IDLE) stored_valid <= new_stored_valid;
|
||||
stored_valid <= new_stored_valid;
|
||||
|
||||
if (miss_found) begin
|
||||
miss_addr <= i_p_addr[send_index_to_bank[miss_bank_index]];
|
||||
|
|
@ -220,10 +233,10 @@ module VX_d_cache(clk,
|
|||
.readdata (readdata_per_bank[bank_id]), // Data read
|
||||
.eviction_addr (eviction_addr_per_bank[bank_id]),
|
||||
.data_evicted (o_m_writedata[bank_id]),
|
||||
.eviction_wb (eviction_wb[bank_ind]), // Something needs to be written back
|
||||
.eviction_wb (eviction_wb[bank_id]), // Something needs to be written back
|
||||
|
||||
|
||||
.fetched_writedata(i_m_readdata[bank_ind]) // Data From memory
|
||||
.fetched_writedata(i_m_readdata[bank_id]) // Data From memory
|
||||
);
|
||||
|
||||
end
|
||||
|
|
|
|||
568
rtl/cache/VX_d_cache_old.v
vendored
568
rtl/cache/VX_d_cache_old.v
vendored
|
|
@ -1,568 +0,0 @@
|
|||
// Cache Memory (8way 4word) //
|
||||
// i_ means input port //
|
||||
// o_ means output port //
|
||||
// _p_ means data exchange with processor //
|
||||
// _m_ means data exchange with memory //
|
||||
|
||||
|
||||
// TO DO:
|
||||
// - Send in a response from memory of what the data is from the test bench
|
||||
|
||||
`include "VX_define.v"
|
||||
//`include "VX_priority_encoder.v"
|
||||
`include "VX_Cache_Bank.v"
|
||||
//`include "cache_set.v"
|
||||
|
||||
|
||||
module VX_d_cache(clk,
|
||||
rst,
|
||||
i_p_initial_request,
|
||||
i_p_addr,
|
||||
//i_p_byte_en,
|
||||
i_p_writedata,
|
||||
i_p_read_or_write, // 0 = Read | 1 = Write
|
||||
i_p_valid,
|
||||
//i_p_write,
|
||||
o_p_readdata,
|
||||
o_p_readdata_valid,
|
||||
o_p_waitrequest, // 0 = all threads done | 1 = Still threads that need to
|
||||
|
||||
o_m_addr,
|
||||
//o_m_byte_en,
|
||||
o_m_writedata,
|
||||
|
||||
o_m_read_or_write, // 0 = Read | 1 = Write
|
||||
o_m_valid,
|
||||
//o_m_write,
|
||||
i_m_readdata,
|
||||
|
||||
//i_m_readdata_ready,
|
||||
//i_m_waitrequest,
|
||||
i_m_ready
|
||||
|
||||
//cnt_r,
|
||||
//cnt_w,
|
||||
//cnt_hit_r,
|
||||
//cnt_hit_w
|
||||
//cnt_wb_r,
|
||||
//cnt_wb_w
|
||||
);
|
||||
|
||||
parameter NUMBER_BANKS = 8;
|
||||
|
||||
localparam CACHE_IDLE = 0; // Idle
|
||||
localparam SORT_BY_BANK = 1; // Determines the bank each thread will access
|
||||
localparam INITIAL_ACCESS = 2; // Accesses the bank and checks if it is a hit or miss
|
||||
localparam INITIAL_PROCESSING = 3; // Check to see if there were misses
|
||||
localparam CONTINUED_PROCESSING = 4; // Keep checking status of banks that need to be written back or fetched
|
||||
localparam DIRTY_EVICT_GRAB_BLOCK = 5; // Grab the full block of dirty data
|
||||
localparam DIRTY_EVICT_WB = 6; // Write back this block into memory
|
||||
localparam FETCH_FROM_MEM = 7; // Send a request to mem looking for read data
|
||||
localparam FETCH2 = 8; // Stall until memory gets back with the data
|
||||
localparam UPDATE_CACHE = 9; // Update the cache with the data read from mem
|
||||
localparam RE_ACCESS = 10; // Access the cache after the block has been fetched from memory
|
||||
localparam RE_ACCESS_PROCESSING = 11; // Access the cache after the block has been fetched from memory
|
||||
|
||||
|
||||
//parameter cache_entry = 9;
|
||||
input wire clk, rst;
|
||||
input wire [`NT_M1:0] i_p_valid;
|
||||
//input wire [`NT_M1:0][24:0] i_p_addr; // FIXME
|
||||
input wire [`NT_M1:0][31:0] i_p_addr; // FIXME
|
||||
input wire i_p_initial_request;
|
||||
//input wire [3:0] i_p_byte_en;
|
||||
input wire [`NT_M1:0][31:0] i_p_writedata;
|
||||
input wire i_p_read_or_write; //, i_p_write;
|
||||
output reg [`NT_M1:0][31:0] o_p_readdata;
|
||||
output reg [`NT_M1:0] o_p_readdata_valid;
|
||||
output wire o_p_waitrequest;
|
||||
//output reg [24:0] o_m_addr; // Only one address is sent out at a time to memory -- FIXME
|
||||
output reg [31:0] o_m_addr; // Address is xxxxxxxxxxoooobbbyy
|
||||
output reg o_m_valid;
|
||||
//output wire [255:0][31:0] evicted_data;
|
||||
//output wire [3:0] o_m_byte_en;
|
||||
//output reg [(NUMBER_BANKS * 32) - 1:0] o_m_writedata;
|
||||
output reg[NUMBER_BANKS - 1:0][`NUM_WORDS_PER_BLOCK-1:0][31:0] o_m_writedata;
|
||||
output reg o_m_read_or_write; //, o_m_write;
|
||||
//input wire [(NUMBER_BANKS * 32) - 1:0] i_m_readdata; // Read Data that is passed from the memory module back to the controller
|
||||
input wire[NUMBER_BANKS - 1:0][`NUM_WORDS_PER_BLOCK-1:0][31:0] i_m_readdata;
|
||||
//input wire i_m_readdata_ready;
|
||||
//input wire i_m_waitrequest;
|
||||
input wire i_m_ready;
|
||||
|
||||
//output reg [31:0] cnt_r;
|
||||
//output reg [31:0] cnt_w;
|
||||
//output reg [31:0] cnt_hit_r;
|
||||
//output reg [31:0] cnt_hit_w;
|
||||
//output reg [31:0] cnt_wb_r;
|
||||
//output reg [31:0] cnt_wb_w;
|
||||
|
||||
//wire [1:0] tag [`NT_M1:0];
|
||||
//wire [3:0] index [`NT_M1:0];
|
||||
//wire [2:0] bank [`NT_M1:0];
|
||||
//wire all_done;
|
||||
|
||||
//integer i;
|
||||
reg [`NT_M1:0] thread_done; // Maybe should have "thread_serviced" and "thread_done", serviced==checked cache
|
||||
//reg [`NT_M1:0] thread_serviced; // Maybe should have "thread_serviced" and "thread_done", serviced==checked cache
|
||||
reg [NUMBER_BANKS - 1:0] banks_ready;
|
||||
//reg [NUMBER_BANKS - 1:0] banks_missed;
|
||||
reg [NUMBER_BANKS - 1:0] banks_to_service;
|
||||
reg [NUMBER_BANKS - 1:0] banks_wb_needed;
|
||||
reg [NUMBER_BANKS - 1:0][31:0] banks_wb_addr;
|
||||
//reg [NUMBER_BANKS - 1:0] bank_states;
|
||||
//reg [NUMBER_BANKS - 1:0][31:0] banks_wb_data;
|
||||
//reg [NUMBER_BANKS - 1:0][13:0] banks_in_addr;
|
||||
|
||||
|
||||
reg [3:0] state;
|
||||
reg [NUMBER_BANKS - 1:0][31:0] data_from_bank;
|
||||
//reg got_valid_data;
|
||||
//reg [31:0] data_to_write;
|
||||
|
||||
|
||||
//reg [`NT_M1:0] thread_track_bank_0;
|
||||
//reg [`NT_M1:0] thread_track_bank_1;
|
||||
//reg [`NT_M1:0] thread_track_bank_2;
|
||||
//reg [`NT_M1:0] thread_track_bank_3;
|
||||
//reg [`NT_M1:0] thread_track_bank_4;
|
||||
//reg [`NT_M1:0] thread_track_bank_5;
|
||||
//reg [`NT_M1:0] thread_track_bank_6;
|
||||
//reg [`NT_M1:0] thread_track_bank_7;
|
||||
reg [NUMBER_BANKS - 1 : 0][`NT_M1:0] thread_track_banks;
|
||||
reg [NUMBER_BANKS - 1 : 0] bank_has_access; // Will track if a bank has been accessed in this cycle
|
||||
reg [NUMBER_BANKS - 1 : 0][31:0] bank_access_addr;
|
||||
reg [NUMBER_BANKS - 1 : 0][31:0] bank_access_data;
|
||||
reg [NUMBER_BANKS - 1 : 0][1:0] threads_in_banks;
|
||||
|
||||
|
||||
//reg [1:0] thread_in_memory; // keeps track of threadID which is in memory
|
||||
reg rd_or_wr;
|
||||
//reg did_miss, needs_service; Commented out Oct 21
|
||||
|
||||
integer bnk;
|
||||
integer found;
|
||||
integer t_id;
|
||||
//integer num_misses;
|
||||
//integer num_evictions_to_wb;
|
||||
integer i; //reg [1:0] correct_tag;
|
||||
integer index;
|
||||
//reg [3:0] correct_index;
|
||||
|
||||
//assign tag = i_p_addr[13:12];
|
||||
|
||||
assign o_p_waitrequest = (thread_done == 4'hF) ? 1'b0 : 1'b1; // change thread_done to be generic
|
||||
//assign did_miss = (banks_missed != 8'h0) ? 1'b1 : 1'b0;
|
||||
//assign needs_service = ((banks_to_service != 8'b0 || banks_to_service_temp != 8'b0)) ? 1'b1 : 1'b0; // added banks_to_service temp
|
||||
//assign w_Test1 = r_Check ? 1'b1 : 1'b0;
|
||||
//for ( i = 0;i < `NT_M1;i = i + 1) begin
|
||||
// assign tag[i] = i_p_addr[i][13:12];
|
||||
|
||||
// Fares
|
||||
// wire no_bank_misses;
|
||||
// assign no_bank_misses = banks_to_service != 8'b0;
|
||||
|
||||
reg[NUMBER_BANKS - 1:0] banks_to_service_temp;
|
||||
reg[NUMBER_BANKS - 1:0] banks_to_wb;
|
||||
reg[NUMBER_BANKS - 1:0] banks_to_wb_temp;
|
||||
reg[NUMBER_BANKS - 1:0] banks_all_help;
|
||||
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
state <= CACHE_IDLE;
|
||||
//banks_ready <= 8'b0;
|
||||
//cnt_r <= 0;
|
||||
//cnt_w <= 0;
|
||||
//cnt_hit_r <= 0;
|
||||
//cnt_hit_w <= 0;
|
||||
//cnt_wb_r <= 0;
|
||||
//cnt_wb_w <= 0;
|
||||
|
||||
end else begin
|
||||
// Change Logic of which state the cache is in
|
||||
case (state)
|
||||
CACHE_IDLE:begin
|
||||
if (i_p_initial_request == 1'b1) begin
|
||||
state <= SORT_BY_BANK;
|
||||
end
|
||||
end
|
||||
SORT_BY_BANK:begin
|
||||
state <= INITIAL_ACCESS;
|
||||
end
|
||||
INITIAL_ACCESS:begin
|
||||
if (thread_done == 4'hF) begin
|
||||
state <= CACHE_IDLE;
|
||||
end else begin
|
||||
state <= INITIAL_PROCESSING;
|
||||
end
|
||||
end
|
||||
INITIAL_PROCESSING:begin
|
||||
//if (bank_has_access == banks_ready ) begin // if all hits
|
||||
if (thread_done == 4'hF) begin
|
||||
state <= INITIAL_ACCESS;
|
||||
end else begin
|
||||
state <= CONTINUED_PROCESSING;
|
||||
end
|
||||
|
||||
end
|
||||
CONTINUED_PROCESSING:begin
|
||||
if (banks_to_wb == 8'b0 && banks_to_service == 8'b0) begin // If all threads are done, then the cache can go back into idle state (not currently fetching any requests)
|
||||
//if (banks_to_wb_temp == 8'b0 && banks_to_service_temp == 8'b0) begin
|
||||
state <= INITIAL_ACCESS;
|
||||
//end else if (num_misses > 0) begin
|
||||
end else if ((banks_to_wb != 8'b0)) begin // change 1pm
|
||||
//end else if ((banks_to_wb_temp != 8'b0)) begin // change 1pm
|
||||
state <= DIRTY_EVICT_GRAB_BLOCK;
|
||||
//end else if (did_miss == 1'b1 || needs_service == 1'b1) begin
|
||||
end else if(banks_to_service != 8'b0) begin
|
||||
//end else if(banks_to_service_temp != 8'b0) begin
|
||||
state <= FETCH_FROM_MEM;
|
||||
// end else if (did_miss == 1'b0 && num_evictions_to_wb > 0) begin
|
||||
//end else if (needs_service == 1'b0 && did_miss == 1'b0 && (banks_to_wb != 8'b0)) begin
|
||||
//end else if (did_miss == 1'b0 && needs_service == 1'b0) begin
|
||||
//state <= INITIAL_ACCESS;
|
||||
end
|
||||
end
|
||||
FETCH_FROM_MEM:begin
|
||||
state <= FETCH2;
|
||||
end
|
||||
FETCH2:begin
|
||||
if (i_m_ready == 1'b1) begin
|
||||
state <= UPDATE_CACHE; // Not sure about this one !!!!!! Check
|
||||
end else begin
|
||||
state <= FETCH2;
|
||||
end
|
||||
end
|
||||
UPDATE_CACHE:begin
|
||||
state <= RE_ACCESS;
|
||||
end
|
||||
RE_ACCESS:begin
|
||||
state <= CONTINUED_PROCESSING;
|
||||
end
|
||||
RE_ACCESS_PROCESSING: begin
|
||||
state <= CONTINUED_PROCESSING;
|
||||
end
|
||||
DIRTY_EVICT_GRAB_BLOCK:begin
|
||||
state <= DIRTY_EVICT_WB;
|
||||
end
|
||||
DIRTY_EVICT_WB:begin
|
||||
state <= CONTINUED_PROCESSING;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
//tag[`NT_M1:0] <= i_p_addr[`NT_M1:0][13:12];
|
||||
end
|
||||
|
||||
// Change values which will be fed into the cache
|
||||
always @(*) begin
|
||||
case (state)
|
||||
CACHE_IDLE:begin
|
||||
thread_done = 0;
|
||||
o_m_read_or_write = 0;
|
||||
o_m_valid = 0;
|
||||
o_m_writedata = 0;
|
||||
o_p_readdata = 0;
|
||||
o_p_readdata_valid = 0;
|
||||
bank_has_access = 8'b0;
|
||||
//bank_states = CACHE_IDLE;
|
||||
//thread_track_bank_0 = 4'b0;
|
||||
//thread_track_bank_1 = 4'b0;
|
||||
//thread_track_bank_2 = 4'b0;
|
||||
//thread_track_bank_3 = 4'b0;
|
||||
//thread_track_bank_4 = 4'b0;
|
||||
//thread_track_bank_5 = 4'b0;
|
||||
//thread_track_bank_6 = 4'b0;
|
||||
//thread_track_bank_7 = 4'b0;
|
||||
for (bnk = 0; bnk < NUMBER_BANKS; bnk = bnk + 1) begin
|
||||
thread_track_banks[bnk] = 4'b0;
|
||||
end
|
||||
end
|
||||
SORT_BY_BANK:begin
|
||||
//bank_states = SORT_BY_BANK;
|
||||
rd_or_wr = i_p_read_or_write;
|
||||
for (t_id = 0; t_id <= `NT_M1; t_id = t_id + 1) begin
|
||||
//t_id = {1'b0,t_id};
|
||||
if (i_p_valid[t_id] == 1'b0) begin
|
||||
thread_done[t_id] = 1'b1;
|
||||
end
|
||||
//if (i_p_valid[t_id] == 1'b1 && thread_done[t_id] == 1'b0) begin // Need logic for thread done
|
||||
else if (i_p_addr[t_id][4:2] == 3'b000) begin
|
||||
//banks_in_addr[0] = i_p_addr[t_id]; // WIll need to do this later
|
||||
//thread_track_bank_0[t_id] = 1'b1;
|
||||
thread_track_banks[0][t_id] = 1'b1;
|
||||
end
|
||||
else if (i_p_addr[t_id][4:2] == 3'b001) begin // !!!!!!!
|
||||
//banks_in_addr[0] = i_p_addr[t_id]; // WIll need to do this later
|
||||
//thread_track_bank_1[t_id] = 1'b1;
|
||||
thread_track_banks[1][t_id] = 1'b1;
|
||||
end
|
||||
else if (i_p_addr[t_id][4:2] == 3'b010) begin
|
||||
//banks_in_addr[0] = i_p_addr[t_id]; // WIll need to do this later
|
||||
//thread_track_bank_2[t_id] = 1'b1;
|
||||
thread_track_banks[2][t_id] = 1'b1;
|
||||
end
|
||||
else if (i_p_addr[t_id][4:2] == 3'b011) begin
|
||||
//banks_in_addr[0] = i_p_addr[t_id]; // WIll need to do this later
|
||||
//thread_track_bank_3[t_id] = 1'b1;
|
||||
thread_track_banks[3][t_id] = 1'b1;
|
||||
end
|
||||
else if (i_p_addr[t_id][4:2] == 3'b100) begin
|
||||
//banks_in_addr[0] = i_p_addr[t_id]; // WIll need to do this later
|
||||
//thread_track_bank_4[t_id] = 1'b1;
|
||||
thread_track_banks[4][t_id] = 1'b1;
|
||||
end
|
||||
else if (i_p_addr[t_id][4:2] == 3'b101) begin
|
||||
//banks_in_addr[0] = i_p_addr[t_id]; // WIll need to do this later
|
||||
//thread_track_bank_5[t_id] = 1'b1;
|
||||
thread_track_banks[5][t_id] = 1'b1;
|
||||
end
|
||||
else if (i_p_addr[t_id][4:2] == 3'b110) begin
|
||||
//banks_in_addr[0] = i_p_addr[t_id]; // WIll need to do this later
|
||||
//thread_track_bank_6[t_id] = 1'b1;
|
||||
thread_track_banks[6][t_id] = 1'b1;
|
||||
end
|
||||
else if (i_p_addr[t_id][4:2] == 3'b111) begin
|
||||
//banks_in_addr[0] = i_p_addr[t_id]; // WIll need to do this later
|
||||
//thread_track_bank_7[t_id] = 1'b1;
|
||||
thread_track_banks[7][t_id] = 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
INITIAL_ACCESS:begin
|
||||
//bank_states = INITIAL_ACCESS;
|
||||
o_m_valid = 1'b0;
|
||||
|
||||
// Before Access
|
||||
// if (no_bank_misses) begin
|
||||
// Dont do anything, next clock cycle it will switch back to (Fetch from mem)
|
||||
// end else begin // Do logic to send requests to each bank (look through thread_track_bank regs)
|
||||
bank_has_access = 8'b0;
|
||||
for (t_id = 0; t_id <= `NT_M1; t_id = t_id + 1) begin
|
||||
for (bnk = 0; bnk < NUMBER_BANKS; bnk = bnk + 1) begin
|
||||
if(thread_track_banks[bnk][t_id] == 1'b1 && bank_has_access[bnk] == 1'b0) begin
|
||||
bank_has_access[bnk] = 1'b1;
|
||||
bank_access_data[bnk] = i_p_writedata[t_id];
|
||||
bank_access_addr[bnk] = i_p_addr[t_id];
|
||||
threads_in_banks[bnk] = t_id[1:0];
|
||||
end
|
||||
end
|
||||
//if (banks_wb_needed[bnk]) begin // need to fix this for multiple misses
|
||||
//o_m_read_or_write = 1'b0;
|
||||
//o_m_addr = banks_wb_addr[bnk];
|
||||
//o_m_valid = 1'b1;
|
||||
//o_m_writedata = {banks_wb_data[bnk], 96'b0};
|
||||
//end
|
||||
//if(thread_track_bank_0[t_id] == 1'b1 && bank_has_access[0] == 1'b0) begin
|
||||
//bank_has_access[0] = 1'b1;
|
||||
//bank_access_data[0] = i_p_writedata[t_id];
|
||||
//bank_access_addr[0] = i_p_addr[t_id];
|
||||
//threads_in_banks[0] = t_id;
|
||||
//end
|
||||
// NEED TO UPDATE HITS (STORE IN THREADS_DONE)
|
||||
end
|
||||
//num_misses = {28'b0, $countones(banks_missed)};
|
||||
//did_miss = (banks_missed == 4'hF);
|
||||
|
||||
// end
|
||||
|
||||
|
||||
end
|
||||
INITIAL_PROCESSING:begin
|
||||
for (bnk = 0; bnk < NUMBER_BANKS; bnk = bnk + 1) begin
|
||||
if(banks_ready[bnk]) begin // FIX to handle hits
|
||||
thread_done[threads_in_banks[bnk]] = 1'b1;
|
||||
o_p_readdata[threads_in_banks[bnk]] = data_from_bank[bnk];
|
||||
if(i_p_read_or_write == 1'b0) begin
|
||||
o_p_readdata_valid[threads_in_banks[bnk]] = 1'b1;
|
||||
end
|
||||
thread_track_banks[bnk][threads_in_banks[bnk]] = 1'b0; // Update that this thread does not need to be serviced again
|
||||
end
|
||||
end
|
||||
//banks_to_service_temp = !banks_ready; // These are clean misses
|
||||
for (bnk = 0; bnk < NUMBER_BANKS; bnk = bnk + 1) begin
|
||||
assign banks_to_service_temp[bnk] = (banks_ready[bnk] || (bank_has_access[bnk] == 0)) ? 1'b0 : 1'b1;
|
||||
assign banks_to_wb_temp[bnk] = (banks_wb_needed[bnk]);
|
||||
assign banks_all_help[bnk] = banks_to_service_temp[bnk] || banks_to_wb_temp[bnk];
|
||||
end
|
||||
//bank_has_access = 8'b0; // Oct 23
|
||||
end
|
||||
CONTINUED_PROCESSING:begin
|
||||
//for (i = `NW-1; i >= 0; i = i - 1) begin
|
||||
// if (thread_done[threads_in_banks[bnk]] == 1'b1) begin // Not sure about this logic
|
||||
// //index = i[`NW_M1:0];
|
||||
// banks_to_service_temp[i] = 1'b0;
|
||||
// banks_to_wb_temp[i] = 1'b0;
|
||||
// end
|
||||
//end
|
||||
|
||||
for (bnk = 0; bnk < NUMBER_BANKS; bnk = bnk + 1) begin
|
||||
if(banks_ready[bnk]) begin // FIX to handle hits
|
||||
thread_done[threads_in_banks[bnk]] = 1'b1;
|
||||
o_p_readdata[threads_in_banks[bnk]] = data_from_bank[bnk];
|
||||
if(i_p_read_or_write == 1'b0) begin
|
||||
o_p_readdata_valid[threads_in_banks[bnk]] = 1'b1;
|
||||
end
|
||||
thread_track_banks[bnk][threads_in_banks[bnk]] = 1'b0; // Update that this thread does not need to be serviced again
|
||||
// Added Oct 21
|
||||
banks_to_service_temp[bnk] = 1'b0;
|
||||
banks_to_wb_temp[bnk] = 1'b0;
|
||||
end
|
||||
end
|
||||
bank_has_access = 8'b0; // Oct 23
|
||||
end
|
||||
FETCH_FROM_MEM:begin
|
||||
// NEED TO ADD LOGIC TO SEE IF MISSES GO TO SAME BLOCK
|
||||
index = 0;
|
||||
found = 0;
|
||||
for (i = `NW-1; i >= 0; i = i - 1) begin
|
||||
if (banks_to_service[i]) begin // Not sure about this logic
|
||||
//index = i[`NW_M1:0];
|
||||
index = i;
|
||||
found = 1;
|
||||
end
|
||||
end
|
||||
if (found == 1) begin
|
||||
//banks_missed[index] = 0;
|
||||
//thread_done
|
||||
|
||||
//thread_in_memory = threads_in_banks[index];
|
||||
//o_m_writedata = bank_access_data[index];
|
||||
banks_to_service_temp[index] = 0;
|
||||
o_m_addr = bank_access_addr[index];
|
||||
o_m_valid = 1'b1;
|
||||
o_m_read_or_write = 1'b0;
|
||||
end
|
||||
//bank_states = FETCH_FROM_MEM;
|
||||
end
|
||||
FETCH2:begin
|
||||
o_m_valid = 1'b0;
|
||||
end
|
||||
UPDATE_CACHE:begin
|
||||
for (bnk = 0; bnk < NUMBER_BANKS; bnk = bnk + 1) begin
|
||||
//if(thread_track_banks[bnk][t_id] == 1'b1 && bank_has_access[bnk] == 1'b0) begin
|
||||
bank_has_access[bnk] = 1'b1;
|
||||
//bank_access_data[bnk] = i_m_readdata[(bnk+1)*32 - 1:bnk*32];
|
||||
bank_access_addr[bnk] = o_m_addr;
|
||||
threads_in_banks[bnk] = t_id[1:0];
|
||||
//end
|
||||
end
|
||||
//bank_access_data = i_m_readdata;
|
||||
rd_or_wr = 1'b1;
|
||||
//thread_done[thread_in_memory] = 1'b1; // Removed, new cache style - Oct 21
|
||||
//o_p_readdata[thread_in_memory] = i_m_readdata[i_p_addr[thread_in_memory][9:5]]; // Removed, new cache style
|
||||
end
|
||||
DIRTY_EVICT_WB:begin // this begininng logic should be added to dirty evict grab block
|
||||
|
||||
//thread_done[thread_in_memory] = 1'b1;
|
||||
bank_has_access = 8'b0;
|
||||
o_m_valid = 1'b1;
|
||||
end
|
||||
DIRTY_EVICT_GRAB_BLOCK:begin
|
||||
index = 0;
|
||||
found = 0;
|
||||
for (i = `NW-1; i >= 0; i = i - 1) begin
|
||||
if (banks_to_wb_temp[i]) begin
|
||||
//index = i[`NW_M1:0];
|
||||
index = i;
|
||||
found = 1;
|
||||
end
|
||||
end
|
||||
if (found == 1) begin
|
||||
banks_to_wb_temp[index] = 0;
|
||||
for (i = `NW-1; i >= 0; i = i - 1) begin
|
||||
if (banks_to_wb_temp[i] && banks_wb_addr[index][31:7] == banks_wb_addr[i][31:7]) begin
|
||||
//index = i[`NW_M1:0];
|
||||
banks_to_wb_temp[i] = 0;
|
||||
end
|
||||
end
|
||||
//thread_done
|
||||
//thread_in_memory = threads_in_banks[index];
|
||||
//o_m_writedata[(bnk+1)*32 - 1:bnk*32] = banks_wb_data[index];
|
||||
o_m_addr = banks_wb_addr[index];
|
||||
o_m_read_or_write = 1'b1;
|
||||
end
|
||||
//for (bnk = 0; bnk < NUMBER_BANKS; bnk = bnk + 1) begin
|
||||
//o_m_writedata[(bnk+1)*32 - 1:bnk*32] = banks_wb_data[index];
|
||||
//end
|
||||
// NEXT LINE CONTAINS DATA TO WB !!!! Think need to just change this to be read data and can remove banks_wb_data
|
||||
//o_m_writedata = {banks_wb_data[7],banks_wb_data[6],banks_wb_data[5],banks_wb_data[4],banks_wb_data[3],banks_wb_data[2],banks_wb_data[1],banks_wb_data[0]};
|
||||
//num_evictions_to_wb = {28'b0, $countones(banks_wb_needed)};
|
||||
rd_or_wr = 1'b0;
|
||||
for (bnk = 0; bnk < NUMBER_BANKS; bnk = bnk + 1) begin
|
||||
//if(thread_track_banks[bnk][t_id] == 1'b1 && bank_has_access[bnk] == 1'b0) begin
|
||||
bank_has_access[bnk] = 1'b1;
|
||||
bank_access_addr[bnk] = o_m_addr;
|
||||
//end
|
||||
end
|
||||
end
|
||||
RE_ACCESS:begin
|
||||
//bank_states = INITIAL_ACCESS;
|
||||
o_m_valid = 1'b0;
|
||||
|
||||
// Before Access
|
||||
// if (no_bank_misses) begin
|
||||
// Dont do anything, next clock cycle it will switch back to (Fetch from mem)
|
||||
// end else begin // Do logic to send requests to each bank (look through thread_track_bank regs)
|
||||
//bank_has_access = banks_all_help & !(banks_to_wb) & !(banks_to_service);
|
||||
for (t_id = 0; t_id <= `NT_M1; t_id = t_id + 1) begin
|
||||
for (bnk = 0; bnk < NUMBER_BANKS; bnk = bnk + 1) begin
|
||||
//bank_has_access[bnk] = banks_all_help[bnk] && !thread_done[threads_in_banks[bnk]]; // Not sure
|
||||
bank_has_access[bnk] = banks_all_help[bnk] && !thread_done[t_id]; // Not sure
|
||||
if(thread_track_banks[bnk][t_id] == 1'b1 && bank_has_access[bnk] == 1'b1) begin
|
||||
//bank_has_access[bnk] = 1'b1;
|
||||
bank_access_data[bnk] = i_p_writedata[t_id];
|
||||
bank_access_addr[bnk] = i_p_addr[t_id];
|
||||
threads_in_banks[bnk] = t_id[1:0];
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
|
||||
end
|
||||
RE_ACCESS_PROCESSING:begin
|
||||
// After Access
|
||||
|
||||
end
|
||||
|
||||
endcase
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
banks_to_service <= banks_to_service_temp;
|
||||
banks_to_wb <= banks_to_wb_temp;
|
||||
end
|
||||
|
||||
|
||||
genvar bank_id;
|
||||
generate
|
||||
for (bank_id = 0; bank_id < NUMBER_BANKS; bank_id = bank_id + 1)
|
||||
begin
|
||||
VX_Cache_Bank bank_structure (
|
||||
.clk (clk),
|
||||
.state (state),
|
||||
.read_or_write (rd_or_wr),
|
||||
.valid_in (bank_has_access[bank_id]),
|
||||
.actual_index (bank_access_addr[bank_id][14:7]), // fix when size changes
|
||||
.o_tag (bank_access_addr[bank_id][31:15]), // fix when size changes
|
||||
.block_offset (bank_access_addr[bank_id][6:5]),
|
||||
.writedata (bank_access_data[bank_id]),
|
||||
//.fetched_writedata (i_m_readdata[(bank_id+1)*32-1 -: 32]),
|
||||
.fetched_writedata (i_m_readdata[bank_id[3:0]]),
|
||||
.readdata (data_from_bank[bank_id]),
|
||||
.hit (banks_ready[bank_id]),
|
||||
//.miss (banks_missed[bank_id]),
|
||||
.eviction_wb (banks_wb_needed[bank_id]),
|
||||
.eviction_addr (banks_wb_addr[bank_id]),
|
||||
//.data_evicted (o_m_writedata[(bank_id+1)*32-1 -: 32])
|
||||
.data_evicted (o_m_writedata[bank_id[3:0]])
|
||||
);
|
||||
|
||||
end
|
||||
endgenerate
|
||||
|
||||
//end
|
||||
|
||||
endmodule
|
||||
|
|
@ -8,7 +8,8 @@
|
|||
interface VX_dram_req_rsp_inter ();
|
||||
|
||||
// Req
|
||||
wire [31:0] o_m_addr;
|
||||
wire [31:0] o_m_evict_addr;
|
||||
wire [31:0] o_m_read_addr;
|
||||
wire o_m_valid;
|
||||
wire[`NUMBER_BANKS - 1:0][`NUM_WORDS_PER_BLOCK-1:0][31:0] o_m_writedata;
|
||||
wire o_m_read_or_write;
|
||||
|
|
|
|||
|
|
@ -3,6 +3,8 @@
|
|||
|
||||
#define NW 8
|
||||
|
||||
#define CACHE_NUM_BANKS 8
|
||||
#define CACHE_WORDS_PER_BLOCK 4
|
||||
|
||||
#define R_INST 51
|
||||
#define L_INST 3
|
||||
|
|
|
|||
|
|
@ -5,11 +5,12 @@
|
|||
int main(int argc, char **argv)
|
||||
{
|
||||
|
||||
Verilated::debug(1);
|
||||
|
||||
Verilated::commandArgs(argc, argv);
|
||||
|
||||
Verilated::traceEverOn(true);
|
||||
|
||||
// Verilated::debug(1);
|
||||
|
||||
|
||||
// bool passed = true;
|
||||
|
|
|
|||
|
|
@ -45,6 +45,8 @@ class Vortex
|
|||
VVortex * vortex;
|
||||
|
||||
unsigned start_pc;
|
||||
bool refill;
|
||||
unsigned refill_addr;
|
||||
long int curr_cycle;
|
||||
bool stop;
|
||||
bool unit_test;
|
||||
|
|
@ -190,120 +192,196 @@ bool Vortex::ibus_driver()
|
|||
|
||||
bool Vortex::dbus_driver()
|
||||
{
|
||||
uint32_t data_read;
|
||||
uint32_t data_write;
|
||||
uint32_t addr;
|
||||
// std::cout << "DBUS DRIVER\n" << std::endl;
|
||||
////////////////////// DBUS //////////////////////
|
||||
|
||||
bool did = false;
|
||||
|
||||
for (unsigned curr_th = 0; curr_th < NT; curr_th++)
|
||||
|
||||
if (this->refill)
|
||||
{
|
||||
if ((vortex->out_cache_driver_in_mem_write != NO_MEM_WRITE) && vortex->out_cache_driver_in_valid[curr_th])
|
||||
this->refill = false;
|
||||
unsigned unordered_mem[32];
|
||||
int num_iter = 0;
|
||||
for (int i = 0; i < CACHE_WORDS_PER_BLOCK; i++)
|
||||
{
|
||||
did = true;
|
||||
data_write = (uint32_t) vortex->out_cache_driver_in_data[curr_th];
|
||||
addr = (uint32_t) vortex->out_cache_driver_in_address[curr_th];
|
||||
|
||||
if (addr == 0x00010000)
|
||||
{
|
||||
std::cerr << (char) data_write;
|
||||
}
|
||||
|
||||
// if ((addr >= 0x810002cc) && (addr < 0x810002d0))
|
||||
// {
|
||||
// int index = (addr - 0x810002cc) / 4;
|
||||
// // std::cerr << GREEN << "1done[" << index << "] = " << data_write << DEFAULT << "\n";
|
||||
// }
|
||||
|
||||
// if ((addr >= 0x810059f4) && (addr < 0x810059f4))
|
||||
// {
|
||||
// int index = (addr - 0x810059f4) / 4;
|
||||
// // std::cerr << RED << "2done[" << index << "] = " << data_write << DEFAULT << "\n";
|
||||
// }
|
||||
|
||||
if (vortex->out_cache_driver_in_mem_write == SB_MEM_WRITE)
|
||||
{
|
||||
data_write = ( data_write) & 0xFF;
|
||||
ram.writeByte( addr, &data_write);
|
||||
|
||||
} else if (vortex->out_cache_driver_in_mem_write == SH_MEM_WRITE)
|
||||
{
|
||||
data_write = ( data_write) & 0xFFFF;
|
||||
ram.writeHalf( addr, &data_write);
|
||||
} else if (vortex->out_cache_driver_in_mem_write == SW_MEM_WRITE)
|
||||
{
|
||||
// printf("STORING %x in %x \n", data_write, addr);
|
||||
data_write = data_write;
|
||||
ram.writeWord( addr, &data_write);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
// printf("----\n");
|
||||
for (unsigned curr_th = 0; curr_th < NT; curr_th++)
|
||||
{
|
||||
|
||||
if ((vortex->out_cache_driver_in_mem_read != NO_MEM_READ) && vortex->out_cache_driver_in_valid[curr_th])
|
||||
{
|
||||
did = true;
|
||||
addr = (uint32_t) vortex->out_cache_driver_in_address[curr_th];
|
||||
for (int j = 0; j < (CACHE_NUM_BANKS*8); j+=8)
|
||||
{
|
||||
unsigned addr = this->refill_addr + (4*num_iter);
|
||||
unsigned data_read;
|
||||
ram.getWord(addr, &data_read);
|
||||
|
||||
if (vortex->out_cache_driver_in_mem_read == LB_MEM_READ)
|
||||
{
|
||||
|
||||
vortex->in_cache_driver_out_data[curr_th] = (data_read & 0x80) ? (data_read | 0xFFFFFF00) : (data_read & 0xFF);
|
||||
|
||||
} else if (vortex->out_cache_driver_in_mem_read == LH_MEM_READ)
|
||||
{
|
||||
|
||||
vortex->in_cache_driver_out_data[curr_th] = (data_read & 0x8000) ? (data_read | 0xFFFF0000) : (data_read & 0xFFFF);
|
||||
|
||||
} else if (vortex->out_cache_driver_in_mem_read == LW_MEM_READ)
|
||||
{
|
||||
// printf("Reading mem - Addr: %x = %x\n", addr, data_read);
|
||||
// std::cout << "READING - Addr: " << std::hex << addr << " = " << data_read << "\n";
|
||||
// std::cout << std::dec;
|
||||
vortex->in_cache_driver_out_data[curr_th] = data_read;
|
||||
|
||||
} else if (vortex->out_cache_driver_in_mem_read == LBU_MEM_READ)
|
||||
{
|
||||
|
||||
vortex->in_cache_driver_out_data[curr_th] = (data_read & 0xFF);
|
||||
|
||||
} else if (vortex->out_cache_driver_in_mem_read == LHU_MEM_READ)
|
||||
{
|
||||
|
||||
vortex->in_cache_driver_out_data[curr_th] = (data_read & 0xFFFF);
|
||||
|
||||
}
|
||||
else
|
||||
{
|
||||
vortex->in_cache_driver_out_data[curr_th] = 0xbabebabe;
|
||||
}
|
||||
unordered_mem[i+j] = data_read;
|
||||
num_iter++;
|
||||
}
|
||||
}
|
||||
else
|
||||
|
||||
vortex->i_m_ready = 1;
|
||||
for (int i = 0; i < CACHE_NUM_BANKS; i++)
|
||||
{
|
||||
vortex->in_cache_driver_out_data[curr_th] = 0xbabebabe;
|
||||
for (int j = 0; j < CACHE_WORDS_PER_BLOCK; j++)
|
||||
{
|
||||
vortex->i_m_readdata[i][j] = unordered_mem[(i*CACHE_WORDS_PER_BLOCK)+j];
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
if (did && (NW > 1))
|
||||
else
|
||||
{
|
||||
|
||||
if (NW < NT)
|
||||
if (vortex->o_m_valid)
|
||||
{
|
||||
this->stats_total_cycles += NT % (NW -1);
|
||||
if (vortex->o_m_read_or_write)
|
||||
{
|
||||
unsigned ordered_mem[32];
|
||||
|
||||
// Create unordered mem
|
||||
unsigned unordered_mem[32];
|
||||
for (int i = 0; i < CACHE_NUM_BANKS; i++)
|
||||
{
|
||||
for (int j = 0; j < CACHE_WORDS_PER_BLOCK; j++)
|
||||
{
|
||||
unordered_mem[(i*CACHE_WORDS_PER_BLOCK)+j] = vortex->o_m_writedata[i][j];
|
||||
}
|
||||
}
|
||||
|
||||
// Order the memory
|
||||
int num_iter = 0;
|
||||
for (int i = 0; i < CACHE_NUM_BANKS; i++)
|
||||
{
|
||||
for (int j = 0; j < (CACHE_NUM_BANKS*CACHE_WORDS_PER_BLOCK); j+=CACHE_WORDS_PER_BLOCK)
|
||||
{
|
||||
printf("i: %d, j: %d, num_iter: %d\n", i, j, num_iter);
|
||||
ordered_mem[i+j] = unordered_mem[num_iter];
|
||||
num_iter++;
|
||||
}
|
||||
}
|
||||
|
||||
// Save the memory
|
||||
for (int i = 0; i < (CACHE_WORDS_PER_BLOCK * CACHE_NUM_BANKS); i++)
|
||||
{
|
||||
unsigned addr = (vortex->o_m_evict_addr) + (4*i);
|
||||
unsigned * data_addr = ordered_mem + i;
|
||||
ram.writeWord( addr, data_addr);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
// Respond next cycle
|
||||
this->refill = true;
|
||||
this->refill_addr = vortex->o_m_read_addr;
|
||||
}
|
||||
}
|
||||
|
||||
// uint32_t data_read;
|
||||
// uint32_t data_write;
|
||||
// uint32_t addr;
|
||||
// // std::cout << "DBUS DRIVER\n" << std::endl;
|
||||
// ////////////////////// DBUS //////////////////////
|
||||
|
||||
// bool did = false;
|
||||
|
||||
// for (unsigned curr_th = 0; curr_th < NT; curr_th++)
|
||||
// {
|
||||
// if ((vortex->out_cache_driver_in_mem_write != NO_MEM_WRITE) && vortex->out_cache_driver_in_valid[curr_th])
|
||||
// {
|
||||
// did = true;
|
||||
// data_write = (uint32_t) vortex->out_cache_driver_in_data[curr_th];
|
||||
// addr = (uint32_t) vortex->out_cache_driver_in_address[curr_th];
|
||||
|
||||
// if (addr == 0x00010000)
|
||||
// {
|
||||
// std::cerr << (char) data_write;
|
||||
// }
|
||||
|
||||
// // if ((addr >= 0x810002cc) && (addr < 0x810002d0))
|
||||
// // {
|
||||
// // int index = (addr - 0x810002cc) / 4;
|
||||
// // // std::cerr << GREEN << "1done[" << index << "] = " << data_write << DEFAULT << "\n";
|
||||
// // }
|
||||
|
||||
// // if ((addr >= 0x810059f4) && (addr < 0x810059f4))
|
||||
// // {
|
||||
// // int index = (addr - 0x810059f4) / 4;
|
||||
// // // std::cerr << RED << "2done[" << index << "] = " << data_write << DEFAULT << "\n";
|
||||
// // }
|
||||
|
||||
// if (vortex->out_cache_driver_in_mem_write == SB_MEM_WRITE)
|
||||
// {
|
||||
// data_write = ( data_write) & 0xFF;
|
||||
// ram.writeByte( addr, &data_write);
|
||||
|
||||
// } else if (vortex->out_cache_driver_in_mem_write == SH_MEM_WRITE)
|
||||
// {
|
||||
// data_write = ( data_write) & 0xFFFF;
|
||||
// ram.writeHalf( addr, &data_write);
|
||||
// } else if (vortex->out_cache_driver_in_mem_write == SW_MEM_WRITE)
|
||||
// {
|
||||
// // printf("STORING %x in %x \n", data_write, addr);
|
||||
// data_write = data_write;
|
||||
// ram.writeWord( addr, &data_write);
|
||||
// }
|
||||
|
||||
// }
|
||||
|
||||
// }
|
||||
|
||||
|
||||
|
||||
|
||||
// // printf("----\n");
|
||||
// for (unsigned curr_th = 0; curr_th < NT; curr_th++)
|
||||
// {
|
||||
|
||||
// if ((vortex->out_cache_driver_in_mem_read != NO_MEM_READ) && vortex->out_cache_driver_in_valid[curr_th])
|
||||
// {
|
||||
// did = true;
|
||||
// addr = (uint32_t) vortex->out_cache_driver_in_address[curr_th];
|
||||
// ram.getWord(addr, &data_read);
|
||||
|
||||
// if (vortex->out_cache_driver_in_mem_read == LB_MEM_READ)
|
||||
// {
|
||||
|
||||
// vortex->in_cache_driver_out_data[curr_th] = (data_read & 0x80) ? (data_read | 0xFFFFFF00) : (data_read & 0xFF);
|
||||
|
||||
// } else if (vortex->out_cache_driver_in_mem_read == LH_MEM_READ)
|
||||
// {
|
||||
|
||||
// vortex->in_cache_driver_out_data[curr_th] = (data_read & 0x8000) ? (data_read | 0xFFFF0000) : (data_read & 0xFFFF);
|
||||
|
||||
// } else if (vortex->out_cache_driver_in_mem_read == LW_MEM_READ)
|
||||
// {
|
||||
// // printf("Reading mem - Addr: %x = %x\n", addr, data_read);
|
||||
// // std::cout << "READING - Addr: " << std::hex << addr << " = " << data_read << "\n";
|
||||
// // std::cout << std::dec;
|
||||
// vortex->in_cache_driver_out_data[curr_th] = data_read;
|
||||
|
||||
// } else if (vortex->out_cache_driver_in_mem_read == LBU_MEM_READ)
|
||||
// {
|
||||
|
||||
// vortex->in_cache_driver_out_data[curr_th] = (data_read & 0xFF);
|
||||
|
||||
// } else if (vortex->out_cache_driver_in_mem_read == LHU_MEM_READ)
|
||||
// {
|
||||
|
||||
// vortex->in_cache_driver_out_data[curr_th] = (data_read & 0xFFFF);
|
||||
|
||||
// }
|
||||
// else
|
||||
// {
|
||||
// vortex->in_cache_driver_out_data[curr_th] = 0xbabebabe;
|
||||
// }
|
||||
// }
|
||||
// else
|
||||
// {
|
||||
// vortex->in_cache_driver_out_data[curr_th] = 0xbabebabe;
|
||||
// }
|
||||
|
||||
// }
|
||||
|
||||
// if (did && (NW > 1))
|
||||
// {
|
||||
|
||||
// if (NW < NT)
|
||||
// {
|
||||
// this->stats_total_cycles += NT % (NW -1);
|
||||
// }
|
||||
// }
|
||||
// printf("******\n");
|
||||
|
||||
|
||||
|
|
@ -376,15 +454,17 @@ bool Vortex::simulate(std::string file_to_simulate)
|
|||
vortex->reset = 1;
|
||||
vortex->clk = 0;
|
||||
vortex->eval();
|
||||
// m_trace->dump(10);
|
||||
vortex->reset = 1;
|
||||
vortex->clk = 1;
|
||||
vortex->eval();
|
||||
// m_trace->dump(11);
|
||||
vortex->reset = 0;
|
||||
vortex->clk = 0;
|
||||
|
||||
// unsigned cycles;
|
||||
counter = 0;
|
||||
this->stats_total_cycles = 10;
|
||||
this->stats_total_cycles = 12;
|
||||
while (this->stop && ((counter < 2)))
|
||||
// while (this->stats_total_cycles < 10)
|
||||
{
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue