minor updates

hw/rtl/VX_platform.vh

@@ -44,11 +44,6 @@ endgenerate
         end                       \
     end
 
-`define __SCOPE
-`define __SCOPE_X
-`define __SCOPE_ON
-`define __SCOPE_OFF
-
 `ifndef TRACING_ALL
 `define TRACING_ON      /* verilator tracing_on */
 `define TRACING_OFF     /* verilator tracing_off */
@@ -158,18 +153,6 @@ endgenerate
 `define UNUSED_PIN(x) . x ()
 `define UNUSED_ARG(x) x
 
-`define __SCOPE (* mark_debug="true" *)
-
-`define __SCOPE_X
-
-`define __SCOPE_ON  \
-    `undef __SCOPE_X \
-    `define __SCOPE_X `__SCOPE
-
-`define __SCOPE_OFF  \
-    `undef __SCOPE_X \
-    `define __SCOPE_X
-
 `endif
 
 ///////////////////////////////////////////////////////////////////////////////

hw/rtl/afu/xrt/VX_afu_wrap.sv

@@ -373,7 +373,9 @@ module VX_afu_wrap #(
     `SCOPE_IO_UNUSED(0)
 `endif
 `endif
+
 `ifdef CHIPSCOPE
+`ifdef DBG_SCOPE_AFU
     ila_afu ila_afu_inst (
       	.clk (clk),
 		.probe0 ({
@@ -394,6 +396,7 @@ module VX_afu_wrap #(
 		})
     );
 `endif
+`endif
 
 `ifdef SIMULATION
 `ifndef VERILATOR

hw/rtl/core/VX_fetch.sv

@@ -166,7 +166,9 @@ module VX_fetch import VX_gpu_pkg::*; #(
     `SCOPE_IO_UNUSED(0)
 `endif
 `endif
+
 `ifdef CHIPSCOPE
+`ifdef DBG_SCOPE_FETCH
     ila_fetch ila_fetch_inst (
         .clk    (clk),
         .probe0 ({schedule_if.valid, schedule_if.data, schedule_if.ready}),
@@ -174,6 +176,7 @@ module VX_fetch import VX_gpu_pkg::*; #(
         .probe2 ({icache_bus_if.rsp_valid, icache_bus_if.rsp_data, icache_bus_if.rsp_ready})
     );
 `endif
+`endif
 
 `ifdef DBG_TRACE_MEM
     always @(posedge clk) begin

hw/rtl/core/VX_issue_slice.sv

@@ -143,7 +143,9 @@ module VX_issue_slice import VX_gpu_pkg::*; #(
     `SCOPE_IO_UNUSED(0)
 `endif
 `endif
+
 `ifdef CHIPSCOPE
+`ifdef DBG_SCOPE_ISSUE
     ila_issue ila_issue_inst (
         .clk    (clk),
         .probe0 ({decode_if.valid, decode_if.data, decode_if.ready}),
@@ -152,6 +154,7 @@ module VX_issue_slice import VX_gpu_pkg::*; #(
         .probe3 ({writeback_if.valid, writeback_if.data})
     );
 `endif
+`endif
 
 `ifdef DBG_TRACE_PIPELINE
     always @(posedge clk) begin

hw/rtl/core/VX_lsu_slice.sv

@@ -561,7 +561,9 @@ module VX_lsu_slice import VX_gpu_pkg::*; #(
     `SCOPE_IO_UNUSED(0)
 `endif
 `endif
+
 `ifdef CHIPSCOPE
+`ifdef DBG_SCOPE_LSU
     ila_lsu ila_lsu_inst (
         .clk    (clk),
         .probe0 ({execute_if.valid, execute_if.data, execute_if.ready}),
@@ -569,5 +571,6 @@ module VX_lsu_slice import VX_gpu_pkg::*; #(
         .probe2 ({lsu_mem_if.rsp_valid, lsu_mem_if.rsp_data, lsu_mem_if.rsp_ready})
     );
 `endif
+`endif
 
 endmodule