mirror of
https://github.com/vortexgpgpu/vortex.git
synced 2025-04-23 13:27:29 -04:00
minor build fixes
This commit is contained in:
Blaise Tine
parent
9b1b8789ac
commit
2415199a8c
6 changed files with 18 additions and 714 deletions
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@ -1,7 +1,7 @@
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#CFLAGS += -std=c++11 -O3 -Wall -Wextra -pedantic -Wfatal-errors
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CFLAGS += -std=c++11 -g -O0 -Wall -Wextra -pedantic -Wfatal-errors
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#USE_MULTICORE=1
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USE_MULTICORE=1
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CFLAGS += -I../../include -I../../../../rtl/simulate
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Binary file not shown.
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@ -5,8 +5,8 @@ INCLUDE=-I. -Ishared_memory -Icache -IVX_cache -IVX_cache/interfaces -Iinterface
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SINGLE_CORE=Vortex.v
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MULTI_CORE=Vortex_SOC.v
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EXE=--exe ./simulate/test_bench.cpp
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MULTI_EXE=--exe ./simulate/multi_test_bench.cpp
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EXE=--exe ./simulate/test_bench.cpp ./simulate/Vortex.cpp
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MULTI_EXE=--exe ./simulate/multi_test_bench.cpp ./simulate/Vortex_SOC.cpp
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COMP=--compiler gcc --language 1800-2009
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@ -291,8 +291,6 @@ void Vortex::flush_caches(uint32_t mem_addr, uint32_t size) {
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}
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bool Vortex::simulate() {
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this->wait(50);
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// reset the device
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this->reset();
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@ -20,13 +20,6 @@
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#include <verilated_vcd_c.h>
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#endif
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unsigned long time_stamp = 0;
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double sc_time_stamp()
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{
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return time_stamp / 1000.0;
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}
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typedef struct
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{
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int cycles_left;
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@ -41,11 +34,17 @@ class Vortex
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Vortex(RAM* ram);
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~Vortex();
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bool simulate();
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void step();
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void reset();
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void flush_caches(uint32_t mem_addr, uint32_t size);
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bool is_busy();
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private:
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void print_stats(bool = true);
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bool ibus_driver();
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bool dbus_driver();
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void io_handler();
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void send_snoops(uint32_t mem_addr, uint32_t size);
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void wait(uint32_t cycles);
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RAM* ram;
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@ -79,387 +78,4 @@ class Vortex
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#ifdef VCD_OUTPUT
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VerilatedVcdC *m_trace;
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#endif
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};
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Vortex::Vortex(RAM* ram) : start_pc(0), curr_cycle(0), stop(true), unit_test(true), stats_static_inst(0), stats_dynamic_inst(-1),
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stats_total_cycles(0), stats_fwd_stalls(0), stats_branch_stalls(0),
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debug_state(0), ibus_state(0), dbus_state(0), debug_return(0),
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debug_wait_num(0), debug_inst_num(0), debug_end_wait(0), debug_debugAddr(0)
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{
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this->ram = ram;
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this->vortex = new VVortex;
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#ifdef VCD_OUTPUT
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this->m_trace = new VerilatedVcdC;
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this->vortex->trace(m_trace, 99);
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this->m_trace->open("trace.vcd");
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#endif
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this->results.open("../results.txt");
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}
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Vortex::~Vortex()
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{
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#ifdef VCD_OUTPUT
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m_trace->close();
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#endif
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this->results.close();
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delete this->vortex;
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}
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void Vortex::print_stats(bool cycle_test)
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{
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if (cycle_test)
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{
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this->results << std::left;
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// this->results << "# Static Instructions:\t" << std::dec << this->stats_static_inst << std::endl;
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this->results << std::setw(24) << "# Dynamic Instructions:" << std::dec << this->stats_dynamic_inst << std::endl;
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this->results << std::setw(24) << "# of total cycles:" << std::dec << this->stats_total_cycles << std::endl;
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this->results << std::setw(24) << "# of forwarding stalls:" << std::dec << this->stats_fwd_stalls << std::endl;
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this->results << std::setw(24) << "# of branch stalls:" << std::dec << this->stats_branch_stalls << std::endl;
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this->results << std::setw(24) << "# CPI:" << std::dec << (double) this->stats_total_cycles / (double) this->stats_dynamic_inst << std::endl;
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this->results << std::setw(24) << "# time to simulate: " << std::dec << this->stats_sim_time << " milliseconds" << std::endl;
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}
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else
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{
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this->results << std::left;
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this->results << std::setw(24) << "# of total cycles:" << std::dec << this->stats_total_cycles << std::endl;
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this->results << std::setw(24) << "# time to simulate: " << std::dec << this->stats_sim_time << " milliseconds" << std::endl;
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}
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uint32_t status;
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ram->getWord(0, &status);
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if (this->unit_test)
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{
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if (status == 1)
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{
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this->results << std::setw(24) << "# GRADE:" << "PASSING\n";
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} else
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{
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this->results << std::setw(24) << "# GRADE:" << "Failed on test: " << status << "\n";
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}
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}
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else
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{
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this->results << std::setw(24) << "# GRADE:" << "N/A [NOT A UNIT TEST]\n";
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}
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this->stats_static_inst = 0;
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this->stats_dynamic_inst = -1;
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this->stats_total_cycles = 0;
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this->stats_fwd_stalls = 0;
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this->stats_branch_stalls = 0;
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}
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bool Vortex::ibus_driver()
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{
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// Iterate through each element, and get pop index
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int dequeue_index = -1;
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bool dequeue_valid = false;
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for (int i = 0; i < this->I_dram_req_vec.size(); i++)
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{
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if (this->I_dram_req_vec[i].cycles_left > 0)
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{
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this->I_dram_req_vec[i].cycles_left -= 1;
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}
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if ((this->I_dram_req_vec[i].cycles_left == 0) && (!dequeue_valid))
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{
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dequeue_index = i;
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dequeue_valid = true;
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}
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}
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if (vortex->I_dram_req)
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{
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// std::cout << "Icache Dram Request received!\n";
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if (vortex->I_dram_req_read)
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{
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// std::cout << "Icache Dram Request is read!\n";
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// Need to add an element
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dram_req_t dram_req;
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dram_req.cycles_left = vortex->I_dram_expected_lat;
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dram_req.data_length = vortex->I_dram_req_size / 4;
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dram_req.base_addr = vortex->I_dram_req_addr;
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dram_req.data = (unsigned *) malloc(dram_req.data_length * sizeof(unsigned));
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for (int i = 0; i < dram_req.data_length; i++)
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{
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unsigned curr_addr = dram_req.base_addr + (i*4);
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unsigned data_rd;
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ram->getWord(curr_addr, &data_rd);
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dram_req.data[i] = data_rd;
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}
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// std::cout << "Fill Req -> Addr: " << std::hex << dram_req.base_addr << std::dec << "\n";
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this->I_dram_req_vec.push_back(dram_req);
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}
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if (vortex->I_dram_req_write)
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{
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unsigned base_addr = vortex->I_dram_req_addr;
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unsigned data_length = vortex->I_dram_req_size / 4;
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for (int i = 0; i < data_length; i++)
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{
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unsigned curr_addr = base_addr + (i*4);
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unsigned data_wr = vortex->I_dram_req_data[i];
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ram->writeWord(curr_addr, &data_wr);
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}
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}
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}
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if (vortex->I_dram_fill_accept && dequeue_valid)
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{
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// std::cout << "Icache Dram Response Sending...!\n";
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vortex->I_dram_fill_rsp = 1;
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vortex->I_dram_fill_rsp_addr = this->I_dram_req_vec[dequeue_index].base_addr;
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// std::cout << "Fill Rsp -> Addr: " << std::hex << (this->I_dram_req_vec[dequeue_index].base_addr) << std::dec << "\n";
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for (int i = 0; i < this->I_dram_req_vec[dequeue_index].data_length; i++)
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{
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vortex->I_dram_fill_rsp_data[i] = this->I_dram_req_vec[dequeue_index].data[i];
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}
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free(this->I_dram_req_vec[dequeue_index].data);
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this->I_dram_req_vec.erase(this->I_dram_req_vec.begin() + dequeue_index);
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}
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else
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{
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vortex->I_dram_fill_rsp = 0;
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vortex->I_dram_fill_rsp_addr = 0;
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}
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return false;
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}
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void Vortex::io_handler()
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{
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// std::cout << "Checking\n";
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if (vortex->io_valid)
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{
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uint32_t data_write = (uint32_t) vortex->io_data;
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// std::cout << "IO VALID!\n";
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char c = (char) data_write;
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std::cerr << c;
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// std::cout << c;
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std::cout << std::flush;
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}
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}
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bool Vortex::dbus_driver()
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{
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// Iterate through each element, and get pop index
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int dequeue_index = -1;
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bool dequeue_valid = false;
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for (int i = 0; i < this->dram_req_vec.size(); i++)
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{
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if (this->dram_req_vec[i].cycles_left > 0)
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{
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this->dram_req_vec[i].cycles_left -= 1;
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}
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if ((this->dram_req_vec[i].cycles_left == 0) && (!dequeue_valid))
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{
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dequeue_index = i;
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dequeue_valid = true;
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}
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}
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if (vortex->dram_req)
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{
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if (vortex->dram_req_read)
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{
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// Need to add an element
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dram_req_t dram_req;
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dram_req.cycles_left = vortex->dram_expected_lat;
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dram_req.data_length = vortex->dram_req_size / 4;
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dram_req.base_addr = vortex->dram_req_addr;
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dram_req.data = (unsigned *) malloc(dram_req.data_length * sizeof(unsigned));
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for (int i = 0; i < dram_req.data_length; i++)
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{
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unsigned curr_addr = dram_req.base_addr + (i*4);
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unsigned data_rd;
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ram->getWord(curr_addr, &data_rd);
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dram_req.data[i] = data_rd;
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}
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// std::cout << "Fill Req -> Addr: " << std::hex << dram_req.base_addr << std::dec << "\n";
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this->dram_req_vec.push_back(dram_req);
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}
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if (vortex->dram_req_write)
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{
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unsigned base_addr = vortex->dram_req_addr;
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unsigned data_length = vortex->dram_req_size / 4;
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for (int i = 0; i < data_length; i++)
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{
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unsigned curr_addr = base_addr + (i*4);
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unsigned data_wr = vortex->dram_req_data[i];
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ram->writeWord(curr_addr, &data_wr);
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}
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}
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}
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if (vortex->dram_fill_accept && dequeue_valid)
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{
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vortex->dram_fill_rsp = 1;
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vortex->dram_fill_rsp_addr = this->dram_req_vec[dequeue_index].base_addr;
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// std::cout << "Fill Rsp -> Addr: " << std::hex << (this->dram_req_vec[dequeue_index].base_addr) << std::dec << "\n";
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for (int i = 0; i < this->dram_req_vec[dequeue_index].data_length; i++)
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{
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vortex->dram_fill_rsp_data[i] = this->dram_req_vec[dequeue_index].data[i];
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}
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free(this->dram_req_vec[dequeue_index].data);
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this->dram_req_vec.erase(this->dram_req_vec.begin() + dequeue_index);
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}
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else
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{
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vortex->dram_fill_rsp = 0;
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vortex->dram_fill_rsp_addr = 0;
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}
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return false;
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}
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bool Vortex::simulate()
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{
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// auto start_time = std::chrono::high_resolution_clock::now();
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static bool stop = false;
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static int counter = 0;
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counter = 0;
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stop = false;
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// auto start_time = clock();
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// vortex->reset = 1;
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// vortex->reset = 0;
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unsigned curr_inst;
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unsigned new_PC;
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// while (this->stop && (!(stop && (counter > 5))))
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// {
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// // std::cout << "************* Cycle: " << cycle << "\n";
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// bool istop = ibus_driver();
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// bool dstop = !dbus_driver();
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// vortex->clk = 1;
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// vortex->eval();
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// vortex->clk = 0;
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// vortex->eval();
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// stop = istop && dstop;
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// if (stop)
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// {
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// counter++;
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// } else
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// {
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// counter = 0;
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// }
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// cycle++;
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// }
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bool istop;
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bool dstop;
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bool cont = false;
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// for (int i = 0; i < 500; i++)
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vortex->reset = 1;
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vortex->clk = 0;
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vortex->eval();
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// m_trace->dump(10);
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vortex->reset = 1;
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vortex->clk = 1;
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vortex->eval();
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// m_trace->dump(11);
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vortex->reset = 0;
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vortex->clk = 0;
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// unsigned cycles;
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counter = 0;
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this->stats_total_cycles = 12;
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while (this->stop && ((counter < 5)))
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// while (this->stats_total_cycles < 10)
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{
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// printf("-------------------------\n");
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// std::cout << "Counter: " << counter << "\n";
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// if ((this->stats_total_cycles) % 5000 == 0) std::cout << "************* Cycle: " << (this->stats_total_cycles) << "\n";
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// dstop = !dbus_driver();
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#ifdef VCD_OUTPUT
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m_trace->dump(2*this->stats_total_cycles);
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#endif
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vortex->clk = 1;
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vortex->eval();
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istop = ibus_driver();
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dstop = !dbus_driver();
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io_handler();
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#ifdef VCD_OUTPUT
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m_trace->dump((2*this->stats_total_cycles)+1);
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#endif
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vortex->clk = 0;
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vortex->eval();
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// stop = istop && dstop;
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stop = vortex->out_ebreak;
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if (stop || cont)
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// if (istop)
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{
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cont = true;
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counter++;
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} else
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{
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counter = 0;
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}
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++time_stamp;
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++stats_total_cycles;
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}
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std::cerr << "New Total Cycles: " << (this->stats_total_cycles) << "\n";
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int status = (unsigned int) vortex->Vortex->vx_back_end->VX_wb->last_data_wb & 0xf;
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// std::cout << "Last wb: " << std::hex << ((unsigned int) vortex->Vortex__DOT__vx_back_end__DOT__VX_wb__DOT__last_data_wb) << "\n";
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// std::cout << "Something: " << result << '\n';
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// uint32_t status;
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// ram->getWord(0, &status);
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this->print_stats();
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return (status == 1);
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// return (1 == 1);
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}
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};
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@ -19,13 +19,6 @@
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#include <verilated_vcd_c.h>
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#endif
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unsigned long time_stamp = 0;
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double sc_time_stamp()
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{
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return time_stamp / 1000.0;
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}
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typedef struct
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{
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int cycles_left;
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|
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@ -40,11 +33,17 @@ class Vortex_SOC
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Vortex_SOC(RAM* ram);
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~Vortex_SOC();
|
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bool simulate();
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void step();
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void reset();
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void flush_caches(uint32_t mem_addr, uint32_t size);
|
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bool is_busy();
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private:
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void print_stats(bool = true);
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bool ibus_driver();
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bool dbus_driver();
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void io_handler();
|
||||
void io_handler();
|
||||
void send_snoops(uint32_t mem_addr, uint32_t size);
|
||||
void wait(uint32_t cycles);
|
||||
|
||||
RAM* ram;
|
||||
|
||||
|
|
@ -77,313 +76,4 @@ class Vortex_SOC
|
|||
#ifdef VCD_OUTPUT
|
||||
VerilatedVcdC *m_trace;
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
|
||||
Vortex_SOC::Vortex_SOC(RAM* ram) : start_pc(0), curr_cycle(0), stop(true), unit_test(true), stats_static_inst(0), stats_dynamic_inst(-1),
|
||||
stats_total_cycles(0), stats_fwd_stalls(0), stats_branch_stalls(0),
|
||||
debug_state(0), ibus_state(0), dbus_state(0), debug_return(0),
|
||||
debug_wait_num(0), debug_inst_num(0), debug_end_wait(0), debug_debugAddr(0)
|
||||
{
|
||||
this->ram = ram;
|
||||
this->vortex = new VVortex_SOC;
|
||||
#ifdef VCD_OUTPUT
|
||||
this->m_trace = new VerilatedVcdC;
|
||||
this->vortex->trace(m_trace, 99);
|
||||
this->m_trace->open("trace.vcd");
|
||||
#endif
|
||||
this->results.open("../results.txt");
|
||||
}
|
||||
|
||||
Vortex_SOC::~Vortex_SOC()
|
||||
{
|
||||
#ifdef VCD_OUTPUT
|
||||
m_trace->close();
|
||||
#endif
|
||||
this->results.close();
|
||||
delete this->vortex;
|
||||
}
|
||||
|
||||
void Vortex_SOC::print_stats(bool cycle_test)
|
||||
{
|
||||
|
||||
if (cycle_test)
|
||||
{
|
||||
this->results << std::left;
|
||||
// this->results << "# Static Instructions:\t" << std::dec << this->stats_static_inst << std::endl;
|
||||
this->results << std::setw(24) << "# Dynamic Instructions:" << std::dec << this->stats_dynamic_inst << std::endl;
|
||||
this->results << std::setw(24) << "# of total cycles:" << std::dec << this->stats_total_cycles << std::endl;
|
||||
this->results << std::setw(24) << "# of forwarding stalls:" << std::dec << this->stats_fwd_stalls << std::endl;
|
||||
this->results << std::setw(24) << "# of branch stalls:" << std::dec << this->stats_branch_stalls << std::endl;
|
||||
this->results << std::setw(24) << "# CPI:" << std::dec << (double) this->stats_total_cycles / (double) this->stats_dynamic_inst << std::endl;
|
||||
this->results << std::setw(24) << "# time to simulate: " << std::dec << this->stats_sim_time << " milliseconds" << std::endl;
|
||||
}
|
||||
else
|
||||
{
|
||||
this->results << std::left;
|
||||
this->results << std::setw(24) << "# of total cycles:" << std::dec << this->stats_total_cycles << std::endl;
|
||||
this->results << std::setw(24) << "# time to simulate: " << std::dec << this->stats_sim_time << " milliseconds" << std::endl;
|
||||
}
|
||||
|
||||
|
||||
uint32_t status;
|
||||
ram->getWord(0, &status);
|
||||
|
||||
if (this->unit_test)
|
||||
{
|
||||
if (status == 1)
|
||||
{
|
||||
this->results << std::setw(24) << "# GRADE:" << "PASSING\n";
|
||||
} else
|
||||
{
|
||||
this->results << std::setw(24) << "# GRADE:" << "Failed on test: " << status << "\n";
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
this->results << std::setw(24) << "# GRADE:" << "N/A [NOT A UNIT TEST]\n";
|
||||
}
|
||||
|
||||
this->stats_static_inst = 0;
|
||||
this->stats_dynamic_inst = -1;
|
||||
this->stats_total_cycles = 0;
|
||||
this->stats_fwd_stalls = 0;
|
||||
this->stats_branch_stalls = 0;
|
||||
|
||||
}
|
||||
|
||||
bool Vortex_SOC::ibus_driver()
|
||||
{
|
||||
|
||||
return false;
|
||||
|
||||
}
|
||||
|
||||
void Vortex_SOC::io_handler()
|
||||
{
|
||||
// std::cout << "Checking\n";
|
||||
for (int c = 0; c < vortex->number_cores; c++)
|
||||
{
|
||||
if (vortex->io_valid[c])
|
||||
{
|
||||
uint32_t data_write = (uint32_t) vortex->io_data[c];
|
||||
// std::cout << "IO VALID!\n";
|
||||
char c = (char) data_write;
|
||||
std::cerr << c;
|
||||
// std::cout << c;
|
||||
|
||||
std::cout << std::flush;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
bool Vortex_SOC::dbus_driver()
|
||||
{
|
||||
|
||||
// Iterate through each element, and get pop index
|
||||
int dequeue_index = -1;
|
||||
bool dequeue_valid = false;
|
||||
for (int i = 0; i < this->dram_req_vec.size(); i++)
|
||||
{
|
||||
if (this->dram_req_vec[i].cycles_left > 0)
|
||||
{
|
||||
this->dram_req_vec[i].cycles_left -= 1;
|
||||
}
|
||||
|
||||
if ((this->dram_req_vec[i].cycles_left == 0) && (!dequeue_valid))
|
||||
{
|
||||
dequeue_index = i;
|
||||
dequeue_valid = true;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
if (vortex->out_dram_req)
|
||||
{
|
||||
if (vortex->out_dram_req_read)
|
||||
{
|
||||
// Need to add an element
|
||||
dram_req_t dram_req;
|
||||
dram_req.cycles_left = vortex->out_dram_expected_lat;
|
||||
dram_req.data_length = vortex->out_dram_req_size / 4;
|
||||
dram_req.base_addr = vortex->out_dram_req_addr;
|
||||
dram_req.data = (unsigned *) malloc(dram_req.data_length * sizeof(unsigned));
|
||||
|
||||
for (int i = 0; i < dram_req.data_length; i++)
|
||||
{
|
||||
unsigned curr_addr = dram_req.base_addr + (i*4);
|
||||
unsigned data_rd;
|
||||
ram->getWord(curr_addr, &data_rd);
|
||||
dram_req.data[i] = data_rd;
|
||||
}
|
||||
// std::cout << "Fill Req -> Addr: " << std::hex << dram_req.base_addr << std::dec << "\n";
|
||||
this->dram_req_vec.push_back(dram_req);
|
||||
}
|
||||
|
||||
if (vortex->out_dram_req_write)
|
||||
{
|
||||
unsigned base_addr = vortex->out_dram_req_addr;
|
||||
unsigned data_length = vortex->out_dram_req_size / 4;
|
||||
|
||||
for (int i = 0; i < data_length; i++)
|
||||
{
|
||||
unsigned curr_addr = base_addr + (i*4);
|
||||
unsigned data_wr = vortex->out_dram_req_data[i];
|
||||
ram->writeWord(curr_addr, &data_wr);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (vortex->out_dram_fill_accept && dequeue_valid)
|
||||
{
|
||||
vortex->out_dram_fill_rsp = 1;
|
||||
vortex->out_dram_fill_rsp_addr = this->dram_req_vec[dequeue_index].base_addr;
|
||||
// std::cout << "Fill Rsp -> Addr: " << std::hex << (this->dram_req_vec[dequeue_index].base_addr) << std::dec << "\n";
|
||||
|
||||
for (int i = 0; i < this->dram_req_vec[dequeue_index].data_length; i++)
|
||||
{
|
||||
vortex->out_dram_fill_rsp_data[i] = this->dram_req_vec[dequeue_index].data[i];
|
||||
}
|
||||
free(this->dram_req_vec[dequeue_index].data);
|
||||
|
||||
this->dram_req_vec.erase(this->dram_req_vec.begin() + dequeue_index);
|
||||
}
|
||||
else
|
||||
{
|
||||
vortex->out_dram_fill_rsp = 0;
|
||||
vortex->out_dram_fill_rsp_addr = 0;
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
|
||||
|
||||
bool Vortex_SOC::simulate()
|
||||
{
|
||||
// auto start_time = std::chrono::high_resolution_clock::now();
|
||||
|
||||
static bool stop = false;
|
||||
static int counter = 0;
|
||||
counter = 0;
|
||||
stop = false;
|
||||
|
||||
// auto start_time = clock();
|
||||
|
||||
|
||||
// vortex->reset = 1;
|
||||
|
||||
|
||||
// vortex->reset = 0;
|
||||
|
||||
unsigned curr_inst;
|
||||
unsigned new_PC;
|
||||
|
||||
// while (this->stop && (!(stop && (counter > 5))))
|
||||
// {
|
||||
|
||||
// // std::cout << "************* Cycle: " << cycle << "\n";
|
||||
// bool istop = ibus_driver();
|
||||
// bool dstop = !dbus_driver();
|
||||
|
||||
// vortex->clk = 1;
|
||||
// vortex->eval();
|
||||
|
||||
|
||||
|
||||
// vortex->clk = 0;
|
||||
// vortex->eval();
|
||||
|
||||
|
||||
// stop = istop && dstop;
|
||||
|
||||
// if (stop)
|
||||
// {
|
||||
// counter++;
|
||||
// } else
|
||||
// {
|
||||
// counter = 0;
|
||||
// }
|
||||
|
||||
// cycle++;
|
||||
// }
|
||||
|
||||
bool istop;
|
||||
bool dstop;
|
||||
bool cont = false;
|
||||
// for (int i = 0; i < 500; i++)
|
||||
|
||||
vortex->reset = 1;
|
||||
vortex->clk = 0;
|
||||
vortex->eval();
|
||||
// m_trace->dump(10);
|
||||
vortex->reset = 1;
|
||||
vortex->clk = 1;
|
||||
vortex->eval();
|
||||
// m_trace->dump(11);
|
||||
vortex->reset = 0;
|
||||
vortex->clk = 0;
|
||||
|
||||
// unsigned cycles;
|
||||
counter = 0;
|
||||
this->stats_total_cycles = 12;
|
||||
while (this->stop && ((counter < 5)))
|
||||
// while (this->stats_total_cycles < 10)
|
||||
{
|
||||
|
||||
// printf("-------------------------\n");
|
||||
// std::cout << "Counter: " << counter << "\n";
|
||||
// if ((this->stats_total_cycles) % 5000 == 0) std::cout << "************* Cycle: " << (this->stats_total_cycles) << "\n";
|
||||
// dstop = !dbus_driver();
|
||||
#ifdef VCD_OUTPUT
|
||||
m_trace->dump(2*this->stats_total_cycles);
|
||||
#endif
|
||||
vortex->clk = 1;
|
||||
vortex->eval();
|
||||
istop = ibus_driver();
|
||||
dstop = !dbus_driver();
|
||||
io_handler();
|
||||
|
||||
#ifdef VCD_OUTPUT
|
||||
m_trace->dump((2*this->stats_total_cycles)+1);
|
||||
#endif
|
||||
vortex->clk = 0;
|
||||
vortex->eval();
|
||||
// stop = istop && dstop;
|
||||
stop = vortex->out_ebreak;
|
||||
|
||||
if (stop || cont)
|
||||
// if (istop)
|
||||
{
|
||||
cont = true;
|
||||
counter++;
|
||||
} else
|
||||
{
|
||||
counter = 0;
|
||||
}
|
||||
|
||||
++time_stamp;
|
||||
++stats_total_cycles;
|
||||
}
|
||||
|
||||
std::cerr << "New Total Cycles: " << (this->stats_total_cycles) << "\n";
|
||||
|
||||
int status = 0;
|
||||
// int status = (unsigned int) vortex->Vortex_SOC__DOT__vx_back_end__DOT__VX_wb__DOT__last_data_wb & 0xf;
|
||||
|
||||
// std::cout << "Last wb: " << std::hex << ((unsigned int) vortex->Vortex__DOT__vx_back_end__DOT__VX_wb__DOT__last_data_wb) << "\n";
|
||||
|
||||
// std::cout << "Something: " << result << '\n';
|
||||
|
||||
// uint32_t status;
|
||||
// ram->getWord(0, &status);
|
||||
|
||||
this->print_stats();
|
||||
|
||||
|
||||
|
||||
return (status == 1);
|
||||
// return (1 == 1);
|
||||
}
|
||||
};
|
||||
Loading…
Add table
Add a link
Reference in a new issue