mirror of
https://github.com/vortexgpgpu/vortex.git
synced 2025-04-22 21:09:15 -04:00
Adding Altera Stratix 10 support
This commit is contained in:
Blaise Tine
parent
b2b8f190dd
commit
25df233005
59 changed files with 18526 additions and 5002 deletions
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@ -105,11 +105,19 @@
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`endif
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`ifndef LATENCY_FDIV
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`define LATENCY_FDIV 15
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`ifdef ALTERA_S10
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`define LATENCY_FDIV 34
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`else
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`define LATENCY_FDIV 20
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`endif
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`endif
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`ifndef LATENCY_FSQRT
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`define LATENCY_FSQRT 10
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`ifdef ALTERA_S10
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`define LATENCY_FSQRT 25
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`else
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`define LATENCY_FSQRT 15
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`endif
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`endif
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`ifndef LATENCY_ITOF
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@ -41,125 +41,32 @@ module VX_fp_addmul #(
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wire [31:0] result_mul;
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`ifdef QUARTUS
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twentynm_fp_mac mac_fp_add (
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// inputs
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.accumulate(),
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.chainin_overflow(),
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.chainin_invalid(),
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.chainin_underflow(),
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.chainin_inexact(),
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.ax(dataa[i]),
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.ay(datab[i]),
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.az(),
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.clk({2'b00, clk}),
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.ena({2'b00, enable}),
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.aclr({reset, reset}),
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.chainin(),
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// outputs
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.overflow(),
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.invalid(),
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.underflow(),
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.inexact(),
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.chainout_overflow(),
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.chainout_invalid(),
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.chainout_underflow(),
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.chainout_inexact(),
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.resulta(result_add),
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.chainout()
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acl_fadd fadd (
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.clk (clk),
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.areset (reset),
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.en (enable),
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.a (dataa[i]),
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.b (datab[i]),
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.q (result_add)
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);
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defparam mac_fp_add.operation_mode = "sp_add";
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defparam mac_fp_add.use_chainin = "false";
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defparam mac_fp_add.adder_subtract = "false";
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defparam mac_fp_add.ax_clock = "0";
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defparam mac_fp_add.ay_clock = "0";
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defparam mac_fp_add.az_clock = "none";
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defparam mac_fp_add.output_clock = "0";
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defparam mac_fp_add.accumulate_clock = "none";
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defparam mac_fp_add.ax_chainin_pl_clock = "none";
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defparam mac_fp_add.accum_pipeline_clock = "none";
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defparam mac_fp_add.mult_pipeline_clock = "none";
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defparam mac_fp_add.adder_input_clock = "0";
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defparam mac_fp_add.accum_adder_clock = "none";
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twentynm_fp_mac mac_fp_sub (
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// inputs
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.accumulate(),
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.chainin_overflow(),
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.chainin_invalid(),
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.chainin_underflow(),
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.chainin_inexact(),
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.ax(dataa[i]),
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.ay(datab[i]),
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.az(),
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.clk({2'b00, clk}),
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.ena({2'b00, enable}),
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.aclr({reset, reset}),
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.chainin(),
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// outputs
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.overflow(),
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.invalid(),
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.underflow(),
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.inexact(),
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.chainout_overflow(),
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.chainout_invalid(),
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.chainout_underflow(),
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.chainout_inexact(),
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.resulta(result_sub),
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.chainout()
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acl_fsub fsub (
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.clk (clk),
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.areset (reset),
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.en (enable),
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.a (dataa[i]),
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.b (datab[i]),
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.q (result_sub)
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);
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defparam mac_fp_sub.operation_mode = "sp_add";
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defparam mac_fp_sub.use_chainin = "false";
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defparam mac_fp_sub.adder_subtract = "true";
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defparam mac_fp_sub.ax_clock = "0";
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defparam mac_fp_sub.ay_clock = "0";
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defparam mac_fp_sub.az_clock = "none";
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defparam mac_fp_sub.output_clock = "0";
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defparam mac_fp_sub.accumulate_clock = "none";
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defparam mac_fp_sub.ax_chainin_pl_clock = "none";
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defparam mac_fp_sub.accum_pipeline_clock = "none";
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defparam mac_fp_sub.mult_pipeline_clock = "none";
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defparam mac_fp_sub.adder_input_clock = "0";
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defparam mac_fp_sub.accum_adder_clock = "none";
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twentynm_fp_mac mac_fp_mul (
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// inputs
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.accumulate(),
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.chainin_overflow(),
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.chainin_invalid(),
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.chainin_underflow(),
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.chainin_inexact(),
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.ax(),
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.ay(datab[i]),
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.az(dataa[i]),
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.clk({2'b00, clk}),
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.ena({2'b00, enable}),
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.aclr({reset, reset}),
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.chainin(),
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// outputs
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.overflow(),
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.invalid(),
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.underflow(),
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.inexact(),
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.chainout_overflow(),
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.chainout_invalid(),
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.chainout_underflow(),
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.chainout_inexact(),
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.resulta(result_mul),
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.chainout()
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acl_fmul fmul (
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.clk (clk),
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.areset (reset),
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.en (enable),
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.a (dataa[i]),
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.b (datab[i]),
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.q (result_mul)
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);
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defparam mac_fp_mul.operation_mode = "sp_mult";
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defparam mac_fp_mul.use_chainin = "false";
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defparam mac_fp_mul.adder_subtract = "false";
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defparam mac_fp_mul.ax_clock = "none";
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defparam mac_fp_mul.ay_clock = "0";
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defparam mac_fp_mul.az_clock = "0";
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defparam mac_fp_mul.output_clock = "0";
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defparam mac_fp_mul.accumulate_clock = "none";
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defparam mac_fp_mul.ax_chainin_pl_clock = "none";
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defparam mac_fp_mul.accum_pipeline_clock = "none";
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defparam mac_fp_mul.mult_pipeline_clock = "0";
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defparam mac_fp_mul.adder_input_clock = "none";
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defparam mac_fp_mul.accum_adder_clock = "none";
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`else
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integer fadd_h, fsub_h, fmul_h;
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initial begin
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@ -185,7 +92,7 @@ module VX_fp_addmul #(
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.clk(clk),
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.reset (reset),
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.enable (enable),
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.data_in ({valid_in, tag_in, do_sub, do_mul}),
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.data_in ({valid_in, tag_in, do_sub, do_mul}),
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.data_out ({valid_out, tag_out, do_sub_r, do_mul_r})
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);
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@ -41,85 +41,25 @@ module VX_fp_madd #(
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wire [31:0] result_msub;
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`ifdef QUARTUS
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twentynm_fp_mac mac_fp_madd (
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// inputs
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.accumulate(),
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.chainin_overflow(),
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.chainin_invalid(),
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.chainin_underflow(),
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.chainin_inexact(),
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.ax(datac[i]),
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.ay(datab[i]),
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.az(dataa[i]),
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.clk({2'b00, clk}),
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.ena({2'b00, enable}),
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.aclr({reset, reset}),
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.chainin(),
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// outputs
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.overflow(),
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.invalid(),
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.underflow(),
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.inexact(),
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.chainout_overflow(),
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.chainout_invalid(),
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.chainout_underflow(),
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.chainout_inexact(),
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.resulta(result_madd),
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.chainout()
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acl_fmadd fmadd (
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.clk (clk),
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.areset (reset),
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.en (enable),
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.a (dataa[i]),
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.b (datab[i]),
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.c (datac[i]),
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.q (result_madd)
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);
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defparam mac_fp_madd.operation_mode = "sp_mult_add";
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defparam mac_fp_madd.use_chainin = "false";
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defparam mac_fp_madd.adder_subtract = "false";
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defparam mac_fp_madd.ax_clock = "0";
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defparam mac_fp_madd.ay_clock = "0";
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defparam mac_fp_madd.az_clock = "0";
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defparam mac_fp_madd.output_clock = "0";
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defparam mac_fp_madd.accumulate_clock = "none";
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defparam mac_fp_madd.ax_chainin_pl_clock = "0";
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defparam mac_fp_madd.accum_pipeline_clock = "none";
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defparam mac_fp_madd.mult_pipeline_clock = "0";
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defparam mac_fp_madd.adder_input_clock = "0";
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defparam mac_fp_madd.accum_adder_clock = "none";
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twentynm_fp_mac mac_fp_msub (
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// inputs
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.accumulate(),
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.chainin_overflow(),
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.chainin_invalid(),
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.chainin_underflow(),
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.chainin_inexact(),
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.ax(datac[i]),
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.ay(datab[i]),
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.az(dataa[i]),
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.clk({2'b00, clk}),
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.ena({2'b00, enable}),
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.aclr({reset, reset}),
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.chainin(),
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// outputs
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.overflow(),
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.invalid(),
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.underflow(),
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.inexact(),
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.chainout_overflow(),
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.chainout_invalid(),
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.chainout_underflow(),
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.chainout_inexact(),
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.resulta(result_msub),
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.chainout()
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acl_fmsub fmsub (
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.clk (clk),
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.areset (reset),
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.en (enable),
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.a (dataa[i]),
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.b (datab[i]),
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.c (datac[i]),
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.q (result_msub)
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);
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defparam mac_fp_msub.operation_mode = "sp_mult_add";
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defparam mac_fp_msub.use_chainin = "false";
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defparam mac_fp_msub.adder_subtract = "true";
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defparam mac_fp_msub.ax_clock = "0";
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defparam mac_fp_msub.ay_clock = "0";
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defparam mac_fp_msub.az_clock = "0";
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defparam mac_fp_msub.output_clock = "0";
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defparam mac_fp_msub.accumulate_clock = "none";
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defparam mac_fp_msub.ax_chainin_pl_clock = "0";
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defparam mac_fp_msub.accum_pipeline_clock = "none";
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defparam mac_fp_msub.mult_pipeline_clock = "0";
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defparam mac_fp_msub.adder_input_clock = "0";
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defparam mac_fp_msub.accum_adder_clock = "none";
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`else
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integer fmadd_h, fmsub_h;
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initial begin
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@ -145,7 +85,7 @@ module VX_fp_madd #(
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.clk(clk),
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.reset (reset),
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.enable (enable),
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.data_in ({valid_in, tag_in, do_sub, do_neg}),
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.data_in ({valid_in, tag_in, do_sub, do_neg}),
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.data_out ({valid_out, tag_out, do_sub_r, do_neg_r})
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);
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Load diff
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:0201EB00011100
|
||||
:0201EC00010F01
|
||||
:0201ED00010E01
|
||||
:0201EE00010D01
|
||||
:0201EF00010C01
|
||||
:0201F000010B01
|
||||
:0201F100010902
|
||||
:0201F200010BFF
|
||||
:0201F300010801
|
||||
:0201F400010800
|
||||
:0201F500010601
|
||||
:0201F600010600
|
||||
:0201F7000107FE
|
||||
:0201F8000105FF
|
||||
:0201F900010300
|
||||
:0201FA00010200
|
||||
:0201FB000102FF
|
||||
:0201FC000103FD
|
||||
:0201FD000102FD
|
||||
:0201FE000100FE
|
||||
:0201FF000100FD
|
||||
:00000001ff
|
||||
File diff suppressed because it is too large
Load diff
|
|
@ -1,169 +0,0 @@
|
|||
starting execution ...
|
||||
build model options ...
|
||||
argc=21
|
||||
Generation context:
|
||||
HardFP is enabled enabling set to true
|
||||
Faithful rounding constraint detected
|
||||
Will not generate valid and channel signals
|
||||
The new component name is acl_s10_fdiv
|
||||
Frequency 250MHz
|
||||
Deployment FPGA Stratix10
|
||||
Estimated resources LUTs 681, DSPs 5, RAMBits 32768, RAMBlocks 3
|
||||
The pipeline depth of the block is 25 cycle(s)
|
||||
@@start
|
||||
@name FPDiv@
|
||||
@latency 25@
|
||||
@LUT 681@
|
||||
@DSP 5@
|
||||
@RAMBits 32768@
|
||||
@RAMBlockUsage 3@
|
||||
@enable 1@
|
||||
@subnormals 0@
|
||||
@error 1.00@
|
||||
@rounding NA@
|
||||
@method polynomial approximation@
|
||||
@inPort 0 fpieee 8 23@
|
||||
@inPort 1 fpieee 8 23@
|
||||
@outPort 0 fpieee 8 23@
|
||||
@nochanvalid 1@
|
||||
@@end
|
||||
starting execution ...
|
||||
build model options ...
|
||||
argc=20
|
||||
Generation context:
|
||||
HardFP is enabled enabling set to true
|
||||
Faithful rounding constraint detected
|
||||
Will not generate valid and channel signals
|
||||
The new component name is acl_s10_fsqrt
|
||||
Frequency 250MHz
|
||||
Deployment FPGA Stratix10
|
||||
Estimated resources LUTs 349, DSPs 3, RAMBits 15872, RAMBlocks 3
|
||||
The pipeline depth of the block is 17 cycle(s)
|
||||
@@start
|
||||
@name FPSqrt@
|
||||
@latency 17@
|
||||
@LUT 349@
|
||||
@DSP 3@
|
||||
@RAMBits 15872@
|
||||
@RAMBlockUsage 3@
|
||||
@enable 1@
|
||||
@subnormals 0@
|
||||
@error 1.00@
|
||||
@rounding NA@
|
||||
@method polynomial approximation@
|
||||
@inPort 0 fpieee 8 23@
|
||||
@outPort 0 fpieee 8 23@
|
||||
@nochanvalid 1@
|
||||
@@end
|
||||
starting execution ...
|
||||
build model options ...
|
||||
argc=23
|
||||
Generation context:
|
||||
HardFP is enabled enabling set to true
|
||||
Faithful rounding constraint detected
|
||||
Will not generate valid and channel signals
|
||||
The new component name is acl_s10_ftoi
|
||||
Frequency 250MHz
|
||||
Deployment FPGA Stratix10
|
||||
Estimated resources LUTs 344, DSPs 0, RAMBits 0, RAMBlocks 0
|
||||
The pipeline depth of the block is 3 cycle(s)
|
||||
@@start
|
||||
@name FPToFXP@
|
||||
@latency 3@
|
||||
@LUT 344@
|
||||
@DSP 0@
|
||||
@RAMBits 0@
|
||||
@RAMBlockUsage 0@
|
||||
@enable 1@
|
||||
@subnormals 0@
|
||||
@error 1.00@
|
||||
@rounding NA@
|
||||
@method default@
|
||||
@inPort 0 fpieee 8 23@
|
||||
@outPort 0 fxp 32 0 1@
|
||||
@nochanvalid 1@
|
||||
@@end
|
||||
starting execution ...
|
||||
build model options ...
|
||||
argc=23
|
||||
Generation context:
|
||||
HardFP is enabled enabling set to true
|
||||
Faithful rounding constraint detected
|
||||
Will not generate valid and channel signals
|
||||
The new component name is acl_s10_ftou
|
||||
Frequency 250MHz
|
||||
Deployment FPGA Stratix10
|
||||
Estimated resources LUTs 272, DSPs 0, RAMBits 0, RAMBlocks 0
|
||||
The pipeline depth of the block is 3 cycle(s)
|
||||
@@start
|
||||
@name FPToFXP@
|
||||
@latency 3@
|
||||
@LUT 272@
|
||||
@DSP 0@
|
||||
@RAMBits 0@
|
||||
@RAMBlockUsage 0@
|
||||
@enable 1@
|
||||
@subnormals 0@
|
||||
@error 1.00@
|
||||
@rounding NA@
|
||||
@method default@
|
||||
@inPort 0 fpieee 8 23@
|
||||
@outPort 0 fxp 32 0 0@
|
||||
@nochanvalid 1@
|
||||
@@end
|
||||
starting execution ...
|
||||
build model options ...
|
||||
argc=23
|
||||
Generation context:
|
||||
HardFP is enabled enabling set to true
|
||||
Faithful rounding constraint detected
|
||||
Will not generate valid and channel signals
|
||||
The new component name is acl_s10_itof
|
||||
Frequency 250MHz
|
||||
Deployment FPGA Stratix10
|
||||
Estimated resources LUTs 362, DSPs 0, RAMBits 0, RAMBlocks 0
|
||||
The pipeline depth of the block is 7 cycle(s)
|
||||
@@start
|
||||
@name FXPToFP@
|
||||
@latency 7@
|
||||
@LUT 362@
|
||||
@DSP 0@
|
||||
@RAMBits 0@
|
||||
@RAMBlockUsage 0@
|
||||
@enable 1@
|
||||
@subnormals 0@
|
||||
@error 1.00@
|
||||
@rounding NA@
|
||||
@method default@
|
||||
@inPort 0 fxp 32 0 1@
|
||||
@outPort 0 fpieee 8 23@
|
||||
@nochanvalid 1@
|
||||
@@end
|
||||
starting execution ...
|
||||
build model options ...
|
||||
argc=23
|
||||
Generation context:
|
||||
HardFP is enabled enabling set to true
|
||||
Faithful rounding constraint detected
|
||||
Will not generate valid and channel signals
|
||||
The new component name is acl_s10_utof
|
||||
Frequency 300MHz
|
||||
Deployment FPGA Stratix10
|
||||
Estimated resources LUTs 310, DSPs 0, RAMBits 0, RAMBlocks 0
|
||||
The pipeline depth of the block is 7 cycle(s)
|
||||
@@start
|
||||
@name FXPToFP@
|
||||
@latency 7@
|
||||
@LUT 310@
|
||||
@DSP 0@
|
||||
@RAMBits 0@
|
||||
@RAMBlockUsage 0@
|
||||
@enable 1@
|
||||
@subnormals 0@
|
||||
@error 1.00@
|
||||
@rounding NA@
|
||||
@method default@
|
||||
@inPort 0 fxp 32 0 0@
|
||||
@outPort 0 fpieee 8 23@
|
||||
@nochanvalid 1@
|
||||
@@end
|
||||
|
|
@ -1,25 +0,0 @@
|
|||
#!/bin/bash
|
||||
|
||||
CMD_POLY_EVAL_PATH=$QUARTUS_HOME/dspba/backend/linux64
|
||||
|
||||
OPTIONS="-target Stratix10 -lang verilog -enableHardFP 1 -printMachineReadable -faithfulRounding -noChanValid -enable -speedgrade 2"
|
||||
|
||||
export LD_LIBRARY_PATH=$CMD_POLY_EVAL_PATH:$LD_LIBRARY_PATH
|
||||
|
||||
CMD="$CMD_POLY_EVAL_PATH/cmdPolyEval $OPTIONS"
|
||||
|
||||
EXP_BITS=8
|
||||
MAN_BITS=23
|
||||
FBITS="f$(($EXP_BITS + $MAN_BITS + 1))"
|
||||
|
||||
echo Generating IP cores for $FBITS
|
||||
{
|
||||
$CMD -name acl_s10_fdiv -frequency 250 FPDiv $EXP_BITS $MAN_BITS 0
|
||||
$CMD -name acl_s10_fsqrt -frequency 250 FPSqrt $EXP_BITS $MAN_BITS
|
||||
$CMD -name acl_s10_ftoi -frequency 250 FPToFXP $EXP_BITS $MAN_BITS 32 0 1
|
||||
$CMD -name acl_s10_ftou -frequency 250 FPToFXP $EXP_BITS $MAN_BITS 32 0 0
|
||||
$CMD -name acl_s10_itof -frequency 250 FXPToFP 32 0 1 $EXP_BITS $MAN_BITS
|
||||
$CMD -name acl_s10_utof -frequency 300 FXPToFP 32 0 0 $EXP_BITS $MAN_BITS
|
||||
} > acl_gen.log 2>&1
|
||||
|
||||
#cp $QUARTUS_HOME/dspba/backend/Libraries/sv/base/dspba_library_ver.sv .
|
||||
67
hw/rtl/fp_cores/altera/arria10/acl_fadd.sv
Normal file
67
hw/rtl/fp_cores/altera/arria10/acl_fadd.sv
Normal file
|
|
@ -0,0 +1,67 @@
|
|||
// -------------------------------------------------------------------------
|
||||
// High Level Design Compiler for Intel(R) FPGAs Version 17.1 (Release Build #273)
|
||||
// Quartus Prime development tool and MATLAB/Simulink Interface
|
||||
//
|
||||
// Legal Notice: Copyright 2017 Intel Corporation. All rights reserved.
|
||||
// Your use of Intel Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly
|
||||
// subject to the terms and conditions of the Intel FPGA Software License
|
||||
// Agreement, Intel MegaCore Function License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for
|
||||
// the sole purpose of programming logic devices manufactured by Intel
|
||||
// and sold by Intel or its authorized distributors. Please refer to the
|
||||
// applicable agreement for further details.
|
||||
// ---------------------------------------------------------------------------
|
||||
|
||||
// SystemVerilog created from acl_fadd
|
||||
// SystemVerilog created on Sun Dec 27 09:47:20 2020
|
||||
|
||||
|
||||
(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *)
|
||||
module acl_fadd (
|
||||
input wire [31:0] a,
|
||||
input wire [31:0] b,
|
||||
input wire [0:0] en,
|
||||
output wire [31:0] q,
|
||||
input wire clk,
|
||||
input wire areset
|
||||
);
|
||||
|
||||
wire [31:0] fpAddTest_impl_ax0;
|
||||
wire [31:0] fpAddTest_impl_ay0;
|
||||
wire [31:0] fpAddTest_impl_q0;
|
||||
wire fpAddTest_impl_reset0;
|
||||
wire fpAddTest_impl_fpAddTest_impl_ena0;
|
||||
|
||||
|
||||
// fpAddTest_impl(FPCOLUMN,5)@0
|
||||
// out q0@3
|
||||
assign fpAddTest_impl_ax0 = b;
|
||||
assign fpAddTest_impl_ay0 = a;
|
||||
assign fpAddTest_impl_reset0 = areset;
|
||||
assign fpAddTest_impl_fpAddTest_impl_ena0 = en[0];
|
||||
twentynm_fp_mac #(
|
||||
.operation_mode("sp_add"),
|
||||
.ax_clock("0"),
|
||||
.ay_clock("0"),
|
||||
.adder_input_clock("0"),
|
||||
.output_clock("0")
|
||||
) fpAddTest_impl_DSP0 (
|
||||
.aclr({ fpAddTest_impl_reset0, fpAddTest_impl_reset0 }),
|
||||
.clk({1'b0,1'b0,clk}),
|
||||
.ena({ 1'b0, 1'b0, fpAddTest_impl_fpAddTest_impl_ena0 }),
|
||||
.ax(fpAddTest_impl_ax0),
|
||||
.ay(fpAddTest_impl_ay0),
|
||||
.resulta(fpAddTest_impl_q0),
|
||||
.accumulate(),
|
||||
.az(),
|
||||
.chainin(),
|
||||
.chainout()
|
||||
);
|
||||
|
||||
// xOut(GPOUT,4)@3
|
||||
assign q = fpAddTest_impl_q0;
|
||||
|
||||
endmodule
|
||||
2632
hw/rtl/fp_cores/altera/arria10/acl_fdiv.sv
Normal file
2632
hw/rtl/fp_cores/altera/arria10/acl_fdiv.sv
Normal file
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,514 @@
|
|||
:020000040000FA
|
||||
:0400000040000004B8
|
||||
:040001003FE00FFCD1
|
||||
:040002003FC03FC4F8
|
||||
:040003003FA08F2D5E
|
||||
:040004003F80FE0833
|
||||
:040005003F618C25A6
|
||||
:040006003F423958E4
|
||||
:040007003F2305711D
|
||||
:040008003F03F0437F
|
||||
:040009003EE4F9A137
|
||||
:04000A003EC6215D70
|
||||
:04000B003EA7674C59
|
||||
:04000C003E88CB401F
|
||||
:04000D003E6A4D0FEB
|
||||
:04000E003E4BEC8CED
|
||||
:04000F003E2DA98C4D
|
||||
:040010003E0F83E537
|
||||
:040011003DF17B6BD7
|
||||
:040012003DD38FF457
|
||||
:040013003DB5C157DF
|
||||
:040014003D980F6A9A
|
||||
:040015003D7A7A03B3
|
||||
:040016003D5D00F953
|
||||
:040017003D3FA424A1
|
||||
:040018003D22635CC6
|
||||
:040019003D053E77EC
|
||||
:04001A003CE8354F3A
|
||||
:04001B003CCB47BCD7
|
||||
:04001C003CAE7596EB
|
||||
:04001D003C91BEB79D
|
||||
:04001E003C7522F813
|
||||
:04001F003C58A23275
|
||||
:040020003C3C3C40E8
|
||||
:040021003C1FF0FC94
|
||||
:040022003C03C0409B
|
||||
:040023003BE7A9E727
|
||||
:040024003BCBADCC59
|
||||
:040025003BAFCBCA58
|
||||
:040026003B9403BD47
|
||||
:040027003B7855814C
|
||||
:040028003B5CC0F18C
|
||||
:040029003B4145EB27
|
||||
:04002A003B25E44A44
|
||||
:04002B003B0A9BEC05
|
||||
:04002C003AEF6CAD8E
|
||||
:04002D003AD4566CFF
|
||||
:04002E003AB959057D
|
||||
:04002F003A9E74562B
|
||||
:040030003A83A83E29
|
||||
:040031003A68F49B9A
|
||||
:040032003A4E594C9D
|
||||
:040033003A33D62F57
|
||||
:040034003A196B23E7
|
||||
:0400350039FF180770
|
||||
:0400360039E4DCBC11
|
||||
:0400370039CAB921E8
|
||||
:0400380039B0AD1618
|
||||
:040039003996B87BC1
|
||||
:04003A00397CDB3002
|
||||
:04003B0039631516FA
|
||||
:04003C003949660FC9
|
||||
:04003D00392FCDFA90
|
||||
:04003E0039164CBA69
|
||||
:04003F0038FCE22F78
|
||||
:0400400038E38E3DD6
|
||||
:0400410038CA50C4A5
|
||||
:0400420038B129A602
|
||||
:04004300389818C60B
|
||||
:04004400387F1E07DC
|
||||
:040045003866394C94
|
||||
:04004600384D6A7651
|
||||
:040047003834B16A2E
|
||||
:04004800381C0E0B47
|
||||
:040049003803803CBC
|
||||
:04004A0037EB07E1A8
|
||||
:04004B0037D2A4DE26
|
||||
:04004C0037BA571751
|
||||
:04004D0037A21E7147
|
||||
:04004E003789FACF25
|
||||
:04004F003771EC1702
|
||||
:040050003759F22DFD
|
||||
:0400510037420CF72F
|
||||
:04005200372A3C5AB3
|
||||
:040053003712803BA5
|
||||
:0400540036FAD88020
|
||||
:0400550036E3450E3B
|
||||
:0400560036CBC5CB15
|
||||
:0400570036B45A9FC2
|
||||
:04005800369D036E60
|
||||
:040059003685C01F09
|
||||
:04005A00366E909AD4
|
||||
:04005B00365774C4DC
|
||||
:04005C0036406C8539
|
||||
:04005D00362977C405
|
||||
:04005E003612966858
|
||||
:04005F0035FBC8584D
|
||||
:0400600035E50D7DF8
|
||||
:0400610035CE65BE75
|
||||
:0400620035B7D103DA
|
||||
:0400630035A14F3440
|
||||
:04006400358AE039C0
|
||||
:04006500357483FC6F
|
||||
:04006600355E3A6366
|
||||
:0400670035480358BD
|
||||
:040068003531DEC58B
|
||||
:04006900351BCC91E6
|
||||
:04006A003505CCA6E6
|
||||
:04006B0034EFDEEEA2
|
||||
:04006C0034DA03522D
|
||||
:04006D0034C439BBA3
|
||||
:04006E0034AE821317
|
||||
:04006F003498DC44A1
|
||||
:040070003483483855
|
||||
:04007100346DC5DA4B
|
||||
:040072003458551396
|
||||
:040073003442F5CF4F
|
||||
:04007400342DA7F789
|
||||
:0400750034186B765A
|
||||
:0400760034034038D7
|
||||
:0400770033EE262717
|
||||
:0400780033D91D2E2D
|
||||
:0400790033C425392E
|
||||
:04007A0033AF3E332F
|
||||
:04007B00339A680745
|
||||
:04007C003385A2A284
|
||||
:04007D003370EDEE01
|
||||
:04007E00335C49D9CD
|
||||
:04007F003347B64D00
|
||||
:0400800033333337AC
|
||||
:04008100331EC084E6
|
||||
:04008200330A5E1FC0
|
||||
:0400830032F60BF650
|
||||
:0400840032E1C9F4A8
|
||||
:0400850032CD9807D9
|
||||
:0400860032B9761CF9
|
||||
:0400870032A5641F1B
|
||||
:04008800329161FE52
|
||||
:04008900327D6FA5B0
|
||||
:04008A0032698D0347
|
||||
:04008B003255BA052B
|
||||
:04008C003241F6986F
|
||||
:04008D00322E42A924
|
||||
:04008E00321A9E285C
|
||||
:04008F00320709012A
|
||||
:0400900031F38323A2
|
||||
:0400910031E00C7CD2
|
||||
:0400920031CCA4FACF
|
||||
:0400930031B94C8BA8
|
||||
:0400940031A6031E70
|
||||
:040095003192C8A23A
|
||||
:04009600317F9D0514
|
||||
:04009700316C803513
|
||||
:040098003159722345
|
||||
:04009900314672BCBE
|
||||
:04009A00313381F08D
|
||||
:04009B0031209FAEC3
|
||||
:04009C00310DCBE572
|
||||
:04009D0030FB0685A9
|
||||
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|
||||
:0201F5000211F5
|
||||
:0201F600020FF6
|
||||
:0201F700020EF6
|
||||
:0201F800020CF7
|
||||
:0201F900020CF6
|
||||
:0201FA00020AF7
|
||||
:0201FB000207F9
|
||||
:0201FC000206F9
|
||||
:0201FD000205F9
|
||||
:0201FE000204F9
|
||||
:0201FF0001FFFE
|
||||
:00000001ff
|
||||
74
hw/rtl/fp_cores/altera/arria10/acl_fmadd.sv
Normal file
74
hw/rtl/fp_cores/altera/arria10/acl_fmadd.sv
Normal file
|
|
@ -0,0 +1,74 @@
|
|||
// -------------------------------------------------------------------------
|
||||
// High Level Design Compiler for Intel(R) FPGAs Version 17.1 (Release Build #273)
|
||||
// Quartus Prime development tool and MATLAB/Simulink Interface
|
||||
//
|
||||
// Legal Notice: Copyright 2017 Intel Corporation. All rights reserved.
|
||||
// Your use of Intel Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly
|
||||
// subject to the terms and conditions of the Intel FPGA Software License
|
||||
// Agreement, Intel MegaCore Function License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for
|
||||
// the sole purpose of programming logic devices manufactured by Intel
|
||||
// and sold by Intel or its authorized distributors. Please refer to the
|
||||
// applicable agreement for further details.
|
||||
// ---------------------------------------------------------------------------
|
||||
|
||||
// SystemVerilog created from acl_fmadd
|
||||
// SystemVerilog created on Sun Dec 27 09:47:20 2020
|
||||
|
||||
|
||||
(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *)
|
||||
module acl_fmadd (
|
||||
input wire [31:0] a,
|
||||
input wire [31:0] b,
|
||||
input wire [31:0] c,
|
||||
input wire [0:0] en,
|
||||
output wire [31:0] q,
|
||||
input wire clk,
|
||||
input wire areset
|
||||
);
|
||||
|
||||
wire [31:0] fpMultAddTest_impl_ax0;
|
||||
wire [31:0] fpMultAddTest_impl_ay0;
|
||||
wire [31:0] fpMultAddTest_impl_az0;
|
||||
wire [31:0] fpMultAddTest_impl_q0;
|
||||
wire fpMultAddTest_impl_reset0;
|
||||
wire fpMultAddTest_impl_fpMultAddTest_impl_ena0;
|
||||
|
||||
|
||||
// fpMultAddTest_impl(FPCOLUMN,5)@0
|
||||
// out q0@4
|
||||
assign fpMultAddTest_impl_ax0 = c;
|
||||
assign fpMultAddTest_impl_ay0 = b;
|
||||
assign fpMultAddTest_impl_az0 = a;
|
||||
assign fpMultAddTest_impl_reset0 = areset;
|
||||
assign fpMultAddTest_impl_fpMultAddTest_impl_ena0 = en[0];
|
||||
twentynm_fp_mac #(
|
||||
.operation_mode("sp_mult_add"),
|
||||
.use_chainin("false"),
|
||||
.ax_clock("0"),
|
||||
.ay_clock("0"),
|
||||
.az_clock("0"),
|
||||
.mult_pipeline_clock("0"),
|
||||
.adder_input_clock("0"),
|
||||
.ax_chainin_pl_clock("0"),
|
||||
.output_clock("0")
|
||||
) fpMultAddTest_impl_DSP0 (
|
||||
.aclr({ fpMultAddTest_impl_reset0, fpMultAddTest_impl_reset0 }),
|
||||
.clk({1'b0,1'b0,clk}),
|
||||
.ena({ 1'b0, 1'b0, fpMultAddTest_impl_fpMultAddTest_impl_ena0 }),
|
||||
.ax(fpMultAddTest_impl_ax0),
|
||||
.ay(fpMultAddTest_impl_ay0),
|
||||
.az(fpMultAddTest_impl_az0),
|
||||
.resulta(fpMultAddTest_impl_q0),
|
||||
.accumulate(),
|
||||
.chainin(),
|
||||
.chainout()
|
||||
);
|
||||
|
||||
// xOut(GPOUT,4)@4
|
||||
assign q = fpMultAddTest_impl_q0;
|
||||
|
||||
endmodule
|
||||
75
hw/rtl/fp_cores/altera/arria10/acl_fmsub.sv
Normal file
75
hw/rtl/fp_cores/altera/arria10/acl_fmsub.sv
Normal file
|
|
@ -0,0 +1,75 @@
|
|||
// -------------------------------------------------------------------------
|
||||
// High Level Design Compiler for Intel(R) FPGAs Version 17.1 (Release Build #273)
|
||||
// Quartus Prime development tool and MATLAB/Simulink Interface
|
||||
//
|
||||
// Legal Notice: Copyright 2017 Intel Corporation. All rights reserved.
|
||||
// Your use of Intel Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly
|
||||
// subject to the terms and conditions of the Intel FPGA Software License
|
||||
// Agreement, Intel MegaCore Function License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for
|
||||
// the sole purpose of programming logic devices manufactured by Intel
|
||||
// and sold by Intel or its authorized distributors. Please refer to the
|
||||
// applicable agreement for further details.
|
||||
// ---------------------------------------------------------------------------
|
||||
|
||||
// SystemVerilog created from acl_fmsub
|
||||
// SystemVerilog created on Sun Dec 27 07:07:02 2020
|
||||
|
||||
|
||||
(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *)
|
||||
module acl_fmsub (
|
||||
input wire [31:0] a,
|
||||
input wire [31:0] b,
|
||||
input wire [31:0] c,
|
||||
input wire [0:0] en,
|
||||
output wire [31:0] q,
|
||||
input wire clk,
|
||||
input wire areset
|
||||
);
|
||||
|
||||
wire [31:0] fpMultAddTest_impl_ax0;
|
||||
wire [31:0] fpMultAddTest_impl_ay0;
|
||||
wire [31:0] fpMultAddTest_impl_az0;
|
||||
wire [31:0] fpMultAddTest_impl_q0;
|
||||
wire fpMultAddTest_impl_reset0;
|
||||
wire fpMultAddTest_impl_fpMultAddTest_impl_ena0;
|
||||
|
||||
|
||||
// fpMultAddTest_impl(FPCOLUMN,5)@0
|
||||
// out q0@4
|
||||
assign fpMultAddTest_impl_ax0 = c;
|
||||
assign fpMultAddTest_impl_ay0 = b;
|
||||
assign fpMultAddTest_impl_az0 = a;
|
||||
assign fpMultAddTest_impl_reset0 = areset;
|
||||
assign fpMultAddTest_impl_fpMultAddTest_impl_ena0 = en[0];
|
||||
twentynm_fp_mac #(
|
||||
.operation_mode("sp_mult_add"),
|
||||
.adder_subtract("true"),
|
||||
.use_chainin("false"),
|
||||
.ax_clock("0"),
|
||||
.ay_clock("0"),
|
||||
.az_clock("0"),
|
||||
.mult_pipeline_clock("0"),
|
||||
.adder_input_clock("0"),
|
||||
.ax_chainin_pl_clock("0"),
|
||||
.output_clock("0")
|
||||
) fpMultAddTest_impl_DSP0 (
|
||||
.aclr({ fpMultAddTest_impl_reset0, fpMultAddTest_impl_reset0 }),
|
||||
.clk({1'b0,1'b0,clk}),
|
||||
.ena({ 1'b0, 1'b0, fpMultAddTest_impl_fpMultAddTest_impl_ena0 }),
|
||||
.ax(fpMultAddTest_impl_ax0),
|
||||
.ay(fpMultAddTest_impl_ay0),
|
||||
.az(fpMultAddTest_impl_az0),
|
||||
.resulta(fpMultAddTest_impl_q0),
|
||||
.accumulate(),
|
||||
.chainin(),
|
||||
.chainout()
|
||||
);
|
||||
|
||||
// xOut(GPOUT,4)@4
|
||||
assign q = fpMultAddTest_impl_q0;
|
||||
|
||||
endmodule
|
||||
67
hw/rtl/fp_cores/altera/arria10/acl_fmul.sv
Normal file
67
hw/rtl/fp_cores/altera/arria10/acl_fmul.sv
Normal file
|
|
@ -0,0 +1,67 @@
|
|||
// -------------------------------------------------------------------------
|
||||
// High Level Design Compiler for Intel(R) FPGAs Version 17.1 (Release Build #273)
|
||||
// Quartus Prime development tool and MATLAB/Simulink Interface
|
||||
//
|
||||
// Legal Notice: Copyright 2017 Intel Corporation. All rights reserved.
|
||||
// Your use of Intel Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly
|
||||
// subject to the terms and conditions of the Intel FPGA Software License
|
||||
// Agreement, Intel MegaCore Function License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for
|
||||
// the sole purpose of programming logic devices manufactured by Intel
|
||||
// and sold by Intel or its authorized distributors. Please refer to the
|
||||
// applicable agreement for further details.
|
||||
// ---------------------------------------------------------------------------
|
||||
|
||||
// SystemVerilog created from acl_fmul
|
||||
// SystemVerilog created on Sun Dec 27 09:47:20 2020
|
||||
|
||||
|
||||
(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *)
|
||||
module acl_fmul (
|
||||
input wire [31:0] a,
|
||||
input wire [31:0] b,
|
||||
input wire [0:0] en,
|
||||
output wire [31:0] q,
|
||||
input wire clk,
|
||||
input wire areset
|
||||
);
|
||||
|
||||
wire [31:0] fpMulTest_impl_ay0;
|
||||
wire [31:0] fpMulTest_impl_az0;
|
||||
wire [31:0] fpMulTest_impl_q0;
|
||||
wire fpMulTest_impl_reset0;
|
||||
wire fpMulTest_impl_fpMulTest_impl_ena0;
|
||||
|
||||
|
||||
// fpMulTest_impl(FPCOLUMN,5)@0
|
||||
// out q0@3
|
||||
assign fpMulTest_impl_ay0 = b;
|
||||
assign fpMulTest_impl_az0 = a;
|
||||
assign fpMulTest_impl_reset0 = areset;
|
||||
assign fpMulTest_impl_fpMulTest_impl_ena0 = en[0];
|
||||
twentynm_fp_mac #(
|
||||
.operation_mode("sp_mult"),
|
||||
.ay_clock("0"),
|
||||
.az_clock("0"),
|
||||
.mult_pipeline_clock("0"),
|
||||
.output_clock("0")
|
||||
) fpMulTest_impl_DSP0 (
|
||||
.aclr({ fpMulTest_impl_reset0, fpMulTest_impl_reset0 }),
|
||||
.clk({1'b0,1'b0,clk}),
|
||||
.ena({ 1'b0, 1'b0, fpMulTest_impl_fpMulTest_impl_ena0 }),
|
||||
.ay(fpMulTest_impl_ay0),
|
||||
.az(fpMulTest_impl_az0),
|
||||
.resulta(fpMulTest_impl_q0),
|
||||
.accumulate(),
|
||||
.ax(),
|
||||
.chainin(),
|
||||
.chainout()
|
||||
);
|
||||
|
||||
// xOut(GPOUT,4)@3
|
||||
assign q = fpMulTest_impl_q0;
|
||||
|
||||
endmodule
|
||||
1491
hw/rtl/fp_cores/altera/arria10/acl_fsqrt.sv
Normal file
1491
hw/rtl/fp_cores/altera/arria10/acl_fsqrt.sv
Normal file
File diff suppressed because it is too large
Load diff
|
|
@ -127,132 +127,132 @@
|
|||
:04007D000B3F49F3F9
|
||||
:04007E000B44F93AFC
|
||||
:04007F000B4AA5A5DE
|
||||
:040080000B504F3C96
|
||||
:040081000B5B99E894
|
||||
:040082000B66D966CA
|
||||
:040083000B720DD619
|
||||
:040084000B7D375861
|
||||
:040085000B88560E80
|
||||
:040086000B936A145A
|
||||
:040087000B9E738ACF
|
||||
:040088000BA97290BE
|
||||
:040089000BB4673E0F
|
||||
:04008A000BBF51B6A1
|
||||
:04008B000BCA321456
|
||||
:04008C000BD5087018
|
||||
:04008D000BDFD4EAC7
|
||||
:04008E000BEA979A48
|
||||
:04008F000BF5509C81
|
||||
:040090000C00000858
|
||||
:040091000C0AA5FAB6
|
||||
:040092000C1542887F
|
||||
:040093000C1FD5CE9B
|
||||
:040094000C2A5FE2F1
|
||||
:040095000C34E0DC6B
|
||||
:040096000C3F58D4EF
|
||||
:040097000C49C7E267
|
||||
:040098000C542E1ABC
|
||||
:040099000C5E8B96D8
|
||||
:04009A000C68E068A6
|
||||
:04009B000C732CA610
|
||||
:04009C000C7D7068FF
|
||||
:04009D000C87ABC25F
|
||||
:04009E000C91DEC81B
|
||||
:04009F000C9C098C20
|
||||
:0400A0000CA62C2658
|
||||
:0400A1000CB046A6B3
|
||||
:0400A2000CBA592219
|
||||
:0400A3000CC463AC7A
|
||||
:0400A4000CCE6654C4
|
||||
:0400A5000CD86132E0
|
||||
:0400A6000CE25454C0
|
||||
:0400A7000CEC3FCC52
|
||||
:0400A8000CF623AE81
|
||||
:0400A9000D0000083E
|
||||
:0400AA000D09D4EE7A
|
||||
:0400AB000D13A2701F
|
||||
:0400AC000D1D689E20
|
||||
:0400AD000D2727886C
|
||||
:0400AE000D30DF3EF4
|
||||
:0400AF000D3A8FD2A5
|
||||
:0400B0000D44395270
|
||||
:0400B1000D4DDBCE48
|
||||
:0400B2000D5777541B
|
||||
:0400B3000D610BF4DC
|
||||
:0400B4000D6A99BC7C
|
||||
:0400B5000D7420BCEA
|
||||
:0400B6000D7DA10219
|
||||
:0400B7000D871A9CFB
|
||||
:0400B8000D908D9684
|
||||
:0400B9000D99FA00A3
|
||||
:0400BA000DA35FE84B
|
||||
:0400BB000DACBF5A6F
|
||||
:0400BC000DB6186401
|
||||
:0400BD000DBF6B12F6
|
||||
:0400BE000DC8B7743E
|
||||
:0400BF000DD1FD92D0
|
||||
:0400C0000DDB3D7C9B
|
||||
:0400C1000DE4773E95
|
||||
:0400C2000DEDAAE2B4
|
||||
:0400C3000DF6D878E6
|
||||
:0400C4000E00000822
|
||||
:0400C5000E0921A05F
|
||||
:0400C6000E123D4C8D
|
||||
:0400C7000E1B5314A5
|
||||
:0400C8000E24630897
|
||||
:0400C9000E2D6D305B
|
||||
:0400CA000E36719AE3
|
||||
:0400CB000E3F704E26
|
||||
:0400CC000E4869561B
|
||||
:0400CD000E515CC0B4
|
||||
:0400CE000E5A4A96E6
|
||||
:0400CF000E6332E0AA
|
||||
:0400D0000E6C15AAF3
|
||||
:0400D1000E74F2FEB9
|
||||
:0400D2000E7DCAE6EF
|
||||
:0400D3000E869D6C8C
|
||||
:0400D4000E8F6A9889
|
||||
:0400D5000E983276D9
|
||||
:0400D6000EA0F51073
|
||||
:0400D7000EA9B26C50
|
||||
:0400D8000EB26A9862
|
||||
:0400D9000EBB1D98A5
|
||||
:0400DA000EC3CB7A0C
|
||||
:0400DB000ECC74448F
|
||||
:0400DC000ED5180025
|
||||
:0400DD000EDDB6B6C8
|
||||
:0400DE000EE650706A
|
||||
:0400DF000EEEE53606
|
||||
:0400E0000EF7751092
|
||||
:0400E1000F00000804
|
||||
:0400E2000F08862459
|
||||
:0400E3000F11076E84
|
||||
:0400E4000F1983EE7F
|
||||
:0400E5000F21FBAC40
|
||||
:0400E6000F2A6EAEC1
|
||||
:0400E7000F32DD00F7
|
||||
:0400E8000F3B46A4E0
|
||||
:0400E9000F43ABA86E
|
||||
:0400EA000F4C0C109B
|
||||
:0400EB000F5467E463
|
||||
:0400EC000F5CBF2ABC
|
||||
:0400ED000F6511EE9C
|
||||
:0400EE000F6D603200
|
||||
:0400EF000F75AA02DD
|
||||
:0400F0000F7DEF6031
|
||||
:0400F1000F863058EE
|
||||
:0400F2000F8E6CEE13
|
||||
:0400F3000F96A52A95
|
||||
:0400F4000F9ED9146E
|
||||
:0400F5000FA708B099
|
||||
:0400F6000FAF34060E
|
||||
:0400F7000FB75B1EC6
|
||||
:0400F8000FBF7DFEBB
|
||||
:0400F9000FC79CACE5
|
||||
:0400FA000FCFB72C41
|
||||
:0400FB000FD7CD8AC4
|
||||
:0400FC000FDFDFC86B
|
||||
:0400FD000FE7EDEC30
|
||||
:0400FE000FEFF80008
|
||||
:0400FF000FF7FE08F1
|
||||
:040080000B504F379B
|
||||
:040081000B5B99E498
|
||||
:040082000B66D962CE
|
||||
:040083000B720DD21D
|
||||
:040084000B7D375564
|
||||
:040085000B88560A84
|
||||
:040086000B936A105E
|
||||
:040087000B9E7387D2
|
||||
:040088000BA9728BC3
|
||||
:040089000BB4673B12
|
||||
:04008A000BBF51B3A4
|
||||
:04008B000BCA32105A
|
||||
:04008C000BD5086D1B
|
||||
:04008D000BDFD4E6CB
|
||||
:04008E000BEA97964C
|
||||
:04008F000BF5509885
|
||||
:040090000C0000045C
|
||||
:040091000C0AA5F5BB
|
||||
:040092000C15428483
|
||||
:040093000C1FD5CA9F
|
||||
:040094000C2A5FDEF5
|
||||
:040095000C34E0D86F
|
||||
:040096000C3F58D1F2
|
||||
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|
|
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:0200B6000CAE8E
|
||||
:0200B7000CB685
|
||||
:0200B8000CB882
|
||||
:0200B9000CC079
|
||||
:0200BA000CC870
|
||||
:0200B0000C80C2
|
||||
:0200B1000C8BB6
|
||||
:0200B2000C91AF
|
||||
:0200B3000C99A6
|
||||
:0200B4000CA19D
|
||||
:0200B5000CA796
|
||||
:0200B6000CAC90
|
||||
:0200B7000CB388
|
||||
:0200B8000CBC7E
|
||||
:0200B9000CC277
|
||||
:0200BA000CC771
|
||||
:0200BB000CCE69
|
||||
:0200BC000CD462
|
||||
:0200BC000CD660
|
||||
:0200BD000CDC59
|
||||
:0200BE000CE450
|
||||
:0200BE000CE153
|
||||
:0200BF000CE84B
|
||||
:0200C0000CF042
|
||||
:0200C1000CF43D
|
||||
:0200C0000CED45
|
||||
:0200C1000CF73A
|
||||
:0200C2000CFA36
|
||||
:0200C3000D022C
|
||||
:0200C4000D0627
|
||||
:0200C5000D0A22
|
||||
:0200C6000D1417
|
||||
:0200C7000D1614
|
||||
:0200C8000D1C0D
|
||||
:0200C9000D2404
|
||||
:0200CA000D2CFB
|
||||
:0200CB000D2EF8
|
||||
:0200CC000D30F5
|
||||
:0200CD000D38EC
|
||||
:0200C4000D0726
|
||||
:0200C5000D0D1F
|
||||
:0200C6000D1318
|
||||
:0200C7000D1911
|
||||
:0200C8000D1E0B
|
||||
:0200C9000D2305
|
||||
:0200CA000D2700
|
||||
:0200CB000D2FF7
|
||||
:0200CC000D35F0
|
||||
:0200CD000D3AEA
|
||||
:0200CE000D3EE5
|
||||
:0200CF000D42E0
|
||||
:0200D0000D46DB
|
||||
:0200D1000D4CD4
|
||||
:0200D2000D54CB
|
||||
:0200D3000D58C6
|
||||
:0200D4000D5AC3
|
||||
:0200D5000D60BC
|
||||
:0200D6000D66B5
|
||||
:0200D7000D66B4
|
||||
:0200D8000D70A9
|
||||
:0200D0000D47DA
|
||||
:0200D1000D4DD3
|
||||
:0200D2000D51CE
|
||||
:0200D3000D55C9
|
||||
:0200D4000D59C4
|
||||
:0200D5000D5EBE
|
||||
:0200D6000D63B8
|
||||
:0200D7000D68B2
|
||||
:0200D8000D6CAD
|
||||
:0200D9000D72A6
|
||||
:0200DA000D789F
|
||||
:0200DB000D7C9A
|
||||
:0200DC000D7E97
|
||||
:0200DC000D7F96
|
||||
:0200DD000D8292
|
||||
:0200DE000D868D
|
||||
:0200DF000D8A88
|
||||
:0200E0000D8E83
|
||||
:0200E1000D947C
|
||||
:0200E2000D9679
|
||||
:0200E3000D9A74
|
||||
:0200E4000DA26B
|
||||
:0200E5000DA468
|
||||
:0200E6000DA467
|
||||
:0200E7000DAE5C
|
||||
:0200E8000DB059
|
||||
:0200E9000DB652
|
||||
:0200EA000DBC4B
|
||||
:0200DF000D8C86
|
||||
:0200E0000D9180
|
||||
:0200E1000D937D
|
||||
:0200E2000D9B74
|
||||
:0200E3000D9E70
|
||||
:0200E4000D9F6E
|
||||
:0200E5000DA864
|
||||
:0200E6000DA863
|
||||
:0200E7000DAD5D
|
||||
:0200E8000DB257
|
||||
:0200E9000DB454
|
||||
:0200EA000DB750
|
||||
:0200EB000DBC4A
|
||||
:0200EC000DC045
|
||||
:0200ED000DC440
|
||||
:0200EE000DC241
|
||||
:0200EF000DCA38
|
||||
:0200F0000DCC35
|
||||
:0200EC000DBF46
|
||||
:0200ED000DC143
|
||||
:0200EE000DC53E
|
||||
:0200EF000DCB37
|
||||
:0200F0000DCE33
|
||||
:0200F1000DD030
|
||||
:0200F2000DD22D
|
||||
:0200F3000DD826
|
||||
:0200F2000DD728
|
||||
:0200F3000DDA24
|
||||
:0200F4000DDC21
|
||||
:0200F5000DDC20
|
||||
:0200F6000DDE1D
|
||||
:0200F7000DE416
|
||||
:0200F8000DEC0D
|
||||
:0200F5000DDF1D
|
||||
:0200F6000DE417
|
||||
:0200F7000DE713
|
||||
:0200F8000DE910
|
||||
:0200F9000DEC0C
|
||||
:0200FA000DEE09
|
||||
:0200FB000DF600
|
||||
:0200FC000DF401
|
||||
:0200FD000DF6FE
|
||||
:0200FE000DF8FB
|
||||
:0200FF000E02EF
|
||||
:0200FB000DF006
|
||||
:0200FC000DF500
|
||||
:0200FD000DF9FB
|
||||
:0200FE000DFCF7
|
||||
:0200FF000DFFF3
|
||||
:00000001ff
|
||||
68
hw/rtl/fp_cores/altera/arria10/acl_fsub.sv
Normal file
68
hw/rtl/fp_cores/altera/arria10/acl_fsub.sv
Normal file
|
|
@ -0,0 +1,68 @@
|
|||
// -------------------------------------------------------------------------
|
||||
// High Level Design Compiler for Intel(R) FPGAs Version 17.1 (Release Build #273)
|
||||
// Quartus Prime development tool and MATLAB/Simulink Interface
|
||||
//
|
||||
// Legal Notice: Copyright 2017 Intel Corporation. All rights reserved.
|
||||
// Your use of Intel Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly
|
||||
// subject to the terms and conditions of the Intel FPGA Software License
|
||||
// Agreement, Intel MegaCore Function License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for
|
||||
// the sole purpose of programming logic devices manufactured by Intel
|
||||
// and sold by Intel or its authorized distributors. Please refer to the
|
||||
// applicable agreement for further details.
|
||||
// ---------------------------------------------------------------------------
|
||||
|
||||
// SystemVerilog created from acl_fsub
|
||||
// SystemVerilog created on Sun Dec 27 09:47:20 2020
|
||||
|
||||
|
||||
(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *)
|
||||
module acl_fsub (
|
||||
input wire [31:0] a,
|
||||
input wire [31:0] b,
|
||||
input wire [0:0] en,
|
||||
output wire [31:0] q,
|
||||
input wire clk,
|
||||
input wire areset
|
||||
);
|
||||
|
||||
wire [31:0] fpSubTest_impl_ax0;
|
||||
wire [31:0] fpSubTest_impl_ay0;
|
||||
wire [31:0] fpSubTest_impl_q0;
|
||||
wire fpSubTest_impl_reset0;
|
||||
wire fpSubTest_impl_fpSubTest_impl_ena0;
|
||||
|
||||
|
||||
// fpSubTest_impl(FPCOLUMN,5)@0
|
||||
// out q0@3
|
||||
assign fpSubTest_impl_ax0 = b;
|
||||
assign fpSubTest_impl_ay0 = a;
|
||||
assign fpSubTest_impl_reset0 = areset;
|
||||
assign fpSubTest_impl_fpSubTest_impl_ena0 = en[0];
|
||||
twentynm_fp_mac #(
|
||||
.operation_mode("sp_add"),
|
||||
.adder_subtract("true"),
|
||||
.ax_clock("0"),
|
||||
.ay_clock("0"),
|
||||
.adder_input_clock("0"),
|
||||
.output_clock("0")
|
||||
) fpSubTest_impl_DSP0 (
|
||||
.aclr({ fpSubTest_impl_reset0, fpSubTest_impl_reset0 }),
|
||||
.clk({1'b0,1'b0,clk}),
|
||||
.ena({ 1'b0, 1'b0, fpSubTest_impl_fpSubTest_impl_ena0 }),
|
||||
.ax(fpSubTest_impl_ax0),
|
||||
.ay(fpSubTest_impl_ay0),
|
||||
.resulta(fpSubTest_impl_q0),
|
||||
.accumulate(),
|
||||
.az(),
|
||||
.chainin(),
|
||||
.chainout()
|
||||
);
|
||||
|
||||
// xOut(GPOUT,4)@3
|
||||
assign q = fpSubTest_impl_q0;
|
||||
|
||||
endmodule
|
||||
|
|
@ -16,7 +16,7 @@
|
|||
// ---------------------------------------------------------------------------
|
||||
|
||||
// SystemVerilog created from acl_ftoi
|
||||
// SystemVerilog created on Wed Dec 9 01:17:51 2020
|
||||
// SystemVerilog created on Sun Dec 27 09:47:21 2020
|
||||
|
||||
|
||||
(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *)
|
||||
|
|
@ -16,7 +16,7 @@
|
|||
// ---------------------------------------------------------------------------
|
||||
|
||||
// SystemVerilog created from acl_ftou
|
||||
// SystemVerilog created on Wed Dec 9 01:17:51 2020
|
||||
// SystemVerilog created on Sun Dec 27 09:47:21 2020
|
||||
|
||||
|
||||
(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *)
|
||||
296
hw/rtl/fp_cores/altera/arria10/acl_gen.log
Normal file
296
hw/rtl/fp_cores/altera/arria10/acl_gen.log
Normal file
|
|
@ -0,0 +1,296 @@
|
|||
starting execution ...
|
||||
build model options ...
|
||||
argc=22
|
||||
Generation context:
|
||||
Will not generate valid and channel signals
|
||||
HardFP is enabled enabling set to true
|
||||
Correct rounding constraint detected
|
||||
Will not generate valid and channel signals
|
||||
The new component name is acl_fadd
|
||||
Frequency 250MHz
|
||||
Deployment FPGA Arria10
|
||||
Estimated resources LUTs 0, DSPs 2, RAMBits 0, RAMBlocks 0
|
||||
The pipeline depth of the block is 3 cycle(s)
|
||||
@@start
|
||||
@name FPAdd@
|
||||
@latency 3@
|
||||
@LUT 0@
|
||||
@DSP 2@
|
||||
@RAMBits 0@
|
||||
@RAMBlockUsage 0@
|
||||
@enable 1@
|
||||
@subnormals 0@
|
||||
@error 0.50@
|
||||
@rounding RNE@
|
||||
@method single path@
|
||||
@inPort 0 fpieee 8 23@
|
||||
@inPort 1 fpieee 8 23@
|
||||
@outPort 0 fpieee 8 23@
|
||||
@nochanvalid 1@
|
||||
@@end
|
||||
starting execution ...
|
||||
build model options ...
|
||||
argc=22
|
||||
Generation context:
|
||||
Will not generate valid and channel signals
|
||||
HardFP is enabled enabling set to true
|
||||
Correct rounding constraint detected
|
||||
Will not generate valid and channel signals
|
||||
The new component name is acl_fsub
|
||||
Frequency 250MHz
|
||||
Deployment FPGA Arria10
|
||||
Estimated resources LUTs 0, DSPs 2, RAMBits 0, RAMBlocks 0
|
||||
The pipeline depth of the block is 3 cycle(s)
|
||||
@@start
|
||||
@name FPSub@
|
||||
@latency 3@
|
||||
@LUT 0@
|
||||
@DSP 2@
|
||||
@RAMBits 0@
|
||||
@RAMBlockUsage 0@
|
||||
@enable 1@
|
||||
@subnormals 0@
|
||||
@error 0.50@
|
||||
@rounding RNE@
|
||||
@method single path@
|
||||
@inPort 0 fpieee 8 23@
|
||||
@inPort 1 fpieee 8 23@
|
||||
@outPort 0 fpieee 8 23@
|
||||
@nochanvalid 1@
|
||||
@@end
|
||||
starting execution ...
|
||||
build model options ...
|
||||
argc=22
|
||||
Generation context:
|
||||
Will not generate valid and channel signals
|
||||
HardFP is enabled enabling set to true
|
||||
Correct rounding constraint detected
|
||||
Will not generate valid and channel signals
|
||||
The new component name is acl_fmul
|
||||
Frequency 250MHz
|
||||
Deployment FPGA Arria10
|
||||
Estimated resources LUTs 0, DSPs 2, RAMBits 0, RAMBlocks 0
|
||||
The pipeline depth of the block is 3 cycle(s)
|
||||
@@start
|
||||
@name FPMul@
|
||||
@latency 3@
|
||||
@LUT 0@
|
||||
@DSP 2@
|
||||
@RAMBits 0@
|
||||
@RAMBlockUsage 0@
|
||||
@enable 1@
|
||||
@subnormals 0@
|
||||
@error 0.50@
|
||||
@rounding RNE@
|
||||
@method default@
|
||||
@inPort 0 fpieee 8 23@
|
||||
@inPort 1 fpieee 8 23@
|
||||
@outPort 0 fpieee 8 23@
|
||||
@nochanvalid 1@
|
||||
@@end
|
||||
starting execution ...
|
||||
build model options ...
|
||||
argc=22
|
||||
Generation context:
|
||||
Will not generate valid and channel signals
|
||||
HardFP is enabled enabling set to true
|
||||
Correct rounding constraint detected
|
||||
Will not generate valid and channel signals
|
||||
The new component name is acl_fmadd
|
||||
Frequency 250MHz
|
||||
Deployment FPGA Arria10
|
||||
Estimated resources LUTs 0, DSPs 2, RAMBits 0, RAMBlocks 0
|
||||
The pipeline depth of the block is 4 cycle(s)
|
||||
@@start
|
||||
@name FPMultAdd@
|
||||
@latency 4@
|
||||
@LUT 0@
|
||||
@DSP 2@
|
||||
@RAMBits 0@
|
||||
@RAMBlockUsage 0@
|
||||
@enable 1@
|
||||
@subnormals 0@
|
||||
@error 0.50@
|
||||
@rounding RNE@
|
||||
@method multadd@
|
||||
@inPort 0 fpieee 8 23@
|
||||
@inPort 1 fpieee 8 23@
|
||||
@inPort 2 fpieee 8 23@
|
||||
@outPort 0 fpieee 8 23@
|
||||
@nochanvalid 1@
|
||||
@@end
|
||||
starting execution ...
|
||||
build model options ...
|
||||
argc=23
|
||||
Generation context:
|
||||
Will not generate valid and channel signals
|
||||
HardFP is enabled enabling set to true
|
||||
Correct rounding constraint detected
|
||||
Will not generate valid and channel signals
|
||||
The new component name is acl_fdiv
|
||||
Frequency 250MHz
|
||||
Deployment FPGA Arria10
|
||||
Estimated resources LUTs 1067, DSPs 7, RAMBits 34304, RAMBlocks 3
|
||||
The pipeline depth of the block is 20 cycle(s)
|
||||
@@start
|
||||
@name FPDiv@
|
||||
@latency 20@
|
||||
@LUT 1067@
|
||||
@DSP 7@
|
||||
@RAMBits 34304@
|
||||
@RAMBlockUsage 3@
|
||||
@enable 1@
|
||||
@subnormals 0@
|
||||
@error 0.50@
|
||||
@rounding RNE@
|
||||
@method polynomial approximation@
|
||||
@inPort 0 fpieee 8 23@
|
||||
@inPort 1 fpieee 8 23@
|
||||
@outPort 0 fpieee 8 23@
|
||||
@nochanvalid 1@
|
||||
@@end
|
||||
starting execution ...
|
||||
build model options ...
|
||||
argc=22
|
||||
Generation context:
|
||||
Will not generate valid and channel signals
|
||||
HardFP is enabled enabling set to true
|
||||
Correct rounding constraint detected
|
||||
Will not generate valid and channel signals
|
||||
The new component name is acl_fsqrt
|
||||
Frequency 250MHz
|
||||
Deployment FPGA Arria10
|
||||
Estimated resources LUTs 518, DSPs 5, RAMBits 15872, RAMBlocks 3
|
||||
The pipeline depth of the block is 15 cycle(s)
|
||||
@@start
|
||||
@name FPSqrt@
|
||||
@latency 15@
|
||||
@LUT 518@
|
||||
@DSP 5@
|
||||
@RAMBits 15872@
|
||||
@RAMBlockUsage 3@
|
||||
@enable 1@
|
||||
@subnormals 0@
|
||||
@error 0.50@
|
||||
@rounding RNE@
|
||||
@method polynomial approximation@
|
||||
@inPort 0 fpieee 8 23@
|
||||
@outPort 0 fpieee 8 23@
|
||||
@nochanvalid 1@
|
||||
@@end
|
||||
starting execution ...
|
||||
build model options ...
|
||||
argc=25
|
||||
Generation context:
|
||||
Will not generate valid and channel signals
|
||||
HardFP is enabled enabling set to true
|
||||
Correct rounding constraint detected
|
||||
Will not generate valid and channel signals
|
||||
The new component name is acl_ftoi
|
||||
Frequency 250MHz
|
||||
Deployment FPGA Arria10
|
||||
Estimated resources LUTs 327, DSPs 0, RAMBits 0, RAMBlocks 0
|
||||
The pipeline depth of the block is 3 cycle(s)
|
||||
@@start
|
||||
@name FPToFXP@
|
||||
@latency 3@
|
||||
@LUT 327@
|
||||
@DSP 0@
|
||||
@RAMBits 0@
|
||||
@RAMBlockUsage 0@
|
||||
@enable 1@
|
||||
@subnormals 0@
|
||||
@error 0.50@
|
||||
@rounding RNE@
|
||||
@method default@
|
||||
@inPort 0 fpieee 8 23@
|
||||
@outPort 0 fxp 32 0 1@
|
||||
@nochanvalid 1@
|
||||
@@end
|
||||
starting execution ...
|
||||
build model options ...
|
||||
argc=25
|
||||
Generation context:
|
||||
Will not generate valid and channel signals
|
||||
HardFP is enabled enabling set to true
|
||||
Correct rounding constraint detected
|
||||
Will not generate valid and channel signals
|
||||
The new component name is acl_ftou
|
||||
Frequency 250MHz
|
||||
Deployment FPGA Arria10
|
||||
Estimated resources LUTs 287, DSPs 0, RAMBits 0, RAMBlocks 0
|
||||
The pipeline depth of the block is 3 cycle(s)
|
||||
@@start
|
||||
@name FPToFXP@
|
||||
@latency 3@
|
||||
@LUT 287@
|
||||
@DSP 0@
|
||||
@RAMBits 0@
|
||||
@RAMBlockUsage 0@
|
||||
@enable 1@
|
||||
@subnormals 0@
|
||||
@error 0.50@
|
||||
@rounding RNE@
|
||||
@method default@
|
||||
@inPort 0 fpieee 8 23@
|
||||
@outPort 0 fxp 32 0 0@
|
||||
@nochanvalid 1@
|
||||
@@end
|
||||
starting execution ...
|
||||
build model options ...
|
||||
argc=25
|
||||
Generation context:
|
||||
Will not generate valid and channel signals
|
||||
HardFP is enabled enabling set to true
|
||||
Correct rounding constraint detected
|
||||
Will not generate valid and channel signals
|
||||
The new component name is acl_itof
|
||||
Frequency 250MHz
|
||||
Deployment FPGA Arria10
|
||||
Estimated resources LUTs 397, DSPs 0, RAMBits 0, RAMBlocks 0
|
||||
The pipeline depth of the block is 7 cycle(s)
|
||||
@@start
|
||||
@name FXPToFP@
|
||||
@latency 7@
|
||||
@LUT 397@
|
||||
@DSP 0@
|
||||
@RAMBits 0@
|
||||
@RAMBlockUsage 0@
|
||||
@enable 1@
|
||||
@subnormals 0@
|
||||
@error 0.50@
|
||||
@rounding RNE@
|
||||
@method default@
|
||||
@inPort 0 fxp 32 0 1@
|
||||
@outPort 0 fpieee 8 23@
|
||||
@nochanvalid 1@
|
||||
@@end
|
||||
starting execution ...
|
||||
build model options ...
|
||||
argc=25
|
||||
Generation context:
|
||||
Will not generate valid and channel signals
|
||||
HardFP is enabled enabling set to true
|
||||
Correct rounding constraint detected
|
||||
Will not generate valid and channel signals
|
||||
The new component name is acl_utof
|
||||
Frequency 300MHz
|
||||
Deployment FPGA Arria10
|
||||
Estimated resources LUTs 363, DSPs 0, RAMBits 0, RAMBlocks 0
|
||||
The pipeline depth of the block is 7 cycle(s)
|
||||
@@start
|
||||
@name FXPToFP@
|
||||
@latency 7@
|
||||
@LUT 363@
|
||||
@DSP 0@
|
||||
@RAMBits 0@
|
||||
@RAMBlockUsage 0@
|
||||
@enable 1@
|
||||
@subnormals 0@
|
||||
@error 0.50@
|
||||
@rounding RNE@
|
||||
@method default@
|
||||
@inPort 0 fxp 32 0 0@
|
||||
@outPort 0 fpieee 8 23@
|
||||
@nochanvalid 1@
|
||||
@@end
|
||||
33
hw/rtl/fp_cores/altera/arria10/acl_gen.sh
Executable file
33
hw/rtl/fp_cores/altera/arria10/acl_gen.sh
Executable file
|
|
@ -0,0 +1,33 @@
|
|||
#!/bin/bash
|
||||
|
||||
FAMILY=Arria10
|
||||
PREFIX=acl
|
||||
|
||||
CMD_POLY_EVAL_PATH=$QUARTUS_HOME/dspba/backend/linux64
|
||||
|
||||
OPTIONS="-target $FAMILY -noChanValid -enable -enableHardFP 1 -printMachineReadable -lang verilog -correctRounding -noChanValid -enable -speedgrade 2"
|
||||
|
||||
export LD_LIBRARY_PATH=$CMD_POLY_EVAL_PATH:$LD_LIBRARY_PATH
|
||||
|
||||
CMD="$CMD_POLY_EVAL_PATH/cmdPolyEval $OPTIONS"
|
||||
|
||||
EXP_BITS=8
|
||||
MAN_BITS=23
|
||||
|
||||
FBITS="f$(($EXP_BITS + $MAN_BITS + 1))"
|
||||
|
||||
echo Generating IP cores for $FBITS
|
||||
{
|
||||
$CMD -name "$PREFIX"_fadd -frequency 250 FPAdd $EXP_BITS $MAN_BITS
|
||||
$CMD -name "$PREFIX"_fsub -frequency 250 FPSub $EXP_BITS $MAN_BITS
|
||||
$CMD -name "$PREFIX"_fmul -frequency 250 FPMul $EXP_BITS $MAN_BITS
|
||||
$CMD -name "$PREFIX"_fmadd -frequency 250 FPMultAdd $EXP_BITS $MAN_BITS
|
||||
$CMD -name "$PREFIX"_fdiv -frequency 250 FPDiv $EXP_BITS $MAN_BITS 0
|
||||
$CMD -name "$PREFIX"_fsqrt -frequency 250 FPSqrt $EXP_BITS $MAN_BITS
|
||||
$CMD -name "$PREFIX"_ftoi -frequency 250 FPToFXP $EXP_BITS $MAN_BITS 32 0 1
|
||||
$CMD -name "$PREFIX"_ftou -frequency 250 FPToFXP $EXP_BITS $MAN_BITS 32 0 0
|
||||
$CMD -name "$PREFIX"_itof -frequency 250 FXPToFP 32 0 1 $EXP_BITS $MAN_BITS
|
||||
$CMD -name "$PREFIX"_utof -frequency 300 FXPToFP 32 0 0 $EXP_BITS $MAN_BITS
|
||||
} > acl_gen.log 2>&1
|
||||
|
||||
#cp $QUARTUS_HOME/dspba/backend/Libraries/sv/base/dspba_library_ver.sv .
|
||||
|
|
@ -16,7 +16,7 @@
|
|||
// ---------------------------------------------------------------------------
|
||||
|
||||
// SystemVerilog created from acl_itof
|
||||
// SystemVerilog created on Wed Dec 9 01:17:51 2020
|
||||
// SystemVerilog created on Sun Dec 27 09:47:21 2020
|
||||
|
||||
|
||||
(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *)
|
||||
|
|
@ -16,7 +16,7 @@
|
|||
// ---------------------------------------------------------------------------
|
||||
|
||||
// SystemVerilog created from acl_utof
|
||||
// SystemVerilog created on Wed Dec 9 01:17:51 2020
|
||||
// SystemVerilog created on Sun Dec 27 09:47:21 2020
|
||||
|
||||
|
||||
(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *)
|
||||
68
hw/rtl/fp_cores/altera/stratix10/acl_fadd.sv
Normal file
68
hw/rtl/fp_cores/altera/stratix10/acl_fadd.sv
Normal file
|
|
@ -0,0 +1,68 @@
|
|||
// -------------------------------------------------------------------------
|
||||
// High Level Design Compiler for Intel(R) FPGAs Version 18.1 (Release Build #277)
|
||||
// Quartus Prime development tool and MATLAB/Simulink Interface
|
||||
//
|
||||
// Legal Notice: Copyright 2019 Intel Corporation. All rights reserved.
|
||||
// Your use of Intel Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly
|
||||
// subject to the terms and conditions of the Intel FPGA Software License
|
||||
// Agreement, Intel MegaCore Function License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for
|
||||
// the sole purpose of programming logic devices manufactured by Intel
|
||||
// and sold by Intel or its authorized distributors. Please refer to the
|
||||
// applicable agreement for further details.
|
||||
// ---------------------------------------------------------------------------
|
||||
|
||||
// SystemVerilog created from acl_fadd
|
||||
// SystemVerilog created on Sun Dec 27 09:48:57 2020
|
||||
|
||||
|
||||
(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *)
|
||||
module acl_fadd (
|
||||
input wire [31:0] a,
|
||||
input wire [31:0] b,
|
||||
input wire [0:0] en,
|
||||
output wire [31:0] q,
|
||||
input wire clk,
|
||||
input wire areset
|
||||
);
|
||||
|
||||
wire fpAddTest_impl_reset0;
|
||||
wire fpAddTest_impl_ena0;
|
||||
wire [31:0] fpAddTest_impl_ax0;
|
||||
wire [31:0] fpAddTest_impl_ay0;
|
||||
wire [31:0] fpAddTest_impl_q0;
|
||||
|
||||
|
||||
// fpAddTest_impl(FPCOLUMN,5)@0
|
||||
// out q0@3
|
||||
assign fpAddTest_impl_ax0 = b;
|
||||
assign fpAddTest_impl_ay0 = a;
|
||||
assign fpAddTest_impl_reset0 = areset;
|
||||
assign fpAddTest_impl_ena0 = en[0] | fpAddTest_impl_reset0;
|
||||
fourteennm_fp_mac #(
|
||||
.operation_mode("sp_add"),
|
||||
.ax_clock("0"),
|
||||
.ay_clock("0"),
|
||||
.adder_input_clock("0"),
|
||||
.output_clock("0"),
|
||||
.clear_type("sclr")
|
||||
) fpAddTest_impl_DSP0 (
|
||||
.clk({1'b0,1'b0,clk}),
|
||||
.ena({ 1'b0, 1'b0, fpAddTest_impl_ena0 }),
|
||||
.clr({ fpAddTest_impl_reset0, fpAddTest_impl_reset0 }),
|
||||
.ax(fpAddTest_impl_ax0),
|
||||
.ay(fpAddTest_impl_ay0),
|
||||
.resulta(fpAddTest_impl_q0),
|
||||
.accumulate(),
|
||||
.az(),
|
||||
.chainin(),
|
||||
.chainout()
|
||||
);
|
||||
|
||||
// xOut(GPOUT,4)@3
|
||||
assign q = fpAddTest_impl_q0;
|
||||
|
||||
endmodule
|
||||
4167
hw/rtl/fp_cores/altera/stratix10/acl_fdiv.sv
Normal file
4167
hw/rtl/fp_cores/altera/stratix10/acl_fdiv.sv
Normal file
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,514 @@
|
|||
:020000040000FA
|
||||
:0400000040000004B8
|
||||
:040001003FE00FFCD1
|
||||
:040002003FC03FC4F8
|
||||
:040003003FA08F2D5E
|
||||
:040004003F80FE0833
|
||||
:040005003F618C25A6
|
||||
:040006003F423958E4
|
||||
:040007003F2305711D
|
||||
:040008003F03F0437F
|
||||
:040009003EE4F9A137
|
||||
:04000A003EC6215D70
|
||||
:04000B003EA7674C59
|
||||
:04000C003E88CB401F
|
||||
:04000D003E6A4D0FEB
|
||||
:04000E003E4BEC8CED
|
||||
:04000F003E2DA98C4D
|
||||
:040010003E0F83E537
|
||||
:040011003DF17B6BD7
|
||||
:040012003DD38FF457
|
||||
:040013003DB5C157DF
|
||||
:040014003D980F6A9A
|
||||
:040015003D7A7A03B3
|
||||
:040016003D5D00F953
|
||||
:040017003D3FA424A1
|
||||
:040018003D22635CC6
|
||||
:040019003D053E77EC
|
||||
:04001A003CE8354F3A
|
||||
:04001B003CCB47BCD7
|
||||
:04001C003CAE7596EB
|
||||
:04001D003C91BEB79D
|
||||
:04001E003C7522F813
|
||||
:04001F003C58A23275
|
||||
:040020003C3C3C40E8
|
||||
:040021003C1FF0FC94
|
||||
:040022003C03C0409B
|
||||
:040023003BE7A9E727
|
||||
:040024003BCBADCC59
|
||||
:040025003BAFCBCA58
|
||||
:040026003B9403BD47
|
||||
:040027003B7855814C
|
||||
:040028003B5CC0F18C
|
||||
:040029003B4145EB27
|
||||
:04002A003B25E44A44
|
||||
:04002B003B0A9BEC05
|
||||
:04002C003AEF6CAD8E
|
||||
:04002D003AD4566CFF
|
||||
:04002E003AB959057D
|
||||
:04002F003A9E74562B
|
||||
:040030003A83A83E29
|
||||
:040031003A68F49B9A
|
||||
:040032003A4E594C9D
|
||||
:040033003A33D62F57
|
||||
:040034003A196B23E7
|
||||
:0400350039FF180770
|
||||
:0400360039E4DCBC11
|
||||
:0400370039CAB921E8
|
||||
:0400380039B0AD1618
|
||||
:040039003996B87BC1
|
||||
:04003A00397CDB3002
|
||||
:04003B0039631516FA
|
||||
:04003C003949660FC9
|
||||
:04003D00392FCDFA90
|
||||
:04003E0039164CBA69
|
||||
:04003F0038FCE22F78
|
||||
:0400400038E38E3DD6
|
||||
:0400410038CA50C4A5
|
||||
:0400420038B129A602
|
||||
:04004300389818C60B
|
||||
:04004400387F1E07DC
|
||||
:040045003866394C94
|
||||
:04004600384D6A7651
|
||||
:040047003834B16A2E
|
||||
:04004800381C0E0B47
|
||||
:040049003803803CBC
|
||||
:04004A0037EB07E1A8
|
||||
:04004B0037D2A4DE26
|
||||
:04004C0037BA571751
|
||||
:04004D0037A21E7147
|
||||
:04004E003789FACF25
|
||||
:04004F003771EC1702
|
||||
:040050003759F22DFD
|
||||
:0400510037420CF72F
|
||||
:04005200372A3C5AB3
|
||||
:040053003712803BA5
|
||||
:0400540036FAD88020
|
||||
:0400550036E3450E3B
|
||||
:0400560036CBC5CB15
|
||||
:0400570036B45A9FC2
|
||||
:04005800369D036E60
|
||||
:040059003685C01F09
|
||||
:04005A00366E909AD4
|
||||
:04005B00365774C4DC
|
||||
:04005C0036406C8539
|
||||
:04005D00362977C405
|
||||
:04005E003612966858
|
||||
:04005F0035FBC8584D
|
||||
:0400600035E50D7DF8
|
||||
:0400610035CE65BE75
|
||||
:0400620035B7D103DA
|
||||
:0400630035A14F3440
|
||||
:04006400358AE039C0
|
||||
:04006500357483FC6F
|
||||
:04006600355E3A6366
|
||||
:0400670035480358BD
|
||||
:040068003531DEC58B
|
||||
:04006900351BCC91E6
|
||||
:04006A003505CCA6E6
|
||||
:04006B0034EFDEEEA2
|
||||
:04006C0034DA03522D
|
||||
:04006D0034C439BBA3
|
||||
:04006E0034AE821317
|
||||
:04006F003498DC44A1
|
||||
:040070003483483855
|
||||
:04007100346DC5DA4B
|
||||
:040072003458551396
|
||||
:040073003442F5CF4F
|
||||
:04007400342DA7F789
|
||||
:0400750034186B765A
|
||||
:0400760034034038D7
|
||||
:0400770033EE262717
|
||||
:0400780033D91D2E2D
|
||||
:0400790033C425392E
|
||||
:04007A0033AF3E332F
|
||||
:04007B00339A680745
|
||||
:04007C003385A2A284
|
||||
:04007D003370EDEE01
|
||||
:04007E00335C49D9CD
|
||||
:04007F003347B64D00
|
||||
:0400800033333337AC
|
||||
:04008100331EC084E6
|
||||
:04008200330A5E1FC0
|
||||
:0400830032F60BF650
|
||||
:0400840032E1C9F4A8
|
||||
:0400850032CD9807D9
|
||||
:0400860032B9761CF9
|
||||
:0400870032A5641F1B
|
||||
:04008800329161FE52
|
||||
:04008900327D6FA5B0
|
||||
:04008A0032698D0347
|
||||
:04008B003255BA052B
|
||||
:04008C003241F6986F
|
||||
:04008D00322E42A924
|
||||
:04008E00321A9E285C
|
||||
:04008F00320709012A
|
||||
:0400900031F38323A2
|
||||
:0400910031E00C7CD2
|
||||
:0400920031CCA4FACF
|
||||
:0400930031B94C8BA8
|
||||
:0400940031A6031E70
|
||||
:040095003192C8A23A
|
||||
:04009600317F9D0514
|
||||
:04009700316C803513
|
||||
:040098003159722345
|
||||
:04009900314672BCBE
|
||||
:04009A00313381F08D
|
||||
:04009B0031209FAEC3
|
||||
:04009C00310DCBE572
|
||||
:04009D0030FB0685A9
|
||||
:04009E0030E84F7D7A
|
||||
:04009F0030D5A6BDF5
|
||||
:0400A00030C30C3528
|
||||
:0400A10030B07FD329
|
||||
:0400A200309E018902
|
||||
:0400A300308B9146C7
|
||||
:0400A40030792EF988
|
||||
:0400A5003066DA9453
|
||||
:0400A6003054940737
|
||||
:0400A70030425B4147
|
||||
:0400A8003030303490
|
||||
:0400A900301E12D023
|
||||
:0400AA00300C03050E
|
||||
:0400AB002FFA00C464
|
||||
:0400AC002FE80BFE30
|
||||
:0400AD002FD624A482
|
||||
:0400AE002FC44AA76A
|
||||
:0400AF002FB27DF7F8
|
||||
:0400B0002FA0BE8738
|
||||
:0400B1002F8F0C473A
|
||||
:0400B2002F7D67280F
|
||||
:0400B3002F6BCF1DC3
|
||||
:0400B4002F5A441665
|
||||
:0400B5002F48C60505
|
||||
:0400B6002F3754DBB1
|
||||
:0400B7002F25F08B76
|
||||
:0400B8002F14990761
|
||||
:0400B9002F034E3F84
|
||||
:0400BA002EF21027EB
|
||||
:0400BB002EE0DEB0A5
|
||||
:0400BC002ECFB9CCBE
|
||||
:0400BD002EBEA16E44
|
||||
:0400BE002EAD958846
|
||||
:0400BF002E9C960CD1
|
||||
:0400C0002E8BA2EDF4
|
||||
:0400C1002E7ABC1DBA
|
||||
:0400C2002E69E18E34
|
||||
:0400C3002E5913356A
|
||||
:0400C4002E4851026F
|
||||
:0400C5002E379AEA4E
|
||||
:0400C6002E26F0DF13
|
||||
:0400C7002E1652D4CB
|
||||
:0400C8002E05C0BC85
|
||||
:0400C9002DF53A8A4D
|
||||
:0400CA002DE4C0322F
|
||||
:0400CB002DD451A639
|
||||
:0400CC002DC3EEDA78
|
||||
:0400CD002DB397C2F6
|
||||
:0400CE002DA34C51C1
|
||||
:0400CF002D930C7AE7
|
||||
:0400D0002D82D83174
|
||||
:0400D1002D72AF6B72
|
||||
:0400D2002D629219F0
|
||||
:0400D3002D528031F9
|
||||
:0400D4002D4279A799
|
||||
:0400D5002D327E6DDD
|
||||
:0400D6002D228E79D0
|
||||
:0400D7002D12A9BE7F
|
||||
:0400D8002D02D031F4
|
||||
:0400D9002CF301C53E
|
||||
:0400DA002CE33E7065
|
||||
:0400DB002CD3862577
|
||||
:0400DC002CC3D8D980
|
||||
:0400DD002CB4368089
|
||||
:0400DE002CA49F0EA1
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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|
||||
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|
||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
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||||
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|
||||
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||||
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||||
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||||
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|
||||
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|
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|
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|
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|
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|
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||||
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||||
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|
||||
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|
||||
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|
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|
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||||
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||||
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|
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
:0201FD000205F9
|
||||
:0201FE000204F9
|
||||
:0201FF0001FFFE
|
||||
:00000001ff
|
||||
74
hw/rtl/fp_cores/altera/stratix10/acl_fmadd.sv
Normal file
74
hw/rtl/fp_cores/altera/stratix10/acl_fmadd.sv
Normal file
|
|
@ -0,0 +1,74 @@
|
|||
// -------------------------------------------------------------------------
|
||||
// High Level Design Compiler for Intel(R) FPGAs Version 18.1 (Release Build #277)
|
||||
// Quartus Prime development tool and MATLAB/Simulink Interface
|
||||
//
|
||||
// Legal Notice: Copyright 2019 Intel Corporation. All rights reserved.
|
||||
// Your use of Intel Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly
|
||||
// subject to the terms and conditions of the Intel FPGA Software License
|
||||
// Agreement, Intel MegaCore Function License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for
|
||||
// the sole purpose of programming logic devices manufactured by Intel
|
||||
// and sold by Intel or its authorized distributors. Please refer to the
|
||||
// applicable agreement for further details.
|
||||
// ---------------------------------------------------------------------------
|
||||
|
||||
// SystemVerilog created from acl_fmadd
|
||||
// SystemVerilog created on Sun Dec 27 09:48:58 2020
|
||||
|
||||
|
||||
(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *)
|
||||
module acl_fmadd (
|
||||
input wire [31:0] a,
|
||||
input wire [31:0] b,
|
||||
input wire [31:0] c,
|
||||
input wire [0:0] en,
|
||||
output wire [31:0] q,
|
||||
input wire clk,
|
||||
input wire areset
|
||||
);
|
||||
|
||||
wire fpMultAddTest_impl_reset0;
|
||||
wire fpMultAddTest_impl_ena0;
|
||||
wire [31:0] fpMultAddTest_impl_ax0;
|
||||
wire [31:0] fpMultAddTest_impl_ay0;
|
||||
wire [31:0] fpMultAddTest_impl_az0;
|
||||
wire [31:0] fpMultAddTest_impl_q0;
|
||||
|
||||
|
||||
// fpMultAddTest_impl(FPCOLUMN,5)@0
|
||||
// out q0@4
|
||||
assign fpMultAddTest_impl_ax0 = c;
|
||||
assign fpMultAddTest_impl_ay0 = b;
|
||||
assign fpMultAddTest_impl_az0 = a;
|
||||
assign fpMultAddTest_impl_reset0 = areset;
|
||||
assign fpMultAddTest_impl_ena0 = en[0] | fpMultAddTest_impl_reset0;
|
||||
fourteennm_fp_mac #(
|
||||
.operation_mode("sp_mult_add"),
|
||||
.ax_clock("0"),
|
||||
.ay_clock("0"),
|
||||
.az_clock("0"),
|
||||
.mult_2nd_pipeline_clock("0"),
|
||||
.adder_input_clock("0"),
|
||||
.ax_chainin_pl_clock("0"),
|
||||
.output_clock("0"),
|
||||
.clear_type("sclr")
|
||||
) fpMultAddTest_impl_DSP0 (
|
||||
.clk({1'b0,1'b0,clk}),
|
||||
.ena({ 1'b0, 1'b0, fpMultAddTest_impl_ena0 }),
|
||||
.clr({ fpMultAddTest_impl_reset0, fpMultAddTest_impl_reset0 }),
|
||||
.ax(fpMultAddTest_impl_ax0),
|
||||
.ay(fpMultAddTest_impl_ay0),
|
||||
.az(fpMultAddTest_impl_az0),
|
||||
.resulta(fpMultAddTest_impl_q0),
|
||||
.accumulate(),
|
||||
.chainin(),
|
||||
.chainout()
|
||||
);
|
||||
|
||||
// xOut(GPOUT,4)@4
|
||||
assign q = fpMultAddTest_impl_q0;
|
||||
|
||||
endmodule
|
||||
75
hw/rtl/fp_cores/altera/stratix10/acl_fmsub.sv
Normal file
75
hw/rtl/fp_cores/altera/stratix10/acl_fmsub.sv
Normal file
|
|
@ -0,0 +1,75 @@
|
|||
// -------------------------------------------------------------------------
|
||||
// High Level Design Compiler for Intel(R) FPGAs Version 18.1 (Release Build #277)
|
||||
// Quartus Prime development tool and MATLAB/Simulink Interface
|
||||
//
|
||||
// Legal Notice: Copyright 2019 Intel Corporation. All rights reserved.
|
||||
// Your use of Intel Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly
|
||||
// subject to the terms and conditions of the Intel FPGA Software License
|
||||
// Agreement, Intel MegaCore Function License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for
|
||||
// the sole purpose of programming logic devices manufactured by Intel
|
||||
// and sold by Intel or its authorized distributors. Please refer to the
|
||||
// applicable agreement for further details.
|
||||
// ---------------------------------------------------------------------------
|
||||
|
||||
// SystemVerilog created from acl_fmsub
|
||||
// SystemVerilog created on Sun Dec 27 07:06:39 2020
|
||||
|
||||
|
||||
(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *)
|
||||
module acl_fmsub (
|
||||
input wire [31:0] a,
|
||||
input wire [31:0] b,
|
||||
input wire [31:0] c,
|
||||
input wire [0:0] en,
|
||||
output wire [31:0] q,
|
||||
input wire clk,
|
||||
input wire areset
|
||||
);
|
||||
|
||||
wire fpMultAddTest_impl_reset0;
|
||||
wire fpMultAddTest_impl_ena0;
|
||||
wire [31:0] fpMultAddTest_impl_ax0;
|
||||
wire [31:0] fpMultAddTest_impl_ay0;
|
||||
wire [31:0] fpMultAddTest_impl_az0;
|
||||
wire [31:0] fpMultAddTest_impl_q0;
|
||||
|
||||
|
||||
// fpMultAddTest_impl(FPCOLUMN,5)@0
|
||||
// out q0@4
|
||||
assign fpMultAddTest_impl_ax0 = c;
|
||||
assign fpMultAddTest_impl_ay0 = b;
|
||||
assign fpMultAddTest_impl_az0 = a;
|
||||
assign fpMultAddTest_impl_reset0 = areset;
|
||||
assign fpMultAddTest_impl_ena0 = en[0] | fpMultAddTest_impl_reset0;
|
||||
fourteennm_fp_mac #(
|
||||
.operation_mode("sp_mult_add"),
|
||||
.adder_subtract("true"),
|
||||
.ax_clock("0"),
|
||||
.ay_clock("0"),
|
||||
.az_clock("0"),
|
||||
.mult_2nd_pipeline_clock("0"),
|
||||
.adder_input_clock("0"),
|
||||
.ax_chainin_pl_clock("0"),
|
||||
.output_clock("0"),
|
||||
.clear_type("sclr")
|
||||
) fpMultAddTest_impl_DSP0 (
|
||||
.clk({1'b0,1'b0,clk}),
|
||||
.ena({ 1'b0, 1'b0, fpMultAddTest_impl_ena0 }),
|
||||
.clr({ fpMultAddTest_impl_reset0, fpMultAddTest_impl_reset0 }),
|
||||
.ax(fpMultAddTest_impl_ax0),
|
||||
.ay(fpMultAddTest_impl_ay0),
|
||||
.az(fpMultAddTest_impl_az0),
|
||||
.resulta(fpMultAddTest_impl_q0),
|
||||
.accumulate(),
|
||||
.chainin(),
|
||||
.chainout()
|
||||
);
|
||||
|
||||
// xOut(GPOUT,4)@4
|
||||
assign q = fpMultAddTest_impl_q0;
|
||||
|
||||
endmodule
|
||||
68
hw/rtl/fp_cores/altera/stratix10/acl_fmul.sv
Normal file
68
hw/rtl/fp_cores/altera/stratix10/acl_fmul.sv
Normal file
|
|
@ -0,0 +1,68 @@
|
|||
// -------------------------------------------------------------------------
|
||||
// High Level Design Compiler for Intel(R) FPGAs Version 18.1 (Release Build #277)
|
||||
// Quartus Prime development tool and MATLAB/Simulink Interface
|
||||
//
|
||||
// Legal Notice: Copyright 2019 Intel Corporation. All rights reserved.
|
||||
// Your use of Intel Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly
|
||||
// subject to the terms and conditions of the Intel FPGA Software License
|
||||
// Agreement, Intel MegaCore Function License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for
|
||||
// the sole purpose of programming logic devices manufactured by Intel
|
||||
// and sold by Intel or its authorized distributors. Please refer to the
|
||||
// applicable agreement for further details.
|
||||
// ---------------------------------------------------------------------------
|
||||
|
||||
// SystemVerilog created from acl_fmul
|
||||
// SystemVerilog created on Sun Dec 27 09:48:57 2020
|
||||
|
||||
|
||||
(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *)
|
||||
module acl_fmul (
|
||||
input wire [31:0] a,
|
||||
input wire [31:0] b,
|
||||
input wire [0:0] en,
|
||||
output wire [31:0] q,
|
||||
input wire clk,
|
||||
input wire areset
|
||||
);
|
||||
|
||||
wire fpMulTest_impl_reset0;
|
||||
wire fpMulTest_impl_ena0;
|
||||
wire [31:0] fpMulTest_impl_ay0;
|
||||
wire [31:0] fpMulTest_impl_az0;
|
||||
wire [31:0] fpMulTest_impl_q0;
|
||||
|
||||
|
||||
// fpMulTest_impl(FPCOLUMN,5)@0
|
||||
// out q0@3
|
||||
assign fpMulTest_impl_ay0 = b;
|
||||
assign fpMulTest_impl_az0 = a;
|
||||
assign fpMulTest_impl_reset0 = areset;
|
||||
assign fpMulTest_impl_ena0 = en[0] | fpMulTest_impl_reset0;
|
||||
fourteennm_fp_mac #(
|
||||
.operation_mode("sp_mult"),
|
||||
.ay_clock("0"),
|
||||
.az_clock("0"),
|
||||
.mult_2nd_pipeline_clock("0"),
|
||||
.output_clock("0"),
|
||||
.clear_type("sclr")
|
||||
) fpMulTest_impl_DSP0 (
|
||||
.clk({1'b0,1'b0,clk}),
|
||||
.ena({ 1'b0, 1'b0, fpMulTest_impl_ena0 }),
|
||||
.clr({ fpMulTest_impl_reset0, fpMulTest_impl_reset0 }),
|
||||
.ay(fpMulTest_impl_ay0),
|
||||
.az(fpMulTest_impl_az0),
|
||||
.resulta(fpMulTest_impl_q0),
|
||||
.accumulate(),
|
||||
.ax(),
|
||||
.chainin(),
|
||||
.chainout()
|
||||
);
|
||||
|
||||
// xOut(GPOUT,4)@3
|
||||
assign q = fpMulTest_impl_q0;
|
||||
|
||||
endmodule
|
||||
2116
hw/rtl/fp_cores/altera/stratix10/acl_fsqrt.sv
Normal file
2116
hw/rtl/fp_cores/altera/stratix10/acl_fsqrt.sv
Normal file
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,258 @@
|
|||
:020000040000FA
|
||||
:0400000008000004F0
|
||||
:040001000807FC08E8
|
||||
:04000200080FF024CF
|
||||
:040003000817DC6F8F
|
||||
:04000400081FC0FF12
|
||||
:0400050008279DEC3F
|
||||
:04000600082F734C00
|
||||
:040007000837413342
|
||||
:04000800083F07B7EF
|
||||
:040009000846C6EEF1
|
||||
:04000A00084E7EEB33
|
||||
:04000B0008562FC2A2
|
||||
:04000C00085DD9882A
|
||||
:04000D0008657C4FB7
|
||||
:04000E00086D182B36
|
||||
:04000F000874AD2E96
|
||||
:04001000087C3B6BC2
|
||||
:040011000883C2F3AB
|
||||
:04001200088B43D83C
|
||||
:040013000892BE2D64
|
||||
:04001400089A320113
|
||||
:0400150008A19F6639
|
||||
:0400160008A9066DC2
|
||||
:0400170008B06725A1
|
||||
:0400180008B7C19EC6
|
||||
:0400190008BF15E91E
|
||||
:04001A0008C664159B
|
||||
:04001B0008CDAC312F
|
||||
:04001C0008D4EE4CCA
|
||||
:04001D0008DC2A755C
|
||||
:04001E0008E360BAD9
|
||||
:04001F0008EA912931
|
||||
:0400200008F1BBD256
|
||||
:0400210008F8E0C13A
|
||||
:0400220009000004CD
|
||||
:04002300090719A907
|
||||
:04002400090E2DBCD8
|
||||
:0400250009153C4C31
|
||||
:04002600091C456408
|
||||
:04002700092349114F
|
||||
:04002800092A4761F9
|
||||
:040029000931405EFB
|
||||
:04002A000938341548
|
||||
:04002B00093F2292D5
|
||||
:04002C0009460BE195
|
||||
:04002D00094CF00D7D
|
||||
:04002E000953CF2182
|
||||
:04002F00095AA92998
|
||||
:0400300009617E31B3
|
||||
:0400310009684E42CA
|
||||
:04003200096F1967D2
|
||||
:040033000975DFACC0
|
||||
:04003400097CA11A88
|
||||
:0400350009835DBC22
|
||||
:04003600098A159C82
|
||||
:040037000990C8C59F
|
||||
:040038000997773F6E
|
||||
:04003900099E2115E6
|
||||
:04003A0009A4C650FF
|
||||
:04003B0009AB66FAAD
|
||||
:04003C0009B2031CE6
|
||||
:04003D0009B89AC0A4
|
||||
:04003E0009BF2DEEDB
|
||||
:04003F0009C5BCB083
|
||||
:0400400009CC470E92
|
||||
:0400410009D2CD1102
|
||||
:0400420009D94EC3C7
|
||||
:0400430009DFCC2ADB
|
||||
:0400440009E6455133
|
||||
:0400450009ECBA3FC9
|
||||
:0400460009F32AFC94
|
||||
:0400470009F997908C
|
||||
:040048000A000004A6
|
||||
:040049000A06645FE0
|
||||
:04004A000A0CC4AA2E
|
||||
:04004B000A1320EC88
|
||||
:04004C000A19792CE8
|
||||
:04004D000A1FCD7247
|
||||
:04004E000A261DC69B
|
||||
:04004F000A2C6A2FDE
|
||||
:040050000A32B2B40A
|
||||
:040051000A38F75C16
|
||||
:040052000A3F382EFB
|
||||
:040053000A457532B3
|
||||
:040054000A4BAE6F36
|
||||
:040055000A51E3EA7F
|
||||
:040056000A5815AC83
|
||||
:040057000A5E43BA40
|
||||
:040058000A646E1BAD
|
||||
:040059000A6A94D6C5
|
||||
:04005A000A70B7F180
|
||||
:04005B000A76D773D7
|
||||
:04005C000A7CF362C5
|
||||
:04005D000A830BC443
|
||||
:04005E000A89209F4C
|
||||
:04005F000A8F31F9DA
|
||||
:040060000A953FD9E5
|
||||
:040061000A9B4A4468
|
||||
:040062000AA151405E
|
||||
:040063000AA754D4C0
|
||||
:040064000AAD550488
|
||||
:040065000AB351D7B2
|
||||
:040066000AB94B5236
|
||||
:040067000ABF417A11
|
||||
:040068000AC534563B
|
||||
:040069000ACB23EBB0
|
||||
:04006A000AD1103E69
|
||||
:04006B000AD6F95464
|
||||
:04006C000ADCDF3398
|
||||
:04006D000AE2C1E002
|
||||
:04006E000AE8A15F9C
|
||||
:04006F000AEE7DB860
|
||||
:040070000AF456ED4B
|
||||
:040071000AFA2D0555
|
||||
:040072000B0000047B
|
||||
:040073000B05CFEFBB
|
||||
:040074000B0B9CCC0A
|
||||
:040075000B11669E67
|
||||
:040076000B172D6BCC
|
||||
:040077000B1CF13736
|
||||
:040078000B22B2079E
|
||||
:040079000B286FDF02
|
||||
:04007A000B2E2AC55A
|
||||
:04007B000B33E2BDA4
|
||||
:04007C000B3997CBDA
|
||||
:04007D000B3F49F3F9
|
||||
:04007E000B44F93AFC
|
||||
:04007F000B4AA5A5DE
|
||||
:040080000B504F379B
|
||||
:040081000B5B99E498
|
||||
:040082000B66D962CE
|
||||
:040083000B720DD21D
|
||||
:040084000B7D375564
|
||||
:040085000B88560A84
|
||||
:040086000B936A105E
|
||||
:040087000B9E7387D2
|
||||
:040088000BA9728BC3
|
||||
:040089000BB4673B12
|
||||
:04008A000BBF51B3A4
|
||||
:04008B000BCA32105A
|
||||
:04008C000BD5086D1B
|
||||
:04008D000BDFD4E6CB
|
||||
:04008E000BEA97964C
|
||||
:04008F000BF5509885
|
||||
:040090000C0000045C
|
||||
:040091000C0AA5F5BB
|
||||
:040092000C15428483
|
||||
:040093000C1FD5CA9F
|
||||
:040094000C2A5FDEF5
|
||||
:040095000C34E0D86F
|
||||
:040096000C3F58D1F2
|
||||
:040097000C49C7DE6B
|
||||
:040098000C542E17BF
|
||||
:040099000C5E8B91DD
|
||||
:04009A000C68E063AB
|
||||
:04009B000C732CA313
|
||||
:04009C000C7D706502
|
||||
:04009D000C87ABBE63
|
||||
:04009E000C91DEC320
|
||||
:04009F000C9C098824
|
||||
:0400A0000CA62C225C
|
||||
:0400A1000CB046A2B7
|
||||
:0400A2000CBA591E1D
|
||||
:0400A3000CC463A77F
|
||||
:0400A4000CCE6651C7
|
||||
:0400A5000CD8612EE4
|
||||
:0400A6000CE2544FC5
|
||||
:0400A7000CEC3FC856
|
||||
:0400A8000CF623A986
|
||||
:0400A9000D00000442
|
||||
:0400AA000D09D4EA7E
|
||||
:0400AB000D13A26B24
|
||||
:0400AC000D1D689925
|
||||
:0400AD000D27278470
|
||||
:0400AE000D30DF3BF7
|
||||
:0400AF000D3A8FCEA9
|
||||
:0400B0000D44394E74
|
||||
:0400B1000D4DDBCA4C
|
||||
:0400B2000D5777501F
|
||||
:0400B3000D610BF0E0
|
||||
:0400B4000D6A99B97F
|
||||
:0400B5000D7420B9ED
|
||||
:0400B6000D7DA0FE1E
|
||||
:0400B7000D871A9700
|
||||
:0400B8000D908D9288
|
||||
:0400B9000D99F9FDA7
|
||||
:0400BA000DA35FE44F
|
||||
:0400BB000DACBF5673
|
||||
:0400BC000DB6186005
|
||||
:0400BD000DBF6B0FF9
|
||||
:0400BE000DC8B76F43
|
||||
:0400BF000DD1FD8ED4
|
||||
:0400C0000DDB3D789F
|
||||
:0400C1000DE4773A99
|
||||
:0400C2000DEDAADFB7
|
||||
:0400C3000DF6D874EA
|
||||
:0400C4000E00000426
|
||||
:0400C5000E09219C63
|
||||
:0400C6000E123D4792
|
||||
:0400C7000E1B5311A8
|
||||
:0400C8000E2463049B
|
||||
:0400C9000E2D6D2D5E
|
||||
:0400CA000E367195E8
|
||||
:0400CB000E3F70492B
|
||||
:0400CC000E4869531E
|
||||
:0400CD000E515CBDB7
|
||||
:0400CE000E5A4A92EA
|
||||
:0400CF000E6332DCAE
|
||||
:0400D0000E6C15A6F7
|
||||
:0400D1000E74F2FABD
|
||||
:0400D2000E7DCAE2F3
|
||||
:0400D3000E869D6791
|
||||
:0400D4000E8F6A948D
|
||||
:0400D5000E983272DD
|
||||
:0400D6000EA0F50B78
|
||||
:0400D7000EA9B26854
|
||||
:0400D8000EB26A9367
|
||||
:0400D9000EBB1D94A9
|
||||
:0400DA000EC3CB7610
|
||||
:0400DB000ECC744093
|
||||
:0400DC000ED517FC2A
|
||||
:0400DD000EDDB6B2CC
|
||||
:0400DE000EE6506C6E
|
||||
:0400DF000EEEE5320A
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|
||||
:0200A9000C4AFF
|
||||
:0200AA000C52F6
|
||||
:0200AB000C59EE
|
||||
:0200AC000C61E5
|
||||
:0200AD000C6DD8
|
||||
:0200AE000C73D1
|
||||
:0200AF000C7AC9
|
||||
:0200B0000C80C2
|
||||
:0200B1000C8BB6
|
||||
:0200B2000C91AF
|
||||
:0200B3000C99A6
|
||||
:0200B4000CA19D
|
||||
:0200B5000CA796
|
||||
:0200B6000CAC90
|
||||
:0200B7000CB388
|
||||
:0200B8000CBC7E
|
||||
:0200B9000CC277
|
||||
:0200BA000CC771
|
||||
:0200BB000CCE69
|
||||
:0200BC000CD660
|
||||
:0200BD000CDC59
|
||||
:0200BE000CE153
|
||||
:0200BF000CE84B
|
||||
:0200C0000CED45
|
||||
:0200C1000CF73A
|
||||
:0200C2000CFA36
|
||||
:0200C3000D022C
|
||||
:0200C4000D0726
|
||||
:0200C5000D0D1F
|
||||
:0200C6000D1318
|
||||
:0200C7000D1911
|
||||
:0200C8000D1E0B
|
||||
:0200C9000D2305
|
||||
:0200CA000D2700
|
||||
:0200CB000D2FF7
|
||||
:0200CC000D35F0
|
||||
:0200CD000D3AEA
|
||||
:0200CE000D3EE5
|
||||
:0200CF000D42E0
|
||||
:0200D0000D47DA
|
||||
:0200D1000D4DD3
|
||||
:0200D2000D51CE
|
||||
:0200D3000D55C9
|
||||
:0200D4000D59C4
|
||||
:0200D5000D5EBE
|
||||
:0200D6000D63B8
|
||||
:0200D7000D68B2
|
||||
:0200D8000D6CAD
|
||||
:0200D9000D72A6
|
||||
:0200DA000D789F
|
||||
:0200DB000D7C9A
|
||||
:0200DC000D7F96
|
||||
:0200DD000D8292
|
||||
:0200DE000D868D
|
||||
:0200DF000D8C86
|
||||
:0200E0000D9180
|
||||
:0200E1000D937D
|
||||
:0200E2000D9B74
|
||||
:0200E3000D9E70
|
||||
:0200E4000D9F6E
|
||||
:0200E5000DA864
|
||||
:0200E6000DA863
|
||||
:0200E7000DAD5D
|
||||
:0200E8000DB257
|
||||
:0200E9000DB454
|
||||
:0200EA000DB750
|
||||
:0200EB000DBC4A
|
||||
:0200EC000DBF46
|
||||
:0200ED000DC143
|
||||
:0200EE000DC53E
|
||||
:0200EF000DCB37
|
||||
:0200F0000DCE33
|
||||
:0200F1000DD030
|
||||
:0200F2000DD728
|
||||
:0200F3000DDA24
|
||||
:0200F4000DDC21
|
||||
:0200F5000DDF1D
|
||||
:0200F6000DE417
|
||||
:0200F7000DE713
|
||||
:0200F8000DE910
|
||||
:0200F9000DEC0C
|
||||
:0200FA000DEE09
|
||||
:0200FB000DF006
|
||||
:0200FC000DF500
|
||||
:0200FD000DF9FB
|
||||
:0200FE000DFCF7
|
||||
:0200FF000DFFF3
|
||||
:00000001ff
|
||||
69
hw/rtl/fp_cores/altera/stratix10/acl_fsub.sv
Normal file
69
hw/rtl/fp_cores/altera/stratix10/acl_fsub.sv
Normal file
|
|
@ -0,0 +1,69 @@
|
|||
// -------------------------------------------------------------------------
|
||||
// High Level Design Compiler for Intel(R) FPGAs Version 18.1 (Release Build #277)
|
||||
// Quartus Prime development tool and MATLAB/Simulink Interface
|
||||
//
|
||||
// Legal Notice: Copyright 2019 Intel Corporation. All rights reserved.
|
||||
// Your use of Intel Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly
|
||||
// subject to the terms and conditions of the Intel FPGA Software License
|
||||
// Agreement, Intel MegaCore Function License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for
|
||||
// the sole purpose of programming logic devices manufactured by Intel
|
||||
// and sold by Intel or its authorized distributors. Please refer to the
|
||||
// applicable agreement for further details.
|
||||
// ---------------------------------------------------------------------------
|
||||
|
||||
// SystemVerilog created from acl_fsub
|
||||
// SystemVerilog created on Sun Dec 27 09:48:57 2020
|
||||
|
||||
|
||||
(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *)
|
||||
module acl_fsub (
|
||||
input wire [31:0] a,
|
||||
input wire [31:0] b,
|
||||
input wire [0:0] en,
|
||||
output wire [31:0] q,
|
||||
input wire clk,
|
||||
input wire areset
|
||||
);
|
||||
|
||||
wire fpSubTest_impl_reset0;
|
||||
wire fpSubTest_impl_ena0;
|
||||
wire [31:0] fpSubTest_impl_ax0;
|
||||
wire [31:0] fpSubTest_impl_ay0;
|
||||
wire [31:0] fpSubTest_impl_q0;
|
||||
|
||||
|
||||
// fpSubTest_impl(FPCOLUMN,5)@0
|
||||
// out q0@3
|
||||
assign fpSubTest_impl_ax0 = b;
|
||||
assign fpSubTest_impl_ay0 = a;
|
||||
assign fpSubTest_impl_reset0 = areset;
|
||||
assign fpSubTest_impl_ena0 = en[0] | fpSubTest_impl_reset0;
|
||||
fourteennm_fp_mac #(
|
||||
.operation_mode("sp_add"),
|
||||
.adder_subtract("true"),
|
||||
.ax_clock("0"),
|
||||
.ay_clock("0"),
|
||||
.adder_input_clock("0"),
|
||||
.output_clock("0"),
|
||||
.clear_type("sclr")
|
||||
) fpSubTest_impl_DSP0 (
|
||||
.clk({1'b0,1'b0,clk}),
|
||||
.ena({ 1'b0, 1'b0, fpSubTest_impl_ena0 }),
|
||||
.clr({ fpSubTest_impl_reset0, fpSubTest_impl_reset0 }),
|
||||
.ax(fpSubTest_impl_ax0),
|
||||
.ay(fpSubTest_impl_ay0),
|
||||
.resulta(fpSubTest_impl_q0),
|
||||
.accumulate(),
|
||||
.az(),
|
||||
.chainin(),
|
||||
.chainout()
|
||||
);
|
||||
|
||||
// xOut(GPOUT,4)@3
|
||||
assign q = fpSubTest_impl_q0;
|
||||
|
||||
endmodule
|
||||
586
hw/rtl/fp_cores/altera/stratix10/acl_ftoi.sv
Normal file
586
hw/rtl/fp_cores/altera/stratix10/acl_ftoi.sv
Normal file
|
|
@ -0,0 +1,586 @@
|
|||
// -------------------------------------------------------------------------
|
||||
// High Level Design Compiler for Intel(R) FPGAs Version 18.1 (Release Build #277)
|
||||
// Quartus Prime development tool and MATLAB/Simulink Interface
|
||||
//
|
||||
// Legal Notice: Copyright 2019 Intel Corporation. All rights reserved.
|
||||
// Your use of Intel Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly
|
||||
// subject to the terms and conditions of the Intel FPGA Software License
|
||||
// Agreement, Intel MegaCore Function License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for
|
||||
// the sole purpose of programming logic devices manufactured by Intel
|
||||
// and sold by Intel or its authorized distributors. Please refer to the
|
||||
// applicable agreement for further details.
|
||||
// ---------------------------------------------------------------------------
|
||||
|
||||
// SystemVerilog created from acl_ftoi
|
||||
// SystemVerilog created on Sun Dec 27 09:48:58 2020
|
||||
|
||||
|
||||
(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *)
|
||||
module acl_ftoi (
|
||||
input wire [31:0] a,
|
||||
input wire [0:0] en,
|
||||
output wire [31:0] q,
|
||||
input wire clk,
|
||||
input wire areset
|
||||
);
|
||||
|
||||
wire [0:0] GND_q;
|
||||
wire [7:0] cstAllOWE_uid6_fpToFxPTest_q;
|
||||
wire [22:0] cstZeroWF_uid7_fpToFxPTest_q;
|
||||
wire [7:0] cstAllZWE_uid8_fpToFxPTest_q;
|
||||
wire [7:0] exp_x_uid9_fpToFxPTest_b;
|
||||
wire [22:0] frac_x_uid10_fpToFxPTest_b;
|
||||
wire [0:0] excZ_x_uid11_fpToFxPTest_q;
|
||||
wire [0:0] expXIsMax_uid12_fpToFxPTest_q;
|
||||
wire [0:0] fracXIsZero_uid13_fpToFxPTest_q;
|
||||
wire [0:0] fracXIsNotZero_uid14_fpToFxPTest_q;
|
||||
wire [0:0] excI_x_uid15_fpToFxPTest_qi;
|
||||
reg [0:0] excI_x_uid15_fpToFxPTest_q;
|
||||
wire [0:0] excN_x_uid16_fpToFxPTest_q;
|
||||
wire [0:0] fracPostZ_uid23_fpToFxPTest_s;
|
||||
reg [22:0] fracPostZ_uid23_fpToFxPTest_q;
|
||||
wire [0:0] invExcXZ_uid24_fpToFxPTest_qi;
|
||||
reg [0:0] invExcXZ_uid24_fpToFxPTest_q;
|
||||
wire [23:0] oFracX_uid25_fpToFxPTest_q;
|
||||
wire [0:0] signX_uid27_fpToFxPTest_b;
|
||||
wire [0:0] notNan_uid28_fpToFxPTest_q;
|
||||
wire [0:0] signX_uid29_fpToFxPTest_qi;
|
||||
reg [0:0] signX_uid29_fpToFxPTest_q;
|
||||
wire [8:0] ovfExpVal_uid30_fpToFxPTest_q;
|
||||
wire [10:0] ovfExpRange_uid31_fpToFxPTest_a;
|
||||
wire [10:0] ovfExpRange_uid31_fpToFxPTest_b;
|
||||
logic [10:0] ovfExpRange_uid31_fpToFxPTest_o;
|
||||
wire [0:0] ovfExpRange_uid31_fpToFxPTest_n;
|
||||
wire [7:0] udfExpVal_uid32_fpToFxPTest_q;
|
||||
wire [10:0] udf_uid33_fpToFxPTest_a;
|
||||
wire [10:0] udf_uid33_fpToFxPTest_b;
|
||||
logic [10:0] udf_uid33_fpToFxPTest_o;
|
||||
wire [0:0] udf_uid33_fpToFxPTest_n;
|
||||
wire [8:0] ovfExpVal_uid34_fpToFxPTest_q;
|
||||
wire [10:0] shiftValE_uid35_fpToFxPTest_a;
|
||||
wire [10:0] shiftValE_uid35_fpToFxPTest_b;
|
||||
logic [10:0] shiftValE_uid35_fpToFxPTest_o;
|
||||
wire [9:0] shiftValE_uid35_fpToFxPTest_q;
|
||||
wire [5:0] shiftValRaw_uid36_fpToFxPTest_in;
|
||||
wire [5:0] shiftValRaw_uid36_fpToFxPTest_b;
|
||||
wire [5:0] maxShiftCst_uid37_fpToFxPTest_q;
|
||||
wire [11:0] shiftOutOfRange_uid38_fpToFxPTest_a;
|
||||
wire [11:0] shiftOutOfRange_uid38_fpToFxPTest_b;
|
||||
logic [11:0] shiftOutOfRange_uid38_fpToFxPTest_o;
|
||||
wire [0:0] shiftOutOfRange_uid38_fpToFxPTest_n;
|
||||
wire [0:0] shiftVal_uid39_fpToFxPTest_s;
|
||||
reg [5:0] shiftVal_uid39_fpToFxPTest_q;
|
||||
wire [31:0] shifterIn_uid41_fpToFxPTest_q;
|
||||
wire [31:0] maxPosValueS_uid43_fpToFxPTest_q;
|
||||
wire [31:0] maxNegValueS_uid44_fpToFxPTest_q;
|
||||
wire [32:0] zRightShiferNoStickyOut_uid45_fpToFxPTest_q;
|
||||
wire [32:0] xXorSignE_uid46_fpToFxPTest_b;
|
||||
wire [32:0] xXorSignE_uid46_fpToFxPTest_qi;
|
||||
reg [32:0] xXorSignE_uid46_fpToFxPTest_q;
|
||||
wire [2:0] d0_uid47_fpToFxPTest_q;
|
||||
wire [33:0] sPostRndFull_uid48_fpToFxPTest_a;
|
||||
wire [33:0] sPostRndFull_uid48_fpToFxPTest_b;
|
||||
logic [33:0] sPostRndFull_uid48_fpToFxPTest_o;
|
||||
wire [33:0] sPostRndFull_uid48_fpToFxPTest_q;
|
||||
wire [32:0] sPostRnd_uid49_fpToFxPTest_in;
|
||||
wire [31:0] sPostRnd_uid49_fpToFxPTest_b;
|
||||
wire [34:0] sPostRnd_uid50_fpToFxPTest_in;
|
||||
wire [33:0] sPostRnd_uid50_fpToFxPTest_b;
|
||||
wire [35:0] rndOvfPos_uid51_fpToFxPTest_a;
|
||||
wire [35:0] rndOvfPos_uid51_fpToFxPTest_b;
|
||||
logic [35:0] rndOvfPos_uid51_fpToFxPTest_o;
|
||||
wire [0:0] rndOvfPos_uid51_fpToFxPTest_c;
|
||||
wire [0:0] ovfPostRnd_uid52_fpToFxPTest_q;
|
||||
wire [2:0] muxSelConc_uid53_fpToFxPTest_q;
|
||||
reg [1:0] muxSel_uid54_fpToFxPTest_q;
|
||||
wire [31:0] maxNegValueU_uid55_fpToFxPTest_q;
|
||||
wire [1:0] finalOut_uid56_fpToFxPTest_s;
|
||||
reg [31:0] finalOut_uid56_fpToFxPTest_q;
|
||||
wire [30:0] rightShiftStage0Idx1Rng1_uid60_rightShiferNoStickyOut_uid42_fpToFxPTest_b;
|
||||
wire [31:0] rightShiftStage0Idx1_uid62_rightShiferNoStickyOut_uid42_fpToFxPTest_q;
|
||||
wire [29:0] rightShiftStage0Idx2Rng2_uid63_rightShiferNoStickyOut_uid42_fpToFxPTest_b;
|
||||
wire [1:0] rightShiftStage0Idx2Pad2_uid64_rightShiferNoStickyOut_uid42_fpToFxPTest_q;
|
||||
wire [31:0] rightShiftStage0Idx2_uid65_rightShiferNoStickyOut_uid42_fpToFxPTest_q;
|
||||
wire [28:0] rightShiftStage0Idx3Rng3_uid66_rightShiferNoStickyOut_uid42_fpToFxPTest_b;
|
||||
wire [2:0] rightShiftStage0Idx3Pad3_uid67_rightShiferNoStickyOut_uid42_fpToFxPTest_q;
|
||||
wire [31:0] rightShiftStage0Idx3_uid68_rightShiferNoStickyOut_uid42_fpToFxPTest_q;
|
||||
wire [1:0] rightShiftStage0_uid70_rightShiferNoStickyOut_uid42_fpToFxPTest_s;
|
||||
reg [31:0] rightShiftStage0_uid70_rightShiferNoStickyOut_uid42_fpToFxPTest_q;
|
||||
wire [27:0] rightShiftStage1Idx1Rng4_uid71_rightShiferNoStickyOut_uid42_fpToFxPTest_b;
|
||||
wire [3:0] rightShiftStage1Idx1Pad4_uid72_rightShiferNoStickyOut_uid42_fpToFxPTest_q;
|
||||
wire [31:0] rightShiftStage1Idx1_uid73_rightShiferNoStickyOut_uid42_fpToFxPTest_q;
|
||||
wire [23:0] rightShiftStage1Idx2Rng8_uid74_rightShiferNoStickyOut_uid42_fpToFxPTest_b;
|
||||
wire [31:0] rightShiftStage1Idx2_uid76_rightShiferNoStickyOut_uid42_fpToFxPTest_q;
|
||||
wire [19:0] rightShiftStage1Idx3Rng12_uid77_rightShiferNoStickyOut_uid42_fpToFxPTest_b;
|
||||
wire [11:0] rightShiftStage1Idx3Pad12_uid78_rightShiferNoStickyOut_uid42_fpToFxPTest_q;
|
||||
wire [31:0] rightShiftStage1Idx3_uid79_rightShiferNoStickyOut_uid42_fpToFxPTest_q;
|
||||
wire [1:0] rightShiftStage1_uid81_rightShiferNoStickyOut_uid42_fpToFxPTest_s;
|
||||
reg [31:0] rightShiftStage1_uid81_rightShiferNoStickyOut_uid42_fpToFxPTest_q;
|
||||
wire [15:0] rightShiftStage2Idx1Rng16_uid82_rightShiferNoStickyOut_uid42_fpToFxPTest_b;
|
||||
wire [15:0] rightShiftStage2Idx1Pad16_uid83_rightShiferNoStickyOut_uid42_fpToFxPTest_q;
|
||||
wire [31:0] rightShiftStage2Idx1_uid84_rightShiferNoStickyOut_uid42_fpToFxPTest_q;
|
||||
wire [1:0] rightShiftStage2_uid88_rightShiferNoStickyOut_uid42_fpToFxPTest_s;
|
||||
reg [31:0] rightShiftStage2_uid88_rightShiferNoStickyOut_uid42_fpToFxPTest_q;
|
||||
wire [1:0] rightShiftStageSel0Dto0_uid69_rightShiferNoStickyOut_uid42_fpToFxPTest_merged_bit_select_b;
|
||||
wire [1:0] rightShiftStageSel0Dto0_uid69_rightShiferNoStickyOut_uid42_fpToFxPTest_merged_bit_select_c;
|
||||
wire [1:0] rightShiftStageSel0Dto0_uid69_rightShiferNoStickyOut_uid42_fpToFxPTest_merged_bit_select_d;
|
||||
reg [31:0] redist0_sPostRnd_uid49_fpToFxPTest_b_1_q;
|
||||
reg [0:0] redist1_udf_uid33_fpToFxPTest_n_3_q;
|
||||
reg [0:0] redist1_udf_uid33_fpToFxPTest_n_3_delay_0;
|
||||
reg [0:0] redist2_ovfExpRange_uid31_fpToFxPTest_n_3_q;
|
||||
reg [0:0] redist2_ovfExpRange_uid31_fpToFxPTest_n_3_delay_0;
|
||||
reg [0:0] redist3_signX_uid29_fpToFxPTest_q_3_q;
|
||||
reg [0:0] redist3_signX_uid29_fpToFxPTest_q_3_delay_0;
|
||||
reg [0:0] redist4_excN_x_uid16_fpToFxPTest_q_3_q;
|
||||
reg [0:0] redist4_excN_x_uid16_fpToFxPTest_q_3_delay_0;
|
||||
reg [0:0] redist4_excN_x_uid16_fpToFxPTest_q_3_delay_1;
|
||||
reg [0:0] redist5_excI_x_uid15_fpToFxPTest_q_3_q;
|
||||
reg [0:0] redist5_excI_x_uid15_fpToFxPTest_q_3_delay_0;
|
||||
|
||||
|
||||
// maxNegValueU_uid55_fpToFxPTest(CONSTANT,54)
|
||||
assign maxNegValueU_uid55_fpToFxPTest_q = 32'b00000000000000000000000000000000;
|
||||
|
||||
// maxNegValueS_uid44_fpToFxPTest(CONSTANT,43)
|
||||
assign maxNegValueS_uid44_fpToFxPTest_q = 32'b10000000000000000000000000000000;
|
||||
|
||||
// maxPosValueS_uid43_fpToFxPTest(CONSTANT,42)
|
||||
assign maxPosValueS_uid43_fpToFxPTest_q = 32'b01111111111111111111111111111111;
|
||||
|
||||
// d0_uid47_fpToFxPTest(CONSTANT,46)
|
||||
assign d0_uid47_fpToFxPTest_q = 3'b001;
|
||||
|
||||
// signX_uid27_fpToFxPTest(BITSELECT,26)@0
|
||||
assign signX_uid27_fpToFxPTest_b = a[31:31];
|
||||
|
||||
// frac_x_uid10_fpToFxPTest(BITSELECT,9)@0
|
||||
assign frac_x_uid10_fpToFxPTest_b = a[22:0];
|
||||
|
||||
// cstZeroWF_uid7_fpToFxPTest(CONSTANT,6)
|
||||
assign cstZeroWF_uid7_fpToFxPTest_q = 23'b00000000000000000000000;
|
||||
|
||||
// fracXIsZero_uid13_fpToFxPTest(LOGICAL,12)@0
|
||||
assign fracXIsZero_uid13_fpToFxPTest_q = cstZeroWF_uid7_fpToFxPTest_q == frac_x_uid10_fpToFxPTest_b ? 1'b1 : 1'b0;
|
||||
|
||||
// fracXIsNotZero_uid14_fpToFxPTest(LOGICAL,13)@0
|
||||
assign fracXIsNotZero_uid14_fpToFxPTest_q = ~ (fracXIsZero_uid13_fpToFxPTest_q);
|
||||
|
||||
// cstAllOWE_uid6_fpToFxPTest(CONSTANT,5)
|
||||
assign cstAllOWE_uid6_fpToFxPTest_q = 8'b11111111;
|
||||
|
||||
// exp_x_uid9_fpToFxPTest(BITSELECT,8)@0
|
||||
assign exp_x_uid9_fpToFxPTest_b = a[30:23];
|
||||
|
||||
// expXIsMax_uid12_fpToFxPTest(LOGICAL,11)@0
|
||||
assign expXIsMax_uid12_fpToFxPTest_q = exp_x_uid9_fpToFxPTest_b == cstAllOWE_uid6_fpToFxPTest_q ? 1'b1 : 1'b0;
|
||||
|
||||
// excN_x_uid16_fpToFxPTest(LOGICAL,15)@0
|
||||
assign excN_x_uid16_fpToFxPTest_q = expXIsMax_uid12_fpToFxPTest_q & fracXIsNotZero_uid14_fpToFxPTest_q;
|
||||
|
||||
// notNan_uid28_fpToFxPTest(LOGICAL,27)@0
|
||||
assign notNan_uid28_fpToFxPTest_q = ~ (excN_x_uid16_fpToFxPTest_q);
|
||||
|
||||
// signX_uid29_fpToFxPTest(LOGICAL,28)@0 + 1
|
||||
assign signX_uid29_fpToFxPTest_qi = notNan_uid28_fpToFxPTest_q & signX_uid27_fpToFxPTest_b;
|
||||
dspba_delay_ver #( .width(1), .depth(1), .reset_kind("SYNC"), .phase(0), .modulus(1) )
|
||||
signX_uid29_fpToFxPTest_delay ( .xin(signX_uid29_fpToFxPTest_qi), .xout(signX_uid29_fpToFxPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// GND(CONSTANT,0)
|
||||
assign GND_q = 1'b0;
|
||||
|
||||
// rightShiftStage2Idx1Pad16_uid83_rightShiferNoStickyOut_uid42_fpToFxPTest(CONSTANT,82)
|
||||
assign rightShiftStage2Idx1Pad16_uid83_rightShiferNoStickyOut_uid42_fpToFxPTest_q = 16'b0000000000000000;
|
||||
|
||||
// rightShiftStage2Idx1Rng16_uid82_rightShiferNoStickyOut_uid42_fpToFxPTest(BITSELECT,81)@1
|
||||
assign rightShiftStage2Idx1Rng16_uid82_rightShiferNoStickyOut_uid42_fpToFxPTest_b = rightShiftStage1_uid81_rightShiferNoStickyOut_uid42_fpToFxPTest_q[31:16];
|
||||
|
||||
// rightShiftStage2Idx1_uid84_rightShiferNoStickyOut_uid42_fpToFxPTest(BITJOIN,83)@1
|
||||
assign rightShiftStage2Idx1_uid84_rightShiferNoStickyOut_uid42_fpToFxPTest_q = {rightShiftStage2Idx1Pad16_uid83_rightShiferNoStickyOut_uid42_fpToFxPTest_q, rightShiftStage2Idx1Rng16_uid82_rightShiferNoStickyOut_uid42_fpToFxPTest_b};
|
||||
|
||||
// rightShiftStage1Idx3Pad12_uid78_rightShiferNoStickyOut_uid42_fpToFxPTest(CONSTANT,77)
|
||||
assign rightShiftStage1Idx3Pad12_uid78_rightShiferNoStickyOut_uid42_fpToFxPTest_q = 12'b000000000000;
|
||||
|
||||
// rightShiftStage1Idx3Rng12_uid77_rightShiferNoStickyOut_uid42_fpToFxPTest(BITSELECT,76)@1
|
||||
assign rightShiftStage1Idx3Rng12_uid77_rightShiferNoStickyOut_uid42_fpToFxPTest_b = rightShiftStage0_uid70_rightShiferNoStickyOut_uid42_fpToFxPTest_q[31:12];
|
||||
|
||||
// rightShiftStage1Idx3_uid79_rightShiferNoStickyOut_uid42_fpToFxPTest(BITJOIN,78)@1
|
||||
assign rightShiftStage1Idx3_uid79_rightShiferNoStickyOut_uid42_fpToFxPTest_q = {rightShiftStage1Idx3Pad12_uid78_rightShiferNoStickyOut_uid42_fpToFxPTest_q, rightShiftStage1Idx3Rng12_uid77_rightShiferNoStickyOut_uid42_fpToFxPTest_b};
|
||||
|
||||
// cstAllZWE_uid8_fpToFxPTest(CONSTANT,7)
|
||||
assign cstAllZWE_uid8_fpToFxPTest_q = 8'b00000000;
|
||||
|
||||
// rightShiftStage1Idx2Rng8_uid74_rightShiferNoStickyOut_uid42_fpToFxPTest(BITSELECT,73)@1
|
||||
assign rightShiftStage1Idx2Rng8_uid74_rightShiferNoStickyOut_uid42_fpToFxPTest_b = rightShiftStage0_uid70_rightShiferNoStickyOut_uid42_fpToFxPTest_q[31:8];
|
||||
|
||||
// rightShiftStage1Idx2_uid76_rightShiferNoStickyOut_uid42_fpToFxPTest(BITJOIN,75)@1
|
||||
assign rightShiftStage1Idx2_uid76_rightShiferNoStickyOut_uid42_fpToFxPTest_q = {cstAllZWE_uid8_fpToFxPTest_q, rightShiftStage1Idx2Rng8_uid74_rightShiferNoStickyOut_uid42_fpToFxPTest_b};
|
||||
|
||||
// rightShiftStage1Idx1Pad4_uid72_rightShiferNoStickyOut_uid42_fpToFxPTest(CONSTANT,71)
|
||||
assign rightShiftStage1Idx1Pad4_uid72_rightShiferNoStickyOut_uid42_fpToFxPTest_q = 4'b0000;
|
||||
|
||||
// rightShiftStage1Idx1Rng4_uid71_rightShiferNoStickyOut_uid42_fpToFxPTest(BITSELECT,70)@1
|
||||
assign rightShiftStage1Idx1Rng4_uid71_rightShiferNoStickyOut_uid42_fpToFxPTest_b = rightShiftStage0_uid70_rightShiferNoStickyOut_uid42_fpToFxPTest_q[31:4];
|
||||
|
||||
// rightShiftStage1Idx1_uid73_rightShiferNoStickyOut_uid42_fpToFxPTest(BITJOIN,72)@1
|
||||
assign rightShiftStage1Idx1_uid73_rightShiferNoStickyOut_uid42_fpToFxPTest_q = {rightShiftStage1Idx1Pad4_uid72_rightShiferNoStickyOut_uid42_fpToFxPTest_q, rightShiftStage1Idx1Rng4_uid71_rightShiferNoStickyOut_uid42_fpToFxPTest_b};
|
||||
|
||||
// rightShiftStage0Idx3Pad3_uid67_rightShiferNoStickyOut_uid42_fpToFxPTest(CONSTANT,66)
|
||||
assign rightShiftStage0Idx3Pad3_uid67_rightShiferNoStickyOut_uid42_fpToFxPTest_q = 3'b000;
|
||||
|
||||
// rightShiftStage0Idx3Rng3_uid66_rightShiferNoStickyOut_uid42_fpToFxPTest(BITSELECT,65)@1
|
||||
assign rightShiftStage0Idx3Rng3_uid66_rightShiferNoStickyOut_uid42_fpToFxPTest_b = shifterIn_uid41_fpToFxPTest_q[31:3];
|
||||
|
||||
// rightShiftStage0Idx3_uid68_rightShiferNoStickyOut_uid42_fpToFxPTest(BITJOIN,67)@1
|
||||
assign rightShiftStage0Idx3_uid68_rightShiferNoStickyOut_uid42_fpToFxPTest_q = {rightShiftStage0Idx3Pad3_uid67_rightShiferNoStickyOut_uid42_fpToFxPTest_q, rightShiftStage0Idx3Rng3_uid66_rightShiferNoStickyOut_uid42_fpToFxPTest_b};
|
||||
|
||||
// rightShiftStage0Idx2Pad2_uid64_rightShiferNoStickyOut_uid42_fpToFxPTest(CONSTANT,63)
|
||||
assign rightShiftStage0Idx2Pad2_uid64_rightShiferNoStickyOut_uid42_fpToFxPTest_q = 2'b00;
|
||||
|
||||
// rightShiftStage0Idx2Rng2_uid63_rightShiferNoStickyOut_uid42_fpToFxPTest(BITSELECT,62)@1
|
||||
assign rightShiftStage0Idx2Rng2_uid63_rightShiferNoStickyOut_uid42_fpToFxPTest_b = shifterIn_uid41_fpToFxPTest_q[31:2];
|
||||
|
||||
// rightShiftStage0Idx2_uid65_rightShiferNoStickyOut_uid42_fpToFxPTest(BITJOIN,64)@1
|
||||
assign rightShiftStage0Idx2_uid65_rightShiferNoStickyOut_uid42_fpToFxPTest_q = {rightShiftStage0Idx2Pad2_uid64_rightShiferNoStickyOut_uid42_fpToFxPTest_q, rightShiftStage0Idx2Rng2_uid63_rightShiferNoStickyOut_uid42_fpToFxPTest_b};
|
||||
|
||||
// rightShiftStage0Idx1Rng1_uid60_rightShiferNoStickyOut_uid42_fpToFxPTest(BITSELECT,59)@1
|
||||
assign rightShiftStage0Idx1Rng1_uid60_rightShiferNoStickyOut_uid42_fpToFxPTest_b = shifterIn_uid41_fpToFxPTest_q[31:1];
|
||||
|
||||
// rightShiftStage0Idx1_uid62_rightShiferNoStickyOut_uid42_fpToFxPTest(BITJOIN,61)@1
|
||||
assign rightShiftStage0Idx1_uid62_rightShiferNoStickyOut_uid42_fpToFxPTest_q = {GND_q, rightShiftStage0Idx1Rng1_uid60_rightShiferNoStickyOut_uid42_fpToFxPTest_b};
|
||||
|
||||
// excZ_x_uid11_fpToFxPTest(LOGICAL,10)@0
|
||||
assign excZ_x_uid11_fpToFxPTest_q = exp_x_uid9_fpToFxPTest_b == cstAllZWE_uid8_fpToFxPTest_q ? 1'b1 : 1'b0;
|
||||
|
||||
// invExcXZ_uid24_fpToFxPTest(LOGICAL,23)@0 + 1
|
||||
assign invExcXZ_uid24_fpToFxPTest_qi = ~ (excZ_x_uid11_fpToFxPTest_q);
|
||||
dspba_delay_ver #( .width(1), .depth(1), .reset_kind("SYNC"), .phase(0), .modulus(1) )
|
||||
invExcXZ_uid24_fpToFxPTest_delay ( .xin(invExcXZ_uid24_fpToFxPTest_qi), .xout(invExcXZ_uid24_fpToFxPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// fracPostZ_uid23_fpToFxPTest(MUX,22)@0 + 1
|
||||
assign fracPostZ_uid23_fpToFxPTest_s = excZ_x_uid11_fpToFxPTest_q;
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
fracPostZ_uid23_fpToFxPTest_q <= 23'b0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
unique case (fracPostZ_uid23_fpToFxPTest_s)
|
||||
1'b0 : fracPostZ_uid23_fpToFxPTest_q <= frac_x_uid10_fpToFxPTest_b;
|
||||
1'b1 : fracPostZ_uid23_fpToFxPTest_q <= cstZeroWF_uid7_fpToFxPTest_q;
|
||||
default : fracPostZ_uid23_fpToFxPTest_q <= 23'b0;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
// oFracX_uid25_fpToFxPTest(BITJOIN,24)@1
|
||||
assign oFracX_uid25_fpToFxPTest_q = {invExcXZ_uid24_fpToFxPTest_q, fracPostZ_uid23_fpToFxPTest_q};
|
||||
|
||||
// shifterIn_uid41_fpToFxPTest(BITJOIN,40)@1
|
||||
assign shifterIn_uid41_fpToFxPTest_q = {oFracX_uid25_fpToFxPTest_q, cstAllZWE_uid8_fpToFxPTest_q};
|
||||
|
||||
// rightShiftStage0_uid70_rightShiferNoStickyOut_uid42_fpToFxPTest(MUX,69)@1
|
||||
assign rightShiftStage0_uid70_rightShiferNoStickyOut_uid42_fpToFxPTest_s = rightShiftStageSel0Dto0_uid69_rightShiferNoStickyOut_uid42_fpToFxPTest_merged_bit_select_b;
|
||||
always @(rightShiftStage0_uid70_rightShiferNoStickyOut_uid42_fpToFxPTest_s or en or shifterIn_uid41_fpToFxPTest_q or rightShiftStage0Idx1_uid62_rightShiferNoStickyOut_uid42_fpToFxPTest_q or rightShiftStage0Idx2_uid65_rightShiferNoStickyOut_uid42_fpToFxPTest_q or rightShiftStage0Idx3_uid68_rightShiferNoStickyOut_uid42_fpToFxPTest_q)
|
||||
begin
|
||||
unique case (rightShiftStage0_uid70_rightShiferNoStickyOut_uid42_fpToFxPTest_s)
|
||||
2'b00 : rightShiftStage0_uid70_rightShiferNoStickyOut_uid42_fpToFxPTest_q = shifterIn_uid41_fpToFxPTest_q;
|
||||
2'b01 : rightShiftStage0_uid70_rightShiferNoStickyOut_uid42_fpToFxPTest_q = rightShiftStage0Idx1_uid62_rightShiferNoStickyOut_uid42_fpToFxPTest_q;
|
||||
2'b10 : rightShiftStage0_uid70_rightShiferNoStickyOut_uid42_fpToFxPTest_q = rightShiftStage0Idx2_uid65_rightShiferNoStickyOut_uid42_fpToFxPTest_q;
|
||||
2'b11 : rightShiftStage0_uid70_rightShiferNoStickyOut_uid42_fpToFxPTest_q = rightShiftStage0Idx3_uid68_rightShiferNoStickyOut_uid42_fpToFxPTest_q;
|
||||
default : rightShiftStage0_uid70_rightShiferNoStickyOut_uid42_fpToFxPTest_q = 32'b0;
|
||||
endcase
|
||||
end
|
||||
|
||||
// rightShiftStage1_uid81_rightShiferNoStickyOut_uid42_fpToFxPTest(MUX,80)@1
|
||||
assign rightShiftStage1_uid81_rightShiferNoStickyOut_uid42_fpToFxPTest_s = rightShiftStageSel0Dto0_uid69_rightShiferNoStickyOut_uid42_fpToFxPTest_merged_bit_select_c;
|
||||
always @(rightShiftStage1_uid81_rightShiferNoStickyOut_uid42_fpToFxPTest_s or en or rightShiftStage0_uid70_rightShiferNoStickyOut_uid42_fpToFxPTest_q or rightShiftStage1Idx1_uid73_rightShiferNoStickyOut_uid42_fpToFxPTest_q or rightShiftStage1Idx2_uid76_rightShiferNoStickyOut_uid42_fpToFxPTest_q or rightShiftStage1Idx3_uid79_rightShiferNoStickyOut_uid42_fpToFxPTest_q)
|
||||
begin
|
||||
unique case (rightShiftStage1_uid81_rightShiferNoStickyOut_uid42_fpToFxPTest_s)
|
||||
2'b00 : rightShiftStage1_uid81_rightShiferNoStickyOut_uid42_fpToFxPTest_q = rightShiftStage0_uid70_rightShiferNoStickyOut_uid42_fpToFxPTest_q;
|
||||
2'b01 : rightShiftStage1_uid81_rightShiferNoStickyOut_uid42_fpToFxPTest_q = rightShiftStage1Idx1_uid73_rightShiferNoStickyOut_uid42_fpToFxPTest_q;
|
||||
2'b10 : rightShiftStage1_uid81_rightShiferNoStickyOut_uid42_fpToFxPTest_q = rightShiftStage1Idx2_uid76_rightShiferNoStickyOut_uid42_fpToFxPTest_q;
|
||||
2'b11 : rightShiftStage1_uid81_rightShiferNoStickyOut_uid42_fpToFxPTest_q = rightShiftStage1Idx3_uid79_rightShiferNoStickyOut_uid42_fpToFxPTest_q;
|
||||
default : rightShiftStage1_uid81_rightShiferNoStickyOut_uid42_fpToFxPTest_q = 32'b0;
|
||||
endcase
|
||||
end
|
||||
|
||||
// maxShiftCst_uid37_fpToFxPTest(CONSTANT,36)
|
||||
assign maxShiftCst_uid37_fpToFxPTest_q = 6'b100000;
|
||||
|
||||
// ovfExpVal_uid34_fpToFxPTest(CONSTANT,33)
|
||||
assign ovfExpVal_uid34_fpToFxPTest_q = 9'b010011101;
|
||||
|
||||
// shiftValE_uid35_fpToFxPTest(SUB,34)@0
|
||||
assign shiftValE_uid35_fpToFxPTest_a = {{2{ovfExpVal_uid34_fpToFxPTest_q[8]}}, ovfExpVal_uid34_fpToFxPTest_q};
|
||||
assign shiftValE_uid35_fpToFxPTest_b = {3'b000, exp_x_uid9_fpToFxPTest_b};
|
||||
assign shiftValE_uid35_fpToFxPTest_o = $signed(shiftValE_uid35_fpToFxPTest_a) - $signed(shiftValE_uid35_fpToFxPTest_b);
|
||||
assign shiftValE_uid35_fpToFxPTest_q = shiftValE_uid35_fpToFxPTest_o[9:0];
|
||||
|
||||
// shiftValRaw_uid36_fpToFxPTest(BITSELECT,35)@0
|
||||
assign shiftValRaw_uid36_fpToFxPTest_in = shiftValE_uid35_fpToFxPTest_q[5:0];
|
||||
assign shiftValRaw_uid36_fpToFxPTest_b = shiftValRaw_uid36_fpToFxPTest_in[5:0];
|
||||
|
||||
// shiftOutOfRange_uid38_fpToFxPTest(COMPARE,37)@0
|
||||
assign shiftOutOfRange_uid38_fpToFxPTest_a = {{2{shiftValE_uid35_fpToFxPTest_q[9]}}, shiftValE_uid35_fpToFxPTest_q};
|
||||
assign shiftOutOfRange_uid38_fpToFxPTest_b = {6'b000000, maxShiftCst_uid37_fpToFxPTest_q};
|
||||
assign shiftOutOfRange_uid38_fpToFxPTest_o = $signed(shiftOutOfRange_uid38_fpToFxPTest_a) - $signed(shiftOutOfRange_uid38_fpToFxPTest_b);
|
||||
assign shiftOutOfRange_uid38_fpToFxPTest_n[0] = ~ (shiftOutOfRange_uid38_fpToFxPTest_o[11]);
|
||||
|
||||
// shiftVal_uid39_fpToFxPTest(MUX,38)@0 + 1
|
||||
assign shiftVal_uid39_fpToFxPTest_s = shiftOutOfRange_uid38_fpToFxPTest_n;
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
shiftVal_uid39_fpToFxPTest_q <= 6'b0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
unique case (shiftVal_uid39_fpToFxPTest_s)
|
||||
1'b0 : shiftVal_uid39_fpToFxPTest_q <= shiftValRaw_uid36_fpToFxPTest_b;
|
||||
1'b1 : shiftVal_uid39_fpToFxPTest_q <= maxShiftCst_uid37_fpToFxPTest_q;
|
||||
default : shiftVal_uid39_fpToFxPTest_q <= 6'b0;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
// rightShiftStageSel0Dto0_uid69_rightShiferNoStickyOut_uid42_fpToFxPTest_merged_bit_select(BITSELECT,89)@1
|
||||
assign rightShiftStageSel0Dto0_uid69_rightShiferNoStickyOut_uid42_fpToFxPTest_merged_bit_select_b = shiftVal_uid39_fpToFxPTest_q[1:0];
|
||||
assign rightShiftStageSel0Dto0_uid69_rightShiferNoStickyOut_uid42_fpToFxPTest_merged_bit_select_c = shiftVal_uid39_fpToFxPTest_q[3:2];
|
||||
assign rightShiftStageSel0Dto0_uid69_rightShiferNoStickyOut_uid42_fpToFxPTest_merged_bit_select_d = shiftVal_uid39_fpToFxPTest_q[5:4];
|
||||
|
||||
// rightShiftStage2_uid88_rightShiferNoStickyOut_uid42_fpToFxPTest(MUX,87)@1
|
||||
assign rightShiftStage2_uid88_rightShiferNoStickyOut_uid42_fpToFxPTest_s = rightShiftStageSel0Dto0_uid69_rightShiferNoStickyOut_uid42_fpToFxPTest_merged_bit_select_d;
|
||||
always @(rightShiftStage2_uid88_rightShiferNoStickyOut_uid42_fpToFxPTest_s or en or rightShiftStage1_uid81_rightShiferNoStickyOut_uid42_fpToFxPTest_q or rightShiftStage2Idx1_uid84_rightShiferNoStickyOut_uid42_fpToFxPTest_q or maxNegValueU_uid55_fpToFxPTest_q)
|
||||
begin
|
||||
unique case (rightShiftStage2_uid88_rightShiferNoStickyOut_uid42_fpToFxPTest_s)
|
||||
2'b00 : rightShiftStage2_uid88_rightShiferNoStickyOut_uid42_fpToFxPTest_q = rightShiftStage1_uid81_rightShiferNoStickyOut_uid42_fpToFxPTest_q;
|
||||
2'b01 : rightShiftStage2_uid88_rightShiferNoStickyOut_uid42_fpToFxPTest_q = rightShiftStage2Idx1_uid84_rightShiferNoStickyOut_uid42_fpToFxPTest_q;
|
||||
2'b10 : rightShiftStage2_uid88_rightShiferNoStickyOut_uid42_fpToFxPTest_q = maxNegValueU_uid55_fpToFxPTest_q;
|
||||
2'b11 : rightShiftStage2_uid88_rightShiferNoStickyOut_uid42_fpToFxPTest_q = maxNegValueU_uid55_fpToFxPTest_q;
|
||||
default : rightShiftStage2_uid88_rightShiferNoStickyOut_uid42_fpToFxPTest_q = 32'b0;
|
||||
endcase
|
||||
end
|
||||
|
||||
// zRightShiferNoStickyOut_uid45_fpToFxPTest(BITJOIN,44)@1
|
||||
assign zRightShiferNoStickyOut_uid45_fpToFxPTest_q = {GND_q, rightShiftStage2_uid88_rightShiferNoStickyOut_uid42_fpToFxPTest_q};
|
||||
|
||||
// xXorSignE_uid46_fpToFxPTest(LOGICAL,45)@1 + 1
|
||||
assign xXorSignE_uid46_fpToFxPTest_b = {{32{signX_uid29_fpToFxPTest_q[0]}}, signX_uid29_fpToFxPTest_q};
|
||||
assign xXorSignE_uid46_fpToFxPTest_qi = zRightShiferNoStickyOut_uid45_fpToFxPTest_q ^ xXorSignE_uid46_fpToFxPTest_b;
|
||||
dspba_delay_ver #( .width(33), .depth(1), .reset_kind("SYNC"), .phase(0), .modulus(1) )
|
||||
xXorSignE_uid46_fpToFxPTest_delay ( .xin(xXorSignE_uid46_fpToFxPTest_qi), .xout(xXorSignE_uid46_fpToFxPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// sPostRndFull_uid48_fpToFxPTest(ADD,47)@2
|
||||
assign sPostRndFull_uid48_fpToFxPTest_a = {{1{xXorSignE_uid46_fpToFxPTest_q[32]}}, xXorSignE_uid46_fpToFxPTest_q};
|
||||
assign sPostRndFull_uid48_fpToFxPTest_b = {{31{d0_uid47_fpToFxPTest_q[2]}}, d0_uid47_fpToFxPTest_q};
|
||||
assign sPostRndFull_uid48_fpToFxPTest_o = $signed(sPostRndFull_uid48_fpToFxPTest_a) + $signed(sPostRndFull_uid48_fpToFxPTest_b);
|
||||
assign sPostRndFull_uid48_fpToFxPTest_q = sPostRndFull_uid48_fpToFxPTest_o[33:0];
|
||||
|
||||
// sPostRnd_uid49_fpToFxPTest(BITSELECT,48)@2
|
||||
assign sPostRnd_uid49_fpToFxPTest_in = sPostRndFull_uid48_fpToFxPTest_q[32:0];
|
||||
assign sPostRnd_uid49_fpToFxPTest_b = sPostRnd_uid49_fpToFxPTest_in[32:1];
|
||||
|
||||
// redist0_sPostRnd_uid49_fpToFxPTest_b_1(DELAY,90)
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
redist0_sPostRnd_uid49_fpToFxPTest_b_1_q <= '0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
redist0_sPostRnd_uid49_fpToFxPTest_b_1_q <= sPostRnd_uid49_fpToFxPTest_b;
|
||||
end
|
||||
end
|
||||
|
||||
// redist3_signX_uid29_fpToFxPTest_q_3(DELAY,93)
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
redist3_signX_uid29_fpToFxPTest_q_3_delay_0 <= '0;
|
||||
redist3_signX_uid29_fpToFxPTest_q_3_q <= '0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
redist3_signX_uid29_fpToFxPTest_q_3_delay_0 <= signX_uid29_fpToFxPTest_q;
|
||||
redist3_signX_uid29_fpToFxPTest_q_3_q <= redist3_signX_uid29_fpToFxPTest_q_3_delay_0;
|
||||
end
|
||||
end
|
||||
|
||||
// udfExpVal_uid32_fpToFxPTest(CONSTANT,31)
|
||||
assign udfExpVal_uid32_fpToFxPTest_q = 8'b01111101;
|
||||
|
||||
// udf_uid33_fpToFxPTest(COMPARE,32)@0 + 1
|
||||
assign udf_uid33_fpToFxPTest_a = {{3{udfExpVal_uid32_fpToFxPTest_q[7]}}, udfExpVal_uid32_fpToFxPTest_q};
|
||||
assign udf_uid33_fpToFxPTest_b = {3'b000, exp_x_uid9_fpToFxPTest_b};
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
udf_uid33_fpToFxPTest_o <= 11'b0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
udf_uid33_fpToFxPTest_o <= $signed(udf_uid33_fpToFxPTest_a) - $signed(udf_uid33_fpToFxPTest_b);
|
||||
end
|
||||
end
|
||||
assign udf_uid33_fpToFxPTest_n[0] = ~ (udf_uid33_fpToFxPTest_o[10]);
|
||||
|
||||
// redist1_udf_uid33_fpToFxPTest_n_3(DELAY,91)
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
redist1_udf_uid33_fpToFxPTest_n_3_delay_0 <= '0;
|
||||
redist1_udf_uid33_fpToFxPTest_n_3_q <= '0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
redist1_udf_uid33_fpToFxPTest_n_3_delay_0 <= udf_uid33_fpToFxPTest_n;
|
||||
redist1_udf_uid33_fpToFxPTest_n_3_q <= redist1_udf_uid33_fpToFxPTest_n_3_delay_0;
|
||||
end
|
||||
end
|
||||
|
||||
// sPostRnd_uid50_fpToFxPTest(BITSELECT,49)@2
|
||||
assign sPostRnd_uid50_fpToFxPTest_in = {{1{sPostRndFull_uid48_fpToFxPTest_q[33]}}, sPostRndFull_uid48_fpToFxPTest_q};
|
||||
assign sPostRnd_uid50_fpToFxPTest_b = sPostRnd_uid50_fpToFxPTest_in[34:1];
|
||||
|
||||
// rndOvfPos_uid51_fpToFxPTest(COMPARE,50)@2 + 1
|
||||
assign rndOvfPos_uid51_fpToFxPTest_a = {4'b0000, maxPosValueS_uid43_fpToFxPTest_q};
|
||||
assign rndOvfPos_uid51_fpToFxPTest_b = {{2{sPostRnd_uid50_fpToFxPTest_b[33]}}, sPostRnd_uid50_fpToFxPTest_b};
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
rndOvfPos_uid51_fpToFxPTest_o <= 36'b0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
rndOvfPos_uid51_fpToFxPTest_o <= $signed(rndOvfPos_uid51_fpToFxPTest_a) - $signed(rndOvfPos_uid51_fpToFxPTest_b);
|
||||
end
|
||||
end
|
||||
assign rndOvfPos_uid51_fpToFxPTest_c[0] = rndOvfPos_uid51_fpToFxPTest_o[35];
|
||||
|
||||
// ovfExpVal_uid30_fpToFxPTest(CONSTANT,29)
|
||||
assign ovfExpVal_uid30_fpToFxPTest_q = 9'b010011110;
|
||||
|
||||
// ovfExpRange_uid31_fpToFxPTest(COMPARE,30)@0 + 1
|
||||
assign ovfExpRange_uid31_fpToFxPTest_a = {3'b000, exp_x_uid9_fpToFxPTest_b};
|
||||
assign ovfExpRange_uid31_fpToFxPTest_b = {{2{ovfExpVal_uid30_fpToFxPTest_q[8]}}, ovfExpVal_uid30_fpToFxPTest_q};
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
ovfExpRange_uid31_fpToFxPTest_o <= 11'b0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
ovfExpRange_uid31_fpToFxPTest_o <= $signed(ovfExpRange_uid31_fpToFxPTest_a) - $signed(ovfExpRange_uid31_fpToFxPTest_b);
|
||||
end
|
||||
end
|
||||
assign ovfExpRange_uid31_fpToFxPTest_n[0] = ~ (ovfExpRange_uid31_fpToFxPTest_o[10]);
|
||||
|
||||
// redist2_ovfExpRange_uid31_fpToFxPTest_n_3(DELAY,92)
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
redist2_ovfExpRange_uid31_fpToFxPTest_n_3_delay_0 <= '0;
|
||||
redist2_ovfExpRange_uid31_fpToFxPTest_n_3_q <= '0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
redist2_ovfExpRange_uid31_fpToFxPTest_n_3_delay_0 <= ovfExpRange_uid31_fpToFxPTest_n;
|
||||
redist2_ovfExpRange_uid31_fpToFxPTest_n_3_q <= redist2_ovfExpRange_uid31_fpToFxPTest_n_3_delay_0;
|
||||
end
|
||||
end
|
||||
|
||||
// excI_x_uid15_fpToFxPTest(LOGICAL,14)@0 + 1
|
||||
assign excI_x_uid15_fpToFxPTest_qi = expXIsMax_uid12_fpToFxPTest_q & fracXIsZero_uid13_fpToFxPTest_q;
|
||||
dspba_delay_ver #( .width(1), .depth(1), .reset_kind("SYNC"), .phase(0), .modulus(1) )
|
||||
excI_x_uid15_fpToFxPTest_delay ( .xin(excI_x_uid15_fpToFxPTest_qi), .xout(excI_x_uid15_fpToFxPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// redist5_excI_x_uid15_fpToFxPTest_q_3(DELAY,95)
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
redist5_excI_x_uid15_fpToFxPTest_q_3_delay_0 <= '0;
|
||||
redist5_excI_x_uid15_fpToFxPTest_q_3_q <= '0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
redist5_excI_x_uid15_fpToFxPTest_q_3_delay_0 <= excI_x_uid15_fpToFxPTest_q;
|
||||
redist5_excI_x_uid15_fpToFxPTest_q_3_q <= redist5_excI_x_uid15_fpToFxPTest_q_3_delay_0;
|
||||
end
|
||||
end
|
||||
|
||||
// redist4_excN_x_uid16_fpToFxPTest_q_3(DELAY,94)
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
redist4_excN_x_uid16_fpToFxPTest_q_3_delay_0 <= '0;
|
||||
redist4_excN_x_uid16_fpToFxPTest_q_3_delay_1 <= '0;
|
||||
redist4_excN_x_uid16_fpToFxPTest_q_3_q <= '0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
redist4_excN_x_uid16_fpToFxPTest_q_3_delay_0 <= excN_x_uid16_fpToFxPTest_q;
|
||||
redist4_excN_x_uid16_fpToFxPTest_q_3_delay_1 <= redist4_excN_x_uid16_fpToFxPTest_q_3_delay_0;
|
||||
redist4_excN_x_uid16_fpToFxPTest_q_3_q <= redist4_excN_x_uid16_fpToFxPTest_q_3_delay_1;
|
||||
end
|
||||
end
|
||||
|
||||
// ovfPostRnd_uid52_fpToFxPTest(LOGICAL,51)@3
|
||||
assign ovfPostRnd_uid52_fpToFxPTest_q = redist4_excN_x_uid16_fpToFxPTest_q_3_q | redist5_excI_x_uid15_fpToFxPTest_q_3_q | redist2_ovfExpRange_uid31_fpToFxPTest_n_3_q | rndOvfPos_uid51_fpToFxPTest_c;
|
||||
|
||||
// muxSelConc_uid53_fpToFxPTest(BITJOIN,52)@3
|
||||
assign muxSelConc_uid53_fpToFxPTest_q = {redist3_signX_uid29_fpToFxPTest_q_3_q, redist1_udf_uid33_fpToFxPTest_n_3_q, ovfPostRnd_uid52_fpToFxPTest_q};
|
||||
|
||||
// muxSel_uid54_fpToFxPTest(LOOKUP,53)@3
|
||||
always @(muxSelConc_uid53_fpToFxPTest_q)
|
||||
begin
|
||||
// Begin reserved scope level
|
||||
unique case (muxSelConc_uid53_fpToFxPTest_q)
|
||||
3'b000 : muxSel_uid54_fpToFxPTest_q = 2'b00;
|
||||
3'b001 : muxSel_uid54_fpToFxPTest_q = 2'b01;
|
||||
3'b010 : muxSel_uid54_fpToFxPTest_q = 2'b11;
|
||||
3'b011 : muxSel_uid54_fpToFxPTest_q = 2'b11;
|
||||
3'b100 : muxSel_uid54_fpToFxPTest_q = 2'b00;
|
||||
3'b101 : muxSel_uid54_fpToFxPTest_q = 2'b10;
|
||||
3'b110 : muxSel_uid54_fpToFxPTest_q = 2'b11;
|
||||
3'b111 : muxSel_uid54_fpToFxPTest_q = 2'b11;
|
||||
default : begin
|
||||
// unreachable
|
||||
muxSel_uid54_fpToFxPTest_q = 2'bxx;
|
||||
end
|
||||
endcase
|
||||
// End reserved scope level
|
||||
end
|
||||
|
||||
// finalOut_uid56_fpToFxPTest(MUX,55)@3
|
||||
assign finalOut_uid56_fpToFxPTest_s = muxSel_uid54_fpToFxPTest_q;
|
||||
always @(finalOut_uid56_fpToFxPTest_s or en or redist0_sPostRnd_uid49_fpToFxPTest_b_1_q or maxPosValueS_uid43_fpToFxPTest_q or maxNegValueS_uid44_fpToFxPTest_q or maxNegValueU_uid55_fpToFxPTest_q)
|
||||
begin
|
||||
unique case (finalOut_uid56_fpToFxPTest_s)
|
||||
2'b00 : finalOut_uid56_fpToFxPTest_q = redist0_sPostRnd_uid49_fpToFxPTest_b_1_q;
|
||||
2'b01 : finalOut_uid56_fpToFxPTest_q = maxPosValueS_uid43_fpToFxPTest_q;
|
||||
2'b10 : finalOut_uid56_fpToFxPTest_q = maxNegValueS_uid44_fpToFxPTest_q;
|
||||
2'b11 : finalOut_uid56_fpToFxPTest_q = maxNegValueU_uid55_fpToFxPTest_q;
|
||||
default : finalOut_uid56_fpToFxPTest_q = 32'b0;
|
||||
endcase
|
||||
end
|
||||
|
||||
// xOut(GPOUT,4)@3
|
||||
assign q = finalOut_uid56_fpToFxPTest_q;
|
||||
|
||||
endmodule
|
||||
563
hw/rtl/fp_cores/altera/stratix10/acl_ftou.sv
Normal file
563
hw/rtl/fp_cores/altera/stratix10/acl_ftou.sv
Normal file
|
|
@ -0,0 +1,563 @@
|
|||
// -------------------------------------------------------------------------
|
||||
// High Level Design Compiler for Intel(R) FPGAs Version 18.1 (Release Build #277)
|
||||
// Quartus Prime development tool and MATLAB/Simulink Interface
|
||||
//
|
||||
// Legal Notice: Copyright 2019 Intel Corporation. All rights reserved.
|
||||
// Your use of Intel Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly
|
||||
// subject to the terms and conditions of the Intel FPGA Software License
|
||||
// Agreement, Intel MegaCore Function License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for
|
||||
// the sole purpose of programming logic devices manufactured by Intel
|
||||
// and sold by Intel or its authorized distributors. Please refer to the
|
||||
// applicable agreement for further details.
|
||||
// ---------------------------------------------------------------------------
|
||||
|
||||
// SystemVerilog created from acl_ftou
|
||||
// SystemVerilog created on Sun Dec 27 09:48:58 2020
|
||||
|
||||
|
||||
(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *)
|
||||
module acl_ftou (
|
||||
input wire [31:0] a,
|
||||
input wire [0:0] en,
|
||||
output wire [31:0] q,
|
||||
input wire clk,
|
||||
input wire areset
|
||||
);
|
||||
|
||||
wire [0:0] GND_q;
|
||||
wire [0:0] VCC_q;
|
||||
wire [7:0] cstAllOWE_uid6_fpToFxPTest_q;
|
||||
wire [22:0] cstZeroWF_uid7_fpToFxPTest_q;
|
||||
wire [7:0] cstAllZWE_uid8_fpToFxPTest_q;
|
||||
wire [7:0] exp_x_uid9_fpToFxPTest_b;
|
||||
wire [22:0] frac_x_uid10_fpToFxPTest_b;
|
||||
wire [0:0] excZ_x_uid11_fpToFxPTest_qi;
|
||||
reg [0:0] excZ_x_uid11_fpToFxPTest_q;
|
||||
wire [0:0] expXIsMax_uid12_fpToFxPTest_qi;
|
||||
reg [0:0] expXIsMax_uid12_fpToFxPTest_q;
|
||||
wire [0:0] fracXIsZero_uid13_fpToFxPTest_q;
|
||||
wire [0:0] fracXIsNotZero_uid14_fpToFxPTest_q;
|
||||
wire [0:0] excI_x_uid15_fpToFxPTest_qi;
|
||||
reg [0:0] excI_x_uid15_fpToFxPTest_q;
|
||||
wire [0:0] excN_x_uid16_fpToFxPTest_q;
|
||||
wire [0:0] fracPostZ_uid23_fpToFxPTest_s;
|
||||
reg [22:0] fracPostZ_uid23_fpToFxPTest_q;
|
||||
wire [0:0] invExcXZ_uid24_fpToFxPTest_q;
|
||||
wire [23:0] oFracX_uid25_fpToFxPTest_q;
|
||||
wire [0:0] signX_uid27_fpToFxPTest_b;
|
||||
wire [0:0] notNan_uid28_fpToFxPTest_q;
|
||||
wire [0:0] signX_uid29_fpToFxPTest_qi;
|
||||
reg [0:0] signX_uid29_fpToFxPTest_q;
|
||||
wire [8:0] ovfExpVal_uid30_fpToFxPTest_q;
|
||||
wire [10:0] ovf_uid31_fpToFxPTest_a;
|
||||
wire [10:0] ovf_uid31_fpToFxPTest_b;
|
||||
logic [10:0] ovf_uid31_fpToFxPTest_o;
|
||||
wire [0:0] ovf_uid31_fpToFxPTest_n;
|
||||
wire [0:0] negOrOvf_uid32_fpToFxPTest_q;
|
||||
wire [7:0] udfExpVal_uid33_fpToFxPTest_q;
|
||||
wire [10:0] udf_uid34_fpToFxPTest_a;
|
||||
wire [10:0] udf_uid34_fpToFxPTest_b;
|
||||
logic [10:0] udf_uid34_fpToFxPTest_o;
|
||||
wire [0:0] udf_uid34_fpToFxPTest_n;
|
||||
wire [8:0] ovfExpVal_uid35_fpToFxPTest_q;
|
||||
wire [10:0] shiftValE_uid36_fpToFxPTest_a;
|
||||
wire [10:0] shiftValE_uid36_fpToFxPTest_b;
|
||||
logic [10:0] shiftValE_uid36_fpToFxPTest_o;
|
||||
wire [9:0] shiftValE_uid36_fpToFxPTest_q;
|
||||
wire [5:0] shiftValRaw_uid37_fpToFxPTest_in;
|
||||
wire [5:0] shiftValRaw_uid37_fpToFxPTest_b;
|
||||
wire [5:0] maxShiftCst_uid38_fpToFxPTest_q;
|
||||
wire [11:0] shiftOutOfRange_uid39_fpToFxPTest_a;
|
||||
wire [11:0] shiftOutOfRange_uid39_fpToFxPTest_b;
|
||||
logic [11:0] shiftOutOfRange_uid39_fpToFxPTest_o;
|
||||
wire [0:0] shiftOutOfRange_uid39_fpToFxPTest_n;
|
||||
wire [0:0] shiftVal_uid40_fpToFxPTest_s;
|
||||
reg [5:0] shiftVal_uid40_fpToFxPTest_q;
|
||||
wire [8:0] zPadd_uid41_fpToFxPTest_q;
|
||||
wire [32:0] shifterIn_uid42_fpToFxPTest_q;
|
||||
wire [31:0] maxPosValueU_uid44_fpToFxPTest_q;
|
||||
wire [31:0] maxNegValueU_uid45_fpToFxPTest_q;
|
||||
wire [33:0] zRightShiferNoStickyOut_uid47_fpToFxPTest_q;
|
||||
wire [34:0] sPostRndFull_uid48_fpToFxPTest_a;
|
||||
wire [34:0] sPostRndFull_uid48_fpToFxPTest_b;
|
||||
logic [34:0] sPostRndFull_uid48_fpToFxPTest_o;
|
||||
wire [34:0] sPostRndFull_uid48_fpToFxPTest_q;
|
||||
wire [32:0] sPostRnd_uid49_fpToFxPTest_in;
|
||||
wire [31:0] sPostRnd_uid49_fpToFxPTest_b;
|
||||
wire [33:0] sPostRndFullMSBU_uid50_fpToFxPTest_in;
|
||||
wire [0:0] sPostRndFullMSBU_uid50_fpToFxPTest_b;
|
||||
wire [0:0] ovfPostRnd_uid51_fpToFxPTest_q;
|
||||
wire [2:0] muxSelConc_uid52_fpToFxPTest_q;
|
||||
reg [1:0] muxSel_uid53_fpToFxPTest_q;
|
||||
wire [1:0] finalOut_uid55_fpToFxPTest_s;
|
||||
reg [31:0] finalOut_uid55_fpToFxPTest_q;
|
||||
wire [31:0] rightShiftStage0Idx1Rng1_uid59_rightShiferNoStickyOut_uid43_fpToFxPTest_b;
|
||||
wire [32:0] rightShiftStage0Idx1_uid61_rightShiferNoStickyOut_uid43_fpToFxPTest_q;
|
||||
wire [30:0] rightShiftStage0Idx2Rng2_uid62_rightShiferNoStickyOut_uid43_fpToFxPTest_b;
|
||||
wire [1:0] rightShiftStage0Idx2Pad2_uid63_rightShiferNoStickyOut_uid43_fpToFxPTest_q;
|
||||
wire [32:0] rightShiftStage0Idx2_uid64_rightShiferNoStickyOut_uid43_fpToFxPTest_q;
|
||||
wire [29:0] rightShiftStage0Idx3Rng3_uid65_rightShiferNoStickyOut_uid43_fpToFxPTest_b;
|
||||
wire [2:0] rightShiftStage0Idx3Pad3_uid66_rightShiferNoStickyOut_uid43_fpToFxPTest_q;
|
||||
wire [32:0] rightShiftStage0Idx3_uid67_rightShiferNoStickyOut_uid43_fpToFxPTest_q;
|
||||
wire [1:0] rightShiftStage0_uid69_rightShiferNoStickyOut_uid43_fpToFxPTest_s;
|
||||
reg [32:0] rightShiftStage0_uid69_rightShiferNoStickyOut_uid43_fpToFxPTest_q;
|
||||
wire [28:0] rightShiftStage1Idx1Rng4_uid70_rightShiferNoStickyOut_uid43_fpToFxPTest_b;
|
||||
wire [3:0] rightShiftStage1Idx1Pad4_uid71_rightShiferNoStickyOut_uid43_fpToFxPTest_q;
|
||||
wire [32:0] rightShiftStage1Idx1_uid72_rightShiferNoStickyOut_uid43_fpToFxPTest_q;
|
||||
wire [24:0] rightShiftStage1Idx2Rng8_uid73_rightShiferNoStickyOut_uid43_fpToFxPTest_b;
|
||||
wire [32:0] rightShiftStage1Idx2_uid75_rightShiferNoStickyOut_uid43_fpToFxPTest_q;
|
||||
wire [20:0] rightShiftStage1Idx3Rng12_uid76_rightShiferNoStickyOut_uid43_fpToFxPTest_b;
|
||||
wire [11:0] rightShiftStage1Idx3Pad12_uid77_rightShiferNoStickyOut_uid43_fpToFxPTest_q;
|
||||
wire [32:0] rightShiftStage1Idx3_uid78_rightShiferNoStickyOut_uid43_fpToFxPTest_q;
|
||||
wire [1:0] rightShiftStage1_uid80_rightShiferNoStickyOut_uid43_fpToFxPTest_s;
|
||||
reg [32:0] rightShiftStage1_uid80_rightShiferNoStickyOut_uid43_fpToFxPTest_q;
|
||||
wire [16:0] rightShiftStage2Idx1Rng16_uid81_rightShiferNoStickyOut_uid43_fpToFxPTest_b;
|
||||
wire [15:0] rightShiftStage2Idx1Pad16_uid82_rightShiferNoStickyOut_uid43_fpToFxPTest_q;
|
||||
wire [32:0] rightShiftStage2Idx1_uid83_rightShiferNoStickyOut_uid43_fpToFxPTest_q;
|
||||
wire [0:0] rightShiftStage2Idx2Rng32_uid84_rightShiferNoStickyOut_uid43_fpToFxPTest_b;
|
||||
wire [32:0] rightShiftStage2Idx2_uid86_rightShiferNoStickyOut_uid43_fpToFxPTest_q;
|
||||
wire [32:0] rightShiftStage2Idx3_uid87_rightShiferNoStickyOut_uid43_fpToFxPTest_q;
|
||||
wire [1:0] rightShiftStage2_uid89_rightShiferNoStickyOut_uid43_fpToFxPTest_s;
|
||||
reg [32:0] rightShiftStage2_uid89_rightShiferNoStickyOut_uid43_fpToFxPTest_q;
|
||||
wire [1:0] rightShiftStageSel0Dto0_uid68_rightShiferNoStickyOut_uid43_fpToFxPTest_merged_bit_select_b;
|
||||
wire [1:0] rightShiftStageSel0Dto0_uid68_rightShiferNoStickyOut_uid43_fpToFxPTest_merged_bit_select_c;
|
||||
wire [1:0] rightShiftStageSel0Dto0_uid68_rightShiferNoStickyOut_uid43_fpToFxPTest_merged_bit_select_d;
|
||||
reg [31:0] redist0_sPostRnd_uid49_fpToFxPTest_b_1_q;
|
||||
reg [0:0] redist1_udf_uid34_fpToFxPTest_n_2_q;
|
||||
reg [0:0] redist2_ovf_uid31_fpToFxPTest_n_2_q;
|
||||
reg [0:0] redist3_signX_uid27_fpToFxPTest_b_1_q;
|
||||
reg [0:0] redist4_excN_x_uid16_fpToFxPTest_q_1_q;
|
||||
reg [22:0] redist5_frac_x_uid10_fpToFxPTest_b_1_q;
|
||||
|
||||
|
||||
// maxNegValueU_uid45_fpToFxPTest(CONSTANT,44)
|
||||
assign maxNegValueU_uid45_fpToFxPTest_q = 32'b00000000000000000000000000000000;
|
||||
|
||||
// maxPosValueU_uid44_fpToFxPTest(CONSTANT,43)
|
||||
assign maxPosValueU_uid44_fpToFxPTest_q = 32'b11111111111111111111111111111111;
|
||||
|
||||
// VCC(CONSTANT,1)
|
||||
assign VCC_q = 1'b1;
|
||||
|
||||
// GND(CONSTANT,0)
|
||||
assign GND_q = 1'b0;
|
||||
|
||||
// rightShiftStage2Idx3_uid87_rightShiferNoStickyOut_uid43_fpToFxPTest(CONSTANT,86)
|
||||
assign rightShiftStage2Idx3_uid87_rightShiferNoStickyOut_uid43_fpToFxPTest_q = 33'b000000000000000000000000000000000;
|
||||
|
||||
// rightShiftStage2Idx2Rng32_uid84_rightShiferNoStickyOut_uid43_fpToFxPTest(BITSELECT,83)@1
|
||||
assign rightShiftStage2Idx2Rng32_uid84_rightShiferNoStickyOut_uid43_fpToFxPTest_b = rightShiftStage1_uid80_rightShiferNoStickyOut_uid43_fpToFxPTest_q[32:32];
|
||||
|
||||
// rightShiftStage2Idx2_uid86_rightShiferNoStickyOut_uid43_fpToFxPTest(BITJOIN,85)@1
|
||||
assign rightShiftStage2Idx2_uid86_rightShiferNoStickyOut_uid43_fpToFxPTest_q = {maxNegValueU_uid45_fpToFxPTest_q, rightShiftStage2Idx2Rng32_uid84_rightShiferNoStickyOut_uid43_fpToFxPTest_b};
|
||||
|
||||
// rightShiftStage2Idx1Pad16_uid82_rightShiferNoStickyOut_uid43_fpToFxPTest(CONSTANT,81)
|
||||
assign rightShiftStage2Idx1Pad16_uid82_rightShiferNoStickyOut_uid43_fpToFxPTest_q = 16'b0000000000000000;
|
||||
|
||||
// rightShiftStage2Idx1Rng16_uid81_rightShiferNoStickyOut_uid43_fpToFxPTest(BITSELECT,80)@1
|
||||
assign rightShiftStage2Idx1Rng16_uid81_rightShiferNoStickyOut_uid43_fpToFxPTest_b = rightShiftStage1_uid80_rightShiferNoStickyOut_uid43_fpToFxPTest_q[32:16];
|
||||
|
||||
// rightShiftStage2Idx1_uid83_rightShiferNoStickyOut_uid43_fpToFxPTest(BITJOIN,82)@1
|
||||
assign rightShiftStage2Idx1_uid83_rightShiferNoStickyOut_uid43_fpToFxPTest_q = {rightShiftStage2Idx1Pad16_uid82_rightShiferNoStickyOut_uid43_fpToFxPTest_q, rightShiftStage2Idx1Rng16_uid81_rightShiferNoStickyOut_uid43_fpToFxPTest_b};
|
||||
|
||||
// rightShiftStage1Idx3Pad12_uid77_rightShiferNoStickyOut_uid43_fpToFxPTest(CONSTANT,76)
|
||||
assign rightShiftStage1Idx3Pad12_uid77_rightShiferNoStickyOut_uid43_fpToFxPTest_q = 12'b000000000000;
|
||||
|
||||
// rightShiftStage1Idx3Rng12_uid76_rightShiferNoStickyOut_uid43_fpToFxPTest(BITSELECT,75)@1
|
||||
assign rightShiftStage1Idx3Rng12_uid76_rightShiferNoStickyOut_uid43_fpToFxPTest_b = rightShiftStage0_uid69_rightShiferNoStickyOut_uid43_fpToFxPTest_q[32:12];
|
||||
|
||||
// rightShiftStage1Idx3_uid78_rightShiferNoStickyOut_uid43_fpToFxPTest(BITJOIN,77)@1
|
||||
assign rightShiftStage1Idx3_uid78_rightShiferNoStickyOut_uid43_fpToFxPTest_q = {rightShiftStage1Idx3Pad12_uid77_rightShiferNoStickyOut_uid43_fpToFxPTest_q, rightShiftStage1Idx3Rng12_uid76_rightShiferNoStickyOut_uid43_fpToFxPTest_b};
|
||||
|
||||
// cstAllZWE_uid8_fpToFxPTest(CONSTANT,7)
|
||||
assign cstAllZWE_uid8_fpToFxPTest_q = 8'b00000000;
|
||||
|
||||
// rightShiftStage1Idx2Rng8_uid73_rightShiferNoStickyOut_uid43_fpToFxPTest(BITSELECT,72)@1
|
||||
assign rightShiftStage1Idx2Rng8_uid73_rightShiferNoStickyOut_uid43_fpToFxPTest_b = rightShiftStage0_uid69_rightShiferNoStickyOut_uid43_fpToFxPTest_q[32:8];
|
||||
|
||||
// rightShiftStage1Idx2_uid75_rightShiferNoStickyOut_uid43_fpToFxPTest(BITJOIN,74)@1
|
||||
assign rightShiftStage1Idx2_uid75_rightShiferNoStickyOut_uid43_fpToFxPTest_q = {cstAllZWE_uid8_fpToFxPTest_q, rightShiftStage1Idx2Rng8_uid73_rightShiferNoStickyOut_uid43_fpToFxPTest_b};
|
||||
|
||||
// rightShiftStage1Idx1Pad4_uid71_rightShiferNoStickyOut_uid43_fpToFxPTest(CONSTANT,70)
|
||||
assign rightShiftStage1Idx1Pad4_uid71_rightShiferNoStickyOut_uid43_fpToFxPTest_q = 4'b0000;
|
||||
|
||||
// rightShiftStage1Idx1Rng4_uid70_rightShiferNoStickyOut_uid43_fpToFxPTest(BITSELECT,69)@1
|
||||
assign rightShiftStage1Idx1Rng4_uid70_rightShiferNoStickyOut_uid43_fpToFxPTest_b = rightShiftStage0_uid69_rightShiferNoStickyOut_uid43_fpToFxPTest_q[32:4];
|
||||
|
||||
// rightShiftStage1Idx1_uid72_rightShiferNoStickyOut_uid43_fpToFxPTest(BITJOIN,71)@1
|
||||
assign rightShiftStage1Idx1_uid72_rightShiferNoStickyOut_uid43_fpToFxPTest_q = {rightShiftStage1Idx1Pad4_uid71_rightShiferNoStickyOut_uid43_fpToFxPTest_q, rightShiftStage1Idx1Rng4_uid70_rightShiferNoStickyOut_uid43_fpToFxPTest_b};
|
||||
|
||||
// rightShiftStage0Idx3Pad3_uid66_rightShiferNoStickyOut_uid43_fpToFxPTest(CONSTANT,65)
|
||||
assign rightShiftStage0Idx3Pad3_uid66_rightShiferNoStickyOut_uid43_fpToFxPTest_q = 3'b000;
|
||||
|
||||
// rightShiftStage0Idx3Rng3_uid65_rightShiferNoStickyOut_uid43_fpToFxPTest(BITSELECT,64)@1
|
||||
assign rightShiftStage0Idx3Rng3_uid65_rightShiferNoStickyOut_uid43_fpToFxPTest_b = shifterIn_uid42_fpToFxPTest_q[32:3];
|
||||
|
||||
// rightShiftStage0Idx3_uid67_rightShiferNoStickyOut_uid43_fpToFxPTest(BITJOIN,66)@1
|
||||
assign rightShiftStage0Idx3_uid67_rightShiferNoStickyOut_uid43_fpToFxPTest_q = {rightShiftStage0Idx3Pad3_uid66_rightShiferNoStickyOut_uid43_fpToFxPTest_q, rightShiftStage0Idx3Rng3_uid65_rightShiferNoStickyOut_uid43_fpToFxPTest_b};
|
||||
|
||||
// rightShiftStage0Idx2Pad2_uid63_rightShiferNoStickyOut_uid43_fpToFxPTest(CONSTANT,62)
|
||||
assign rightShiftStage0Idx2Pad2_uid63_rightShiferNoStickyOut_uid43_fpToFxPTest_q = 2'b00;
|
||||
|
||||
// rightShiftStage0Idx2Rng2_uid62_rightShiferNoStickyOut_uid43_fpToFxPTest(BITSELECT,61)@1
|
||||
assign rightShiftStage0Idx2Rng2_uid62_rightShiferNoStickyOut_uid43_fpToFxPTest_b = shifterIn_uid42_fpToFxPTest_q[32:2];
|
||||
|
||||
// rightShiftStage0Idx2_uid64_rightShiferNoStickyOut_uid43_fpToFxPTest(BITJOIN,63)@1
|
||||
assign rightShiftStage0Idx2_uid64_rightShiferNoStickyOut_uid43_fpToFxPTest_q = {rightShiftStage0Idx2Pad2_uid63_rightShiferNoStickyOut_uid43_fpToFxPTest_q, rightShiftStage0Idx2Rng2_uid62_rightShiferNoStickyOut_uid43_fpToFxPTest_b};
|
||||
|
||||
// rightShiftStage0Idx1Rng1_uid59_rightShiferNoStickyOut_uid43_fpToFxPTest(BITSELECT,58)@1
|
||||
assign rightShiftStage0Idx1Rng1_uid59_rightShiferNoStickyOut_uid43_fpToFxPTest_b = shifterIn_uid42_fpToFxPTest_q[32:1];
|
||||
|
||||
// rightShiftStage0Idx1_uid61_rightShiferNoStickyOut_uid43_fpToFxPTest(BITJOIN,60)@1
|
||||
assign rightShiftStage0Idx1_uid61_rightShiferNoStickyOut_uid43_fpToFxPTest_q = {GND_q, rightShiftStage0Idx1Rng1_uid59_rightShiferNoStickyOut_uid43_fpToFxPTest_b};
|
||||
|
||||
// exp_x_uid9_fpToFxPTest(BITSELECT,8)@0
|
||||
assign exp_x_uid9_fpToFxPTest_b = a[30:23];
|
||||
|
||||
// excZ_x_uid11_fpToFxPTest(LOGICAL,10)@0 + 1
|
||||
assign excZ_x_uid11_fpToFxPTest_qi = exp_x_uid9_fpToFxPTest_b == cstAllZWE_uid8_fpToFxPTest_q ? 1'b1 : 1'b0;
|
||||
dspba_delay_ver #( .width(1), .depth(1), .reset_kind("SYNC"), .phase(0), .modulus(1) )
|
||||
excZ_x_uid11_fpToFxPTest_delay ( .xin(excZ_x_uid11_fpToFxPTest_qi), .xout(excZ_x_uid11_fpToFxPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// invExcXZ_uid24_fpToFxPTest(LOGICAL,23)@1
|
||||
assign invExcXZ_uid24_fpToFxPTest_q = ~ (excZ_x_uid11_fpToFxPTest_q);
|
||||
|
||||
// cstZeroWF_uid7_fpToFxPTest(CONSTANT,6)
|
||||
assign cstZeroWF_uid7_fpToFxPTest_q = 23'b00000000000000000000000;
|
||||
|
||||
// frac_x_uid10_fpToFxPTest(BITSELECT,9)@0
|
||||
assign frac_x_uid10_fpToFxPTest_b = a[22:0];
|
||||
|
||||
// redist5_frac_x_uid10_fpToFxPTest_b_1(DELAY,96)
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
redist5_frac_x_uid10_fpToFxPTest_b_1_q <= '0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
redist5_frac_x_uid10_fpToFxPTest_b_1_q <= frac_x_uid10_fpToFxPTest_b;
|
||||
end
|
||||
end
|
||||
|
||||
// fracPostZ_uid23_fpToFxPTest(MUX,22)@1
|
||||
assign fracPostZ_uid23_fpToFxPTest_s = excZ_x_uid11_fpToFxPTest_q;
|
||||
always @(fracPostZ_uid23_fpToFxPTest_s or en or redist5_frac_x_uid10_fpToFxPTest_b_1_q or cstZeroWF_uid7_fpToFxPTest_q)
|
||||
begin
|
||||
unique case (fracPostZ_uid23_fpToFxPTest_s)
|
||||
1'b0 : fracPostZ_uid23_fpToFxPTest_q = redist5_frac_x_uid10_fpToFxPTest_b_1_q;
|
||||
1'b1 : fracPostZ_uid23_fpToFxPTest_q = cstZeroWF_uid7_fpToFxPTest_q;
|
||||
default : fracPostZ_uid23_fpToFxPTest_q = 23'b0;
|
||||
endcase
|
||||
end
|
||||
|
||||
// oFracX_uid25_fpToFxPTest(BITJOIN,24)@1
|
||||
assign oFracX_uid25_fpToFxPTest_q = {invExcXZ_uid24_fpToFxPTest_q, fracPostZ_uid23_fpToFxPTest_q};
|
||||
|
||||
// zPadd_uid41_fpToFxPTest(CONSTANT,40)
|
||||
assign zPadd_uid41_fpToFxPTest_q = 9'b000000000;
|
||||
|
||||
// shifterIn_uid42_fpToFxPTest(BITJOIN,41)@1
|
||||
assign shifterIn_uid42_fpToFxPTest_q = {oFracX_uid25_fpToFxPTest_q, zPadd_uid41_fpToFxPTest_q};
|
||||
|
||||
// rightShiftStage0_uid69_rightShiferNoStickyOut_uid43_fpToFxPTest(MUX,68)@1
|
||||
assign rightShiftStage0_uid69_rightShiferNoStickyOut_uid43_fpToFxPTest_s = rightShiftStageSel0Dto0_uid68_rightShiferNoStickyOut_uid43_fpToFxPTest_merged_bit_select_b;
|
||||
always @(rightShiftStage0_uid69_rightShiferNoStickyOut_uid43_fpToFxPTest_s or en or shifterIn_uid42_fpToFxPTest_q or rightShiftStage0Idx1_uid61_rightShiferNoStickyOut_uid43_fpToFxPTest_q or rightShiftStage0Idx2_uid64_rightShiferNoStickyOut_uid43_fpToFxPTest_q or rightShiftStage0Idx3_uid67_rightShiferNoStickyOut_uid43_fpToFxPTest_q)
|
||||
begin
|
||||
unique case (rightShiftStage0_uid69_rightShiferNoStickyOut_uid43_fpToFxPTest_s)
|
||||
2'b00 : rightShiftStage0_uid69_rightShiferNoStickyOut_uid43_fpToFxPTest_q = shifterIn_uid42_fpToFxPTest_q;
|
||||
2'b01 : rightShiftStage0_uid69_rightShiferNoStickyOut_uid43_fpToFxPTest_q = rightShiftStage0Idx1_uid61_rightShiferNoStickyOut_uid43_fpToFxPTest_q;
|
||||
2'b10 : rightShiftStage0_uid69_rightShiferNoStickyOut_uid43_fpToFxPTest_q = rightShiftStage0Idx2_uid64_rightShiferNoStickyOut_uid43_fpToFxPTest_q;
|
||||
2'b11 : rightShiftStage0_uid69_rightShiferNoStickyOut_uid43_fpToFxPTest_q = rightShiftStage0Idx3_uid67_rightShiferNoStickyOut_uid43_fpToFxPTest_q;
|
||||
default : rightShiftStage0_uid69_rightShiferNoStickyOut_uid43_fpToFxPTest_q = 33'b0;
|
||||
endcase
|
||||
end
|
||||
|
||||
// rightShiftStage1_uid80_rightShiferNoStickyOut_uid43_fpToFxPTest(MUX,79)@1
|
||||
assign rightShiftStage1_uid80_rightShiferNoStickyOut_uid43_fpToFxPTest_s = rightShiftStageSel0Dto0_uid68_rightShiferNoStickyOut_uid43_fpToFxPTest_merged_bit_select_c;
|
||||
always @(rightShiftStage1_uid80_rightShiferNoStickyOut_uid43_fpToFxPTest_s or en or rightShiftStage0_uid69_rightShiferNoStickyOut_uid43_fpToFxPTest_q or rightShiftStage1Idx1_uid72_rightShiferNoStickyOut_uid43_fpToFxPTest_q or rightShiftStage1Idx2_uid75_rightShiferNoStickyOut_uid43_fpToFxPTest_q or rightShiftStage1Idx3_uid78_rightShiferNoStickyOut_uid43_fpToFxPTest_q)
|
||||
begin
|
||||
unique case (rightShiftStage1_uid80_rightShiferNoStickyOut_uid43_fpToFxPTest_s)
|
||||
2'b00 : rightShiftStage1_uid80_rightShiferNoStickyOut_uid43_fpToFxPTest_q = rightShiftStage0_uid69_rightShiferNoStickyOut_uid43_fpToFxPTest_q;
|
||||
2'b01 : rightShiftStage1_uid80_rightShiferNoStickyOut_uid43_fpToFxPTest_q = rightShiftStage1Idx1_uid72_rightShiferNoStickyOut_uid43_fpToFxPTest_q;
|
||||
2'b10 : rightShiftStage1_uid80_rightShiferNoStickyOut_uid43_fpToFxPTest_q = rightShiftStage1Idx2_uid75_rightShiferNoStickyOut_uid43_fpToFxPTest_q;
|
||||
2'b11 : rightShiftStage1_uid80_rightShiferNoStickyOut_uid43_fpToFxPTest_q = rightShiftStage1Idx3_uid78_rightShiferNoStickyOut_uid43_fpToFxPTest_q;
|
||||
default : rightShiftStage1_uid80_rightShiferNoStickyOut_uid43_fpToFxPTest_q = 33'b0;
|
||||
endcase
|
||||
end
|
||||
|
||||
// maxShiftCst_uid38_fpToFxPTest(CONSTANT,37)
|
||||
assign maxShiftCst_uid38_fpToFxPTest_q = 6'b100001;
|
||||
|
||||
// ovfExpVal_uid35_fpToFxPTest(CONSTANT,34)
|
||||
assign ovfExpVal_uid35_fpToFxPTest_q = 9'b010011110;
|
||||
|
||||
// shiftValE_uid36_fpToFxPTest(SUB,35)@0
|
||||
assign shiftValE_uid36_fpToFxPTest_a = {{2{ovfExpVal_uid35_fpToFxPTest_q[8]}}, ovfExpVal_uid35_fpToFxPTest_q};
|
||||
assign shiftValE_uid36_fpToFxPTest_b = {3'b000, exp_x_uid9_fpToFxPTest_b};
|
||||
assign shiftValE_uid36_fpToFxPTest_o = $signed(shiftValE_uid36_fpToFxPTest_a) - $signed(shiftValE_uid36_fpToFxPTest_b);
|
||||
assign shiftValE_uid36_fpToFxPTest_q = shiftValE_uid36_fpToFxPTest_o[9:0];
|
||||
|
||||
// shiftValRaw_uid37_fpToFxPTest(BITSELECT,36)@0
|
||||
assign shiftValRaw_uid37_fpToFxPTest_in = shiftValE_uid36_fpToFxPTest_q[5:0];
|
||||
assign shiftValRaw_uid37_fpToFxPTest_b = shiftValRaw_uid37_fpToFxPTest_in[5:0];
|
||||
|
||||
// shiftOutOfRange_uid39_fpToFxPTest(COMPARE,38)@0
|
||||
assign shiftOutOfRange_uid39_fpToFxPTest_a = {{2{shiftValE_uid36_fpToFxPTest_q[9]}}, shiftValE_uid36_fpToFxPTest_q};
|
||||
assign shiftOutOfRange_uid39_fpToFxPTest_b = {6'b000000, maxShiftCst_uid38_fpToFxPTest_q};
|
||||
assign shiftOutOfRange_uid39_fpToFxPTest_o = $signed(shiftOutOfRange_uid39_fpToFxPTest_a) - $signed(shiftOutOfRange_uid39_fpToFxPTest_b);
|
||||
assign shiftOutOfRange_uid39_fpToFxPTest_n[0] = ~ (shiftOutOfRange_uid39_fpToFxPTest_o[11]);
|
||||
|
||||
// shiftVal_uid40_fpToFxPTest(MUX,39)@0 + 1
|
||||
assign shiftVal_uid40_fpToFxPTest_s = shiftOutOfRange_uid39_fpToFxPTest_n;
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
shiftVal_uid40_fpToFxPTest_q <= 6'b0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
unique case (shiftVal_uid40_fpToFxPTest_s)
|
||||
1'b0 : shiftVal_uid40_fpToFxPTest_q <= shiftValRaw_uid37_fpToFxPTest_b;
|
||||
1'b1 : shiftVal_uid40_fpToFxPTest_q <= maxShiftCst_uid38_fpToFxPTest_q;
|
||||
default : shiftVal_uid40_fpToFxPTest_q <= 6'b0;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
// rightShiftStageSel0Dto0_uid68_rightShiferNoStickyOut_uid43_fpToFxPTest_merged_bit_select(BITSELECT,90)@1
|
||||
assign rightShiftStageSel0Dto0_uid68_rightShiferNoStickyOut_uid43_fpToFxPTest_merged_bit_select_b = shiftVal_uid40_fpToFxPTest_q[1:0];
|
||||
assign rightShiftStageSel0Dto0_uid68_rightShiferNoStickyOut_uid43_fpToFxPTest_merged_bit_select_c = shiftVal_uid40_fpToFxPTest_q[3:2];
|
||||
assign rightShiftStageSel0Dto0_uid68_rightShiferNoStickyOut_uid43_fpToFxPTest_merged_bit_select_d = shiftVal_uid40_fpToFxPTest_q[5:4];
|
||||
|
||||
// rightShiftStage2_uid89_rightShiferNoStickyOut_uid43_fpToFxPTest(MUX,88)@1 + 1
|
||||
assign rightShiftStage2_uid89_rightShiferNoStickyOut_uid43_fpToFxPTest_s = rightShiftStageSel0Dto0_uid68_rightShiferNoStickyOut_uid43_fpToFxPTest_merged_bit_select_d;
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
rightShiftStage2_uid89_rightShiferNoStickyOut_uid43_fpToFxPTest_q <= 33'b0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
unique case (rightShiftStage2_uid89_rightShiferNoStickyOut_uid43_fpToFxPTest_s)
|
||||
2'b00 : rightShiftStage2_uid89_rightShiferNoStickyOut_uid43_fpToFxPTest_q <= rightShiftStage1_uid80_rightShiferNoStickyOut_uid43_fpToFxPTest_q;
|
||||
2'b01 : rightShiftStage2_uid89_rightShiferNoStickyOut_uid43_fpToFxPTest_q <= rightShiftStage2Idx1_uid83_rightShiferNoStickyOut_uid43_fpToFxPTest_q;
|
||||
2'b10 : rightShiftStage2_uid89_rightShiferNoStickyOut_uid43_fpToFxPTest_q <= rightShiftStage2Idx2_uid86_rightShiferNoStickyOut_uid43_fpToFxPTest_q;
|
||||
2'b11 : rightShiftStage2_uid89_rightShiferNoStickyOut_uid43_fpToFxPTest_q <= rightShiftStage2Idx3_uid87_rightShiferNoStickyOut_uid43_fpToFxPTest_q;
|
||||
default : rightShiftStage2_uid89_rightShiferNoStickyOut_uid43_fpToFxPTest_q <= 33'b0;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
// zRightShiferNoStickyOut_uid47_fpToFxPTest(BITJOIN,46)@2
|
||||
assign zRightShiferNoStickyOut_uid47_fpToFxPTest_q = {GND_q, rightShiftStage2_uid89_rightShiferNoStickyOut_uid43_fpToFxPTest_q};
|
||||
|
||||
// sPostRndFull_uid48_fpToFxPTest(ADD,47)@2
|
||||
assign sPostRndFull_uid48_fpToFxPTest_a = {1'b0, zRightShiferNoStickyOut_uid47_fpToFxPTest_q};
|
||||
assign sPostRndFull_uid48_fpToFxPTest_b = {34'b0000000000000000000000000000000000, VCC_q};
|
||||
assign sPostRndFull_uid48_fpToFxPTest_o = $unsigned(sPostRndFull_uid48_fpToFxPTest_a) + $unsigned(sPostRndFull_uid48_fpToFxPTest_b);
|
||||
assign sPostRndFull_uid48_fpToFxPTest_q = sPostRndFull_uid48_fpToFxPTest_o[34:0];
|
||||
|
||||
// sPostRnd_uid49_fpToFxPTest(BITSELECT,48)@2
|
||||
assign sPostRnd_uid49_fpToFxPTest_in = sPostRndFull_uid48_fpToFxPTest_q[32:0];
|
||||
assign sPostRnd_uid49_fpToFxPTest_b = sPostRnd_uid49_fpToFxPTest_in[32:1];
|
||||
|
||||
// redist0_sPostRnd_uid49_fpToFxPTest_b_1(DELAY,91)
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
redist0_sPostRnd_uid49_fpToFxPTest_b_1_q <= '0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
redist0_sPostRnd_uid49_fpToFxPTest_b_1_q <= sPostRnd_uid49_fpToFxPTest_b;
|
||||
end
|
||||
end
|
||||
|
||||
// signX_uid27_fpToFxPTest(BITSELECT,26)@0
|
||||
assign signX_uid27_fpToFxPTest_b = a[31:31];
|
||||
|
||||
// redist3_signX_uid27_fpToFxPTest_b_1(DELAY,94)
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
redist3_signX_uid27_fpToFxPTest_b_1_q <= '0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
redist3_signX_uid27_fpToFxPTest_b_1_q <= signX_uid27_fpToFxPTest_b;
|
||||
end
|
||||
end
|
||||
|
||||
// fracXIsZero_uid13_fpToFxPTest(LOGICAL,12)@1
|
||||
assign fracXIsZero_uid13_fpToFxPTest_q = cstZeroWF_uid7_fpToFxPTest_q == redist5_frac_x_uid10_fpToFxPTest_b_1_q ? 1'b1 : 1'b0;
|
||||
|
||||
// fracXIsNotZero_uid14_fpToFxPTest(LOGICAL,13)@1
|
||||
assign fracXIsNotZero_uid14_fpToFxPTest_q = ~ (fracXIsZero_uid13_fpToFxPTest_q);
|
||||
|
||||
// cstAllOWE_uid6_fpToFxPTest(CONSTANT,5)
|
||||
assign cstAllOWE_uid6_fpToFxPTest_q = 8'b11111111;
|
||||
|
||||
// expXIsMax_uid12_fpToFxPTest(LOGICAL,11)@0 + 1
|
||||
assign expXIsMax_uid12_fpToFxPTest_qi = exp_x_uid9_fpToFxPTest_b == cstAllOWE_uid6_fpToFxPTest_q ? 1'b1 : 1'b0;
|
||||
dspba_delay_ver #( .width(1), .depth(1), .reset_kind("SYNC"), .phase(0), .modulus(1) )
|
||||
expXIsMax_uid12_fpToFxPTest_delay ( .xin(expXIsMax_uid12_fpToFxPTest_qi), .xout(expXIsMax_uid12_fpToFxPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// excN_x_uid16_fpToFxPTest(LOGICAL,15)@1
|
||||
assign excN_x_uid16_fpToFxPTest_q = expXIsMax_uid12_fpToFxPTest_q & fracXIsNotZero_uid14_fpToFxPTest_q;
|
||||
|
||||
// notNan_uid28_fpToFxPTest(LOGICAL,27)@1
|
||||
assign notNan_uid28_fpToFxPTest_q = ~ (excN_x_uid16_fpToFxPTest_q);
|
||||
|
||||
// signX_uid29_fpToFxPTest(LOGICAL,28)@1 + 1
|
||||
assign signX_uid29_fpToFxPTest_qi = notNan_uid28_fpToFxPTest_q & redist3_signX_uid27_fpToFxPTest_b_1_q;
|
||||
dspba_delay_ver #( .width(1), .depth(1), .reset_kind("SYNC"), .phase(0), .modulus(1) )
|
||||
signX_uid29_fpToFxPTest_delay ( .xin(signX_uid29_fpToFxPTest_qi), .xout(signX_uid29_fpToFxPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// udfExpVal_uid33_fpToFxPTest(CONSTANT,32)
|
||||
assign udfExpVal_uid33_fpToFxPTest_q = 8'b01111101;
|
||||
|
||||
// udf_uid34_fpToFxPTest(COMPARE,33)@0 + 1
|
||||
assign udf_uid34_fpToFxPTest_a = {{3{udfExpVal_uid33_fpToFxPTest_q[7]}}, udfExpVal_uid33_fpToFxPTest_q};
|
||||
assign udf_uid34_fpToFxPTest_b = {3'b000, exp_x_uid9_fpToFxPTest_b};
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
udf_uid34_fpToFxPTest_o <= 11'b0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
udf_uid34_fpToFxPTest_o <= $signed(udf_uid34_fpToFxPTest_a) - $signed(udf_uid34_fpToFxPTest_b);
|
||||
end
|
||||
end
|
||||
assign udf_uid34_fpToFxPTest_n[0] = ~ (udf_uid34_fpToFxPTest_o[10]);
|
||||
|
||||
// redist1_udf_uid34_fpToFxPTest_n_2(DELAY,92)
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
redist1_udf_uid34_fpToFxPTest_n_2_q <= '0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
redist1_udf_uid34_fpToFxPTest_n_2_q <= udf_uid34_fpToFxPTest_n;
|
||||
end
|
||||
end
|
||||
|
||||
// sPostRndFullMSBU_uid50_fpToFxPTest(BITSELECT,49)@2
|
||||
assign sPostRndFullMSBU_uid50_fpToFxPTest_in = sPostRndFull_uid48_fpToFxPTest_q[33:0];
|
||||
assign sPostRndFullMSBU_uid50_fpToFxPTest_b = sPostRndFullMSBU_uid50_fpToFxPTest_in[33:33];
|
||||
|
||||
// ovfExpVal_uid30_fpToFxPTest(CONSTANT,29)
|
||||
assign ovfExpVal_uid30_fpToFxPTest_q = 9'b010011111;
|
||||
|
||||
// ovf_uid31_fpToFxPTest(COMPARE,30)@0 + 1
|
||||
assign ovf_uid31_fpToFxPTest_a = {3'b000, exp_x_uid9_fpToFxPTest_b};
|
||||
assign ovf_uid31_fpToFxPTest_b = {{2{ovfExpVal_uid30_fpToFxPTest_q[8]}}, ovfExpVal_uid30_fpToFxPTest_q};
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
ovf_uid31_fpToFxPTest_o <= 11'b0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
ovf_uid31_fpToFxPTest_o <= $signed(ovf_uid31_fpToFxPTest_a) - $signed(ovf_uid31_fpToFxPTest_b);
|
||||
end
|
||||
end
|
||||
assign ovf_uid31_fpToFxPTest_n[0] = ~ (ovf_uid31_fpToFxPTest_o[10]);
|
||||
|
||||
// redist2_ovf_uid31_fpToFxPTest_n_2(DELAY,93)
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
redist2_ovf_uid31_fpToFxPTest_n_2_q <= '0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
redist2_ovf_uid31_fpToFxPTest_n_2_q <= ovf_uid31_fpToFxPTest_n;
|
||||
end
|
||||
end
|
||||
|
||||
// negOrOvf_uid32_fpToFxPTest(LOGICAL,31)@2
|
||||
assign negOrOvf_uid32_fpToFxPTest_q = signX_uid29_fpToFxPTest_q | redist2_ovf_uid31_fpToFxPTest_n_2_q;
|
||||
|
||||
// excI_x_uid15_fpToFxPTest(LOGICAL,14)@1 + 1
|
||||
assign excI_x_uid15_fpToFxPTest_qi = expXIsMax_uid12_fpToFxPTest_q & fracXIsZero_uid13_fpToFxPTest_q;
|
||||
dspba_delay_ver #( .width(1), .depth(1), .reset_kind("SYNC"), .phase(0), .modulus(1) )
|
||||
excI_x_uid15_fpToFxPTest_delay ( .xin(excI_x_uid15_fpToFxPTest_qi), .xout(excI_x_uid15_fpToFxPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// redist4_excN_x_uid16_fpToFxPTest_q_1(DELAY,95)
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
redist4_excN_x_uid16_fpToFxPTest_q_1_q <= '0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
redist4_excN_x_uid16_fpToFxPTest_q_1_q <= excN_x_uid16_fpToFxPTest_q;
|
||||
end
|
||||
end
|
||||
|
||||
// ovfPostRnd_uid51_fpToFxPTest(LOGICAL,50)@2
|
||||
assign ovfPostRnd_uid51_fpToFxPTest_q = redist4_excN_x_uid16_fpToFxPTest_q_1_q | excI_x_uid15_fpToFxPTest_q | negOrOvf_uid32_fpToFxPTest_q | sPostRndFullMSBU_uid50_fpToFxPTest_b;
|
||||
|
||||
// muxSelConc_uid52_fpToFxPTest(BITJOIN,51)@2
|
||||
assign muxSelConc_uid52_fpToFxPTest_q = {signX_uid29_fpToFxPTest_q, redist1_udf_uid34_fpToFxPTest_n_2_q, ovfPostRnd_uid51_fpToFxPTest_q};
|
||||
|
||||
// muxSel_uid53_fpToFxPTest(LOOKUP,52)@2 + 1
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
muxSel_uid53_fpToFxPTest_q <= 2'b00;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
unique case (muxSelConc_uid52_fpToFxPTest_q)
|
||||
3'b000 : muxSel_uid53_fpToFxPTest_q <= 2'b00;
|
||||
3'b001 : muxSel_uid53_fpToFxPTest_q <= 2'b01;
|
||||
3'b010 : muxSel_uid53_fpToFxPTest_q <= 2'b11;
|
||||
3'b011 : muxSel_uid53_fpToFxPTest_q <= 2'b00;
|
||||
3'b100 : muxSel_uid53_fpToFxPTest_q <= 2'b10;
|
||||
3'b101 : muxSel_uid53_fpToFxPTest_q <= 2'b10;
|
||||
3'b110 : muxSel_uid53_fpToFxPTest_q <= 2'b10;
|
||||
3'b111 : muxSel_uid53_fpToFxPTest_q <= 2'b10;
|
||||
default : begin
|
||||
// unreachable
|
||||
muxSel_uid53_fpToFxPTest_q <= 2'bxx;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
// finalOut_uid55_fpToFxPTest(MUX,54)@3
|
||||
assign finalOut_uid55_fpToFxPTest_s = muxSel_uid53_fpToFxPTest_q;
|
||||
always @(finalOut_uid55_fpToFxPTest_s or en or redist0_sPostRnd_uid49_fpToFxPTest_b_1_q or maxPosValueU_uid44_fpToFxPTest_q or maxNegValueU_uid45_fpToFxPTest_q)
|
||||
begin
|
||||
unique case (finalOut_uid55_fpToFxPTest_s)
|
||||
2'b00 : finalOut_uid55_fpToFxPTest_q = redist0_sPostRnd_uid49_fpToFxPTest_b_1_q;
|
||||
2'b01 : finalOut_uid55_fpToFxPTest_q = maxPosValueU_uid44_fpToFxPTest_q;
|
||||
2'b10 : finalOut_uid55_fpToFxPTest_q = maxNegValueU_uid45_fpToFxPTest_q;
|
||||
2'b11 : finalOut_uid55_fpToFxPTest_q = maxNegValueU_uid45_fpToFxPTest_q;
|
||||
default : finalOut_uid55_fpToFxPTest_q = 32'b0;
|
||||
endcase
|
||||
end
|
||||
|
||||
// xOut(GPOUT,4)@3
|
||||
assign q = finalOut_uid55_fpToFxPTest_q;
|
||||
|
||||
endmodule
|
||||
296
hw/rtl/fp_cores/altera/stratix10/acl_gen.log
Normal file
296
hw/rtl/fp_cores/altera/stratix10/acl_gen.log
Normal file
|
|
@ -0,0 +1,296 @@
|
|||
starting execution ...
|
||||
build model options ...
|
||||
argc=22
|
||||
Generation context:
|
||||
Will not generate valid and channel signals
|
||||
HardFP is enabled enabling set to true
|
||||
Correct rounding constraint detected
|
||||
Will not generate valid and channel signals
|
||||
The new component name is acl_fadd
|
||||
Frequency 250MHz
|
||||
Deployment FPGA Stratix10
|
||||
Estimated resources LUTs 0, DSPs 2, RAMBits 0, RAMBlocks 0
|
||||
The pipeline depth of the block is 3 cycle(s)
|
||||
@@start
|
||||
@name FPAdd@
|
||||
@latency 3@
|
||||
@LUT 0@
|
||||
@DSP 2@
|
||||
@RAMBits 0@
|
||||
@RAMBlockUsage 0@
|
||||
@enable 1@
|
||||
@subnormals 0@
|
||||
@error 0.50@
|
||||
@rounding RNE@
|
||||
@method single path@
|
||||
@inPort 0 fpieee 8 23@
|
||||
@inPort 1 fpieee 8 23@
|
||||
@outPort 0 fpieee 8 23@
|
||||
@nochanvalid 1@
|
||||
@@end
|
||||
starting execution ...
|
||||
build model options ...
|
||||
argc=22
|
||||
Generation context:
|
||||
Will not generate valid and channel signals
|
||||
HardFP is enabled enabling set to true
|
||||
Correct rounding constraint detected
|
||||
Will not generate valid and channel signals
|
||||
The new component name is acl_fsub
|
||||
Frequency 250MHz
|
||||
Deployment FPGA Stratix10
|
||||
Estimated resources LUTs 0, DSPs 2, RAMBits 0, RAMBlocks 0
|
||||
The pipeline depth of the block is 3 cycle(s)
|
||||
@@start
|
||||
@name FPSub@
|
||||
@latency 3@
|
||||
@LUT 0@
|
||||
@DSP 2@
|
||||
@RAMBits 0@
|
||||
@RAMBlockUsage 0@
|
||||
@enable 1@
|
||||
@subnormals 0@
|
||||
@error 0.50@
|
||||
@rounding RNE@
|
||||
@method single path@
|
||||
@inPort 0 fpieee 8 23@
|
||||
@inPort 1 fpieee 8 23@
|
||||
@outPort 0 fpieee 8 23@
|
||||
@nochanvalid 1@
|
||||
@@end
|
||||
starting execution ...
|
||||
build model options ...
|
||||
argc=22
|
||||
Generation context:
|
||||
Will not generate valid and channel signals
|
||||
HardFP is enabled enabling set to true
|
||||
Correct rounding constraint detected
|
||||
Will not generate valid and channel signals
|
||||
The new component name is acl_fmul
|
||||
Frequency 250MHz
|
||||
Deployment FPGA Stratix10
|
||||
Estimated resources LUTs 0, DSPs 2, RAMBits 0, RAMBlocks 0
|
||||
The pipeline depth of the block is 3 cycle(s)
|
||||
@@start
|
||||
@name FPMul@
|
||||
@latency 3@
|
||||
@LUT 0@
|
||||
@DSP 2@
|
||||
@RAMBits 0@
|
||||
@RAMBlockUsage 0@
|
||||
@enable 1@
|
||||
@subnormals 0@
|
||||
@error 0.50@
|
||||
@rounding RNE@
|
||||
@method default@
|
||||
@inPort 0 fpieee 8 23@
|
||||
@inPort 1 fpieee 8 23@
|
||||
@outPort 0 fpieee 8 23@
|
||||
@nochanvalid 1@
|
||||
@@end
|
||||
starting execution ...
|
||||
build model options ...
|
||||
argc=22
|
||||
Generation context:
|
||||
Will not generate valid and channel signals
|
||||
HardFP is enabled enabling set to true
|
||||
Correct rounding constraint detected
|
||||
Will not generate valid and channel signals
|
||||
The new component name is acl_fmadd
|
||||
Frequency 250MHz
|
||||
Deployment FPGA Stratix10
|
||||
Estimated resources LUTs 0, DSPs 2, RAMBits 0, RAMBlocks 0
|
||||
The pipeline depth of the block is 4 cycle(s)
|
||||
@@start
|
||||
@name FPMultAdd@
|
||||
@latency 4@
|
||||
@LUT 0@
|
||||
@DSP 2@
|
||||
@RAMBits 0@
|
||||
@RAMBlockUsage 0@
|
||||
@enable 1@
|
||||
@subnormals 0@
|
||||
@error 0.50@
|
||||
@rounding RNE@
|
||||
@method multadd@
|
||||
@inPort 0 fpieee 8 23@
|
||||
@inPort 1 fpieee 8 23@
|
||||
@inPort 2 fpieee 8 23@
|
||||
@outPort 0 fpieee 8 23@
|
||||
@nochanvalid 1@
|
||||
@@end
|
||||
starting execution ...
|
||||
build model options ...
|
||||
argc=23
|
||||
Generation context:
|
||||
Will not generate valid and channel signals
|
||||
HardFP is enabled enabling set to true
|
||||
Correct rounding constraint detected
|
||||
Will not generate valid and channel signals
|
||||
The new component name is acl_fdiv
|
||||
Frequency 250MHz
|
||||
Deployment FPGA Stratix10
|
||||
Estimated resources LUTs 1232, DSPs 7, RAMBits 34304, RAMBlocks 3
|
||||
The pipeline depth of the block is 34 cycle(s)
|
||||
@@start
|
||||
@name FPDiv@
|
||||
@latency 34@
|
||||
@LUT 1232@
|
||||
@DSP 7@
|
||||
@RAMBits 34304@
|
||||
@RAMBlockUsage 3@
|
||||
@enable 1@
|
||||
@subnormals 0@
|
||||
@error 0.50@
|
||||
@rounding RNE@
|
||||
@method polynomial approximation@
|
||||
@inPort 0 fpieee 8 23@
|
||||
@inPort 1 fpieee 8 23@
|
||||
@outPort 0 fpieee 8 23@
|
||||
@nochanvalid 1@
|
||||
@@end
|
||||
starting execution ...
|
||||
build model options ...
|
||||
argc=22
|
||||
Generation context:
|
||||
Will not generate valid and channel signals
|
||||
HardFP is enabled enabling set to true
|
||||
Correct rounding constraint detected
|
||||
Will not generate valid and channel signals
|
||||
The new component name is acl_fsqrt
|
||||
Frequency 250MHz
|
||||
Deployment FPGA Stratix10
|
||||
Estimated resources LUTs 609, DSPs 5, RAMBits 15872, RAMBlocks 3
|
||||
The pipeline depth of the block is 25 cycle(s)
|
||||
@@start
|
||||
@name FPSqrt@
|
||||
@latency 25@
|
||||
@LUT 609@
|
||||
@DSP 5@
|
||||
@RAMBits 15872@
|
||||
@RAMBlockUsage 3@
|
||||
@enable 1@
|
||||
@subnormals 0@
|
||||
@error 0.50@
|
||||
@rounding RNE@
|
||||
@method polynomial approximation@
|
||||
@inPort 0 fpieee 8 23@
|
||||
@outPort 0 fpieee 8 23@
|
||||
@nochanvalid 1@
|
||||
@@end
|
||||
starting execution ...
|
||||
build model options ...
|
||||
argc=25
|
||||
Generation context:
|
||||
Will not generate valid and channel signals
|
||||
HardFP is enabled enabling set to true
|
||||
Correct rounding constraint detected
|
||||
Will not generate valid and channel signals
|
||||
The new component name is acl_ftoi
|
||||
Frequency 250MHz
|
||||
Deployment FPGA Stratix10
|
||||
Estimated resources LUTs 344, DSPs 0, RAMBits 0, RAMBlocks 0
|
||||
The pipeline depth of the block is 3 cycle(s)
|
||||
@@start
|
||||
@name FPToFXP@
|
||||
@latency 3@
|
||||
@LUT 344@
|
||||
@DSP 0@
|
||||
@RAMBits 0@
|
||||
@RAMBlockUsage 0@
|
||||
@enable 1@
|
||||
@subnormals 0@
|
||||
@error 0.50@
|
||||
@rounding RNE@
|
||||
@method default@
|
||||
@inPort 0 fpieee 8 23@
|
||||
@outPort 0 fxp 32 0 1@
|
||||
@nochanvalid 1@
|
||||
@@end
|
||||
starting execution ...
|
||||
build model options ...
|
||||
argc=25
|
||||
Generation context:
|
||||
Will not generate valid and channel signals
|
||||
HardFP is enabled enabling set to true
|
||||
Correct rounding constraint detected
|
||||
Will not generate valid and channel signals
|
||||
The new component name is acl_ftou
|
||||
Frequency 250MHz
|
||||
Deployment FPGA Stratix10
|
||||
Estimated resources LUTs 272, DSPs 0, RAMBits 0, RAMBlocks 0
|
||||
The pipeline depth of the block is 3 cycle(s)
|
||||
@@start
|
||||
@name FPToFXP@
|
||||
@latency 3@
|
||||
@LUT 272@
|
||||
@DSP 0@
|
||||
@RAMBits 0@
|
||||
@RAMBlockUsage 0@
|
||||
@enable 1@
|
||||
@subnormals 0@
|
||||
@error 0.50@
|
||||
@rounding RNE@
|
||||
@method default@
|
||||
@inPort 0 fpieee 8 23@
|
||||
@outPort 0 fxp 32 0 0@
|
||||
@nochanvalid 1@
|
||||
@@end
|
||||
starting execution ...
|
||||
build model options ...
|
||||
argc=25
|
||||
Generation context:
|
||||
Will not generate valid and channel signals
|
||||
HardFP is enabled enabling set to true
|
||||
Correct rounding constraint detected
|
||||
Will not generate valid and channel signals
|
||||
The new component name is acl_itof
|
||||
Frequency 250MHz
|
||||
Deployment FPGA Stratix10
|
||||
Estimated resources LUTs 362, DSPs 0, RAMBits 0, RAMBlocks 0
|
||||
The pipeline depth of the block is 7 cycle(s)
|
||||
@@start
|
||||
@name FXPToFP@
|
||||
@latency 7@
|
||||
@LUT 362@
|
||||
@DSP 0@
|
||||
@RAMBits 0@
|
||||
@RAMBlockUsage 0@
|
||||
@enable 1@
|
||||
@subnormals 0@
|
||||
@error 0.50@
|
||||
@rounding RNE@
|
||||
@method default@
|
||||
@inPort 0 fxp 32 0 1@
|
||||
@outPort 0 fpieee 8 23@
|
||||
@nochanvalid 1@
|
||||
@@end
|
||||
starting execution ...
|
||||
build model options ...
|
||||
argc=25
|
||||
Generation context:
|
||||
Will not generate valid and channel signals
|
||||
HardFP is enabled enabling set to true
|
||||
Correct rounding constraint detected
|
||||
Will not generate valid and channel signals
|
||||
The new component name is acl_utof
|
||||
Frequency 300MHz
|
||||
Deployment FPGA Stratix10
|
||||
Estimated resources LUTs 310, DSPs 0, RAMBits 0, RAMBlocks 0
|
||||
The pipeline depth of the block is 7 cycle(s)
|
||||
@@start
|
||||
@name FXPToFP@
|
||||
@latency 7@
|
||||
@LUT 310@
|
||||
@DSP 0@
|
||||
@RAMBits 0@
|
||||
@RAMBlockUsage 0@
|
||||
@enable 1@
|
||||
@subnormals 0@
|
||||
@error 0.50@
|
||||
@rounding RNE@
|
||||
@method default@
|
||||
@inPort 0 fxp 32 0 0@
|
||||
@outPort 0 fpieee 8 23@
|
||||
@nochanvalid 1@
|
||||
@@end
|
||||
33
hw/rtl/fp_cores/altera/stratix10/acl_gen.sh
Executable file
33
hw/rtl/fp_cores/altera/stratix10/acl_gen.sh
Executable file
|
|
@ -0,0 +1,33 @@
|
|||
#!/bin/bash
|
||||
|
||||
FAMILY=Stratix10
|
||||
PREFIX=acl
|
||||
|
||||
CMD_POLY_EVAL_PATH=$QUARTUS_HOME/dspba/backend/linux64
|
||||
|
||||
OPTIONS="-target $FAMILY -noChanValid -enable -enableHardFP 1 -printMachineReadable -lang verilog -correctRounding -noChanValid -enable -speedgrade 2"
|
||||
|
||||
export LD_LIBRARY_PATH=$CMD_POLY_EVAL_PATH:$LD_LIBRARY_PATH
|
||||
|
||||
CMD="$CMD_POLY_EVAL_PATH/cmdPolyEval $OPTIONS"
|
||||
|
||||
EXP_BITS=8
|
||||
MAN_BITS=23
|
||||
|
||||
FBITS="f$(($EXP_BITS + $MAN_BITS + 1))"
|
||||
|
||||
echo Generating IP cores for $FBITS
|
||||
{
|
||||
$CMD -name "$PREFIX"_fadd -frequency 250 FPAdd $EXP_BITS $MAN_BITS
|
||||
$CMD -name "$PREFIX"_fsub -frequency 250 FPSub $EXP_BITS $MAN_BITS
|
||||
$CMD -name "$PREFIX"_fmul -frequency 250 FPMul $EXP_BITS $MAN_BITS
|
||||
$CMD -name "$PREFIX"_fmadd -frequency 250 FPMultAdd $EXP_BITS $MAN_BITS
|
||||
$CMD -name "$PREFIX"_fdiv -frequency 250 FPDiv $EXP_BITS $MAN_BITS 0
|
||||
$CMD -name "$PREFIX"_fsqrt -frequency 250 FPSqrt $EXP_BITS $MAN_BITS
|
||||
$CMD -name "$PREFIX"_ftoi -frequency 250 FPToFXP $EXP_BITS $MAN_BITS 32 0 1
|
||||
$CMD -name "$PREFIX"_ftou -frequency 250 FPToFXP $EXP_BITS $MAN_BITS 32 0 0
|
||||
$CMD -name "$PREFIX"_itof -frequency 250 FXPToFP 32 0 1 $EXP_BITS $MAN_BITS
|
||||
$CMD -name "$PREFIX"_utof -frequency 300 FXPToFP 32 0 0 $EXP_BITS $MAN_BITS
|
||||
} > acl_gen.log 2>&1
|
||||
|
||||
#cp $QUARTUS_HOME/dspba/backend/Libraries/sv/base/dspba_library_ver.sv .
|
||||
631
hw/rtl/fp_cores/altera/stratix10/acl_itof.sv
Normal file
631
hw/rtl/fp_cores/altera/stratix10/acl_itof.sv
Normal file
|
|
@ -0,0 +1,631 @@
|
|||
// -------------------------------------------------------------------------
|
||||
// High Level Design Compiler for Intel(R) FPGAs Version 18.1 (Release Build #277)
|
||||
// Quartus Prime development tool and MATLAB/Simulink Interface
|
||||
//
|
||||
// Legal Notice: Copyright 2019 Intel Corporation. All rights reserved.
|
||||
// Your use of Intel Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly
|
||||
// subject to the terms and conditions of the Intel FPGA Software License
|
||||
// Agreement, Intel MegaCore Function License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for
|
||||
// the sole purpose of programming logic devices manufactured by Intel
|
||||
// and sold by Intel or its authorized distributors. Please refer to the
|
||||
// applicable agreement for further details.
|
||||
// ---------------------------------------------------------------------------
|
||||
|
||||
// SystemVerilog created from acl_itof
|
||||
// SystemVerilog created on Sun Dec 27 09:48:58 2020
|
||||
|
||||
|
||||
(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *)
|
||||
module acl_itof (
|
||||
input wire [31:0] a,
|
||||
input wire [0:0] en,
|
||||
output wire [31:0] q,
|
||||
input wire clk,
|
||||
input wire areset
|
||||
);
|
||||
|
||||
wire [0:0] GND_q;
|
||||
wire [0:0] signX_uid6_fxpToFPTest_b;
|
||||
wire [31:0] xXorSign_uid7_fxpToFPTest_b;
|
||||
wire [31:0] xXorSign_uid7_fxpToFPTest_q;
|
||||
wire [32:0] yE_uid8_fxpToFPTest_a;
|
||||
wire [32:0] yE_uid8_fxpToFPTest_b;
|
||||
logic [32:0] yE_uid8_fxpToFPTest_o;
|
||||
wire [32:0] yE_uid8_fxpToFPTest_q;
|
||||
wire [31:0] y_uid9_fxpToFPTest_in;
|
||||
wire [31:0] y_uid9_fxpToFPTest_b;
|
||||
wire [5:0] maxCount_uid11_fxpToFPTest_q;
|
||||
wire [0:0] inIsZero_uid12_fxpToFPTest_qi;
|
||||
reg [0:0] inIsZero_uid12_fxpToFPTest_q;
|
||||
wire [7:0] msbIn_uid13_fxpToFPTest_q;
|
||||
wire [8:0] expPreRnd_uid14_fxpToFPTest_a;
|
||||
wire [8:0] expPreRnd_uid14_fxpToFPTest_b;
|
||||
logic [8:0] expPreRnd_uid14_fxpToFPTest_o;
|
||||
wire [8:0] expPreRnd_uid14_fxpToFPTest_q;
|
||||
wire [32:0] expFracRnd_uid16_fxpToFPTest_q;
|
||||
wire [0:0] sticky_uid20_fxpToFPTest_qi;
|
||||
reg [0:0] sticky_uid20_fxpToFPTest_q;
|
||||
wire [0:0] nr_uid21_fxpToFPTest_q;
|
||||
wire [0:0] rnd_uid22_fxpToFPTest_q;
|
||||
wire [34:0] expFracR_uid24_fxpToFPTest_a;
|
||||
wire [34:0] expFracR_uid24_fxpToFPTest_b;
|
||||
logic [34:0] expFracR_uid24_fxpToFPTest_o;
|
||||
wire [33:0] expFracR_uid24_fxpToFPTest_q;
|
||||
wire [23:0] fracR_uid25_fxpToFPTest_in;
|
||||
wire [22:0] fracR_uid25_fxpToFPTest_b;
|
||||
wire [9:0] expR_uid26_fxpToFPTest_b;
|
||||
wire [11:0] udf_uid27_fxpToFPTest_a;
|
||||
wire [11:0] udf_uid27_fxpToFPTest_b;
|
||||
logic [11:0] udf_uid27_fxpToFPTest_o;
|
||||
wire [0:0] udf_uid27_fxpToFPTest_n;
|
||||
wire [7:0] expInf_uid28_fxpToFPTest_q;
|
||||
wire [11:0] ovf_uid29_fxpToFPTest_a;
|
||||
wire [11:0] ovf_uid29_fxpToFPTest_b;
|
||||
logic [11:0] ovf_uid29_fxpToFPTest_o;
|
||||
wire [0:0] ovf_uid29_fxpToFPTest_n;
|
||||
wire [0:0] excSelector_uid30_fxpToFPTest_q;
|
||||
wire [22:0] fracZ_uid31_fxpToFPTest_q;
|
||||
wire [0:0] fracRPostExc_uid32_fxpToFPTest_s;
|
||||
reg [22:0] fracRPostExc_uid32_fxpToFPTest_q;
|
||||
wire [0:0] udfOrInZero_uid33_fxpToFPTest_q;
|
||||
wire [1:0] excSelector_uid34_fxpToFPTest_q;
|
||||
wire [7:0] expZ_uid37_fxpToFPTest_q;
|
||||
wire [7:0] expR_uid38_fxpToFPTest_in;
|
||||
wire [7:0] expR_uid38_fxpToFPTest_b;
|
||||
wire [1:0] expRPostExc_uid39_fxpToFPTest_s;
|
||||
reg [7:0] expRPostExc_uid39_fxpToFPTest_q;
|
||||
wire [31:0] outRes_uid40_fxpToFPTest_q;
|
||||
wire [31:0] zs_uid42_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
wire [0:0] vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_qi;
|
||||
reg [0:0] vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
wire [0:0] vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest_s;
|
||||
reg [31:0] vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
wire [15:0] zs_uid47_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
wire [0:0] vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
wire [31:0] cStage_uid52_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
wire [0:0] vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest_s;
|
||||
reg [31:0] vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
wire [0:0] vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
wire [31:0] cStage_uid59_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
wire [0:0] vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_s;
|
||||
reg [31:0] vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
wire [3:0] zs_uid61_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
wire [0:0] vCount_uid63_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
wire [31:0] cStage_uid66_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
wire [0:0] vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_s;
|
||||
reg [31:0] vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
wire [1:0] zs_uid68_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
wire [0:0] vCount_uid70_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
wire [31:0] cStage_uid73_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
wire [0:0] vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_s;
|
||||
reg [31:0] vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
wire [0:0] vCount_uid77_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
wire [31:0] cStage_uid80_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
wire [0:0] vStagei_uid81_lzcShifterZ1_uid10_fxpToFPTest_s;
|
||||
reg [31:0] vStagei_uid81_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
wire [5:0] vCount_uid82_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
wire [7:0] vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_a;
|
||||
wire [7:0] vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_b;
|
||||
logic [7:0] vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_o;
|
||||
wire [0:0] vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_c;
|
||||
wire [0:0] vCountFinal_uid86_lzcShifterZ1_uid10_fxpToFPTest_s;
|
||||
reg [5:0] vCountFinal_uid86_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
wire [1:0] l_uid17_fxpToFPTest_merged_bit_select_in;
|
||||
wire [0:0] l_uid17_fxpToFPTest_merged_bit_select_b;
|
||||
wire [0:0] l_uid17_fxpToFPTest_merged_bit_select_c;
|
||||
wire [15:0] rVStage_uid48_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b;
|
||||
wire [15:0] rVStage_uid48_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c;
|
||||
wire [7:0] rVStage_uid55_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b;
|
||||
wire [23:0] rVStage_uid55_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c;
|
||||
wire [3:0] rVStage_uid62_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b;
|
||||
wire [27:0] rVStage_uid62_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c;
|
||||
wire [1:0] rVStage_uid69_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b;
|
||||
wire [29:0] rVStage_uid69_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c;
|
||||
wire [0:0] rVStage_uid76_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b;
|
||||
wire [30:0] rVStage_uid76_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c;
|
||||
wire [30:0] fracRnd_uid15_fxpToFPTest_merged_bit_select_in;
|
||||
wire [23:0] fracRnd_uid15_fxpToFPTest_merged_bit_select_b;
|
||||
wire [6:0] fracRnd_uid15_fxpToFPTest_merged_bit_select_c;
|
||||
reg [23:0] redist0_fracRnd_uid15_fxpToFPTest_merged_bit_select_b_1_q;
|
||||
reg [0:0] redist1_vCount_uid70_lzcShifterZ1_uid10_fxpToFPTest_q_1_q;
|
||||
reg [0:0] redist2_vCount_uid63_lzcShifterZ1_uid10_fxpToFPTest_q_1_q;
|
||||
reg [0:0] redist3_vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest_q_2_q;
|
||||
reg [0:0] redist3_vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest_q_2_delay_0;
|
||||
reg [0:0] redist4_vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q_3_q;
|
||||
reg [0:0] redist4_vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q_3_delay_0;
|
||||
reg [0:0] redist4_vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q_3_delay_1;
|
||||
reg [0:0] redist5_vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q_4_q;
|
||||
reg [0:0] redist5_vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q_4_delay_0;
|
||||
reg [0:0] redist5_vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q_4_delay_1;
|
||||
reg [9:0] redist6_expR_uid26_fxpToFPTest_b_1_q;
|
||||
reg [22:0] redist7_fracR_uid25_fxpToFPTest_b_1_q;
|
||||
reg [0:0] redist8_inIsZero_uid12_fxpToFPTest_q_2_q;
|
||||
reg [31:0] redist9_y_uid9_fxpToFPTest_b_1_q;
|
||||
reg [31:0] redist10_y_uid9_fxpToFPTest_b_2_q;
|
||||
reg [0:0] redist11_signX_uid6_fxpToFPTest_b_7_q;
|
||||
|
||||
|
||||
// signX_uid6_fxpToFPTest(BITSELECT,5)@0
|
||||
assign signX_uid6_fxpToFPTest_b = a[31:31];
|
||||
|
||||
// redist11_signX_uid6_fxpToFPTest_b_7(DELAY,106)
|
||||
dspba_delay_ver #( .width(1), .depth(7), .reset_kind("SYNC"), .phase(0), .modulus(1) )
|
||||
redist11_signX_uid6_fxpToFPTest_b_7 ( .xin(signX_uid6_fxpToFPTest_b), .xout(redist11_signX_uid6_fxpToFPTest_b_7_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// expInf_uid28_fxpToFPTest(CONSTANT,27)
|
||||
assign expInf_uid28_fxpToFPTest_q = 8'b11111111;
|
||||
|
||||
// expZ_uid37_fxpToFPTest(CONSTANT,36)
|
||||
assign expZ_uid37_fxpToFPTest_q = 8'b00000000;
|
||||
|
||||
// rVStage_uid76_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select(BITSELECT,93)@5
|
||||
assign rVStage_uid76_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b = vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_q[31:31];
|
||||
assign rVStage_uid76_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c = vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_q[30:0];
|
||||
|
||||
// GND(CONSTANT,0)
|
||||
assign GND_q = 1'b0;
|
||||
|
||||
// cStage_uid80_lzcShifterZ1_uid10_fxpToFPTest(BITJOIN,79)@5
|
||||
assign cStage_uid80_lzcShifterZ1_uid10_fxpToFPTest_q = {rVStage_uid76_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c, GND_q};
|
||||
|
||||
// rVStage_uid69_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select(BITSELECT,92)@4
|
||||
assign rVStage_uid69_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b = vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_q[31:30];
|
||||
assign rVStage_uid69_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c = vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_q[29:0];
|
||||
|
||||
// zs_uid68_lzcShifterZ1_uid10_fxpToFPTest(CONSTANT,67)
|
||||
assign zs_uid68_lzcShifterZ1_uid10_fxpToFPTest_q = 2'b00;
|
||||
|
||||
// cStage_uid73_lzcShifterZ1_uid10_fxpToFPTest(BITJOIN,72)@4
|
||||
assign cStage_uid73_lzcShifterZ1_uid10_fxpToFPTest_q = {rVStage_uid69_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c, zs_uid68_lzcShifterZ1_uid10_fxpToFPTest_q};
|
||||
|
||||
// rVStage_uid62_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select(BITSELECT,91)@4
|
||||
assign rVStage_uid62_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b = vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_q[31:28];
|
||||
assign rVStage_uid62_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c = vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_q[27:0];
|
||||
|
||||
// zs_uid61_lzcShifterZ1_uid10_fxpToFPTest(CONSTANT,60)
|
||||
assign zs_uid61_lzcShifterZ1_uid10_fxpToFPTest_q = 4'b0000;
|
||||
|
||||
// cStage_uid66_lzcShifterZ1_uid10_fxpToFPTest(BITJOIN,65)@4
|
||||
assign cStage_uid66_lzcShifterZ1_uid10_fxpToFPTest_q = {rVStage_uid62_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c, zs_uid61_lzcShifterZ1_uid10_fxpToFPTest_q};
|
||||
|
||||
// rVStage_uid55_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select(BITSELECT,90)@3
|
||||
assign rVStage_uid55_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b = vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest_q[31:24];
|
||||
assign rVStage_uid55_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c = vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest_q[23:0];
|
||||
|
||||
// cStage_uid59_lzcShifterZ1_uid10_fxpToFPTest(BITJOIN,58)@3
|
||||
assign cStage_uid59_lzcShifterZ1_uid10_fxpToFPTest_q = {rVStage_uid55_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c, expZ_uid37_fxpToFPTest_q};
|
||||
|
||||
// rVStage_uid48_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select(BITSELECT,89)@2
|
||||
assign rVStage_uid48_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b = vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest_q[31:16];
|
||||
assign rVStage_uid48_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c = vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest_q[15:0];
|
||||
|
||||
// zs_uid47_lzcShifterZ1_uid10_fxpToFPTest(CONSTANT,46)
|
||||
assign zs_uid47_lzcShifterZ1_uid10_fxpToFPTest_q = 16'b0000000000000000;
|
||||
|
||||
// cStage_uid52_lzcShifterZ1_uid10_fxpToFPTest(BITJOIN,51)@2
|
||||
assign cStage_uid52_lzcShifterZ1_uid10_fxpToFPTest_q = {rVStage_uid48_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c, zs_uid47_lzcShifterZ1_uid10_fxpToFPTest_q};
|
||||
|
||||
// zs_uid42_lzcShifterZ1_uid10_fxpToFPTest(CONSTANT,41)
|
||||
assign zs_uid42_lzcShifterZ1_uid10_fxpToFPTest_q = 32'b00000000000000000000000000000000;
|
||||
|
||||
// xXorSign_uid7_fxpToFPTest(LOGICAL,6)@0
|
||||
assign xXorSign_uid7_fxpToFPTest_b = {{31{signX_uid6_fxpToFPTest_b[0]}}, signX_uid6_fxpToFPTest_b};
|
||||
assign xXorSign_uid7_fxpToFPTest_q = a ^ xXorSign_uid7_fxpToFPTest_b;
|
||||
|
||||
// yE_uid8_fxpToFPTest(ADD,7)@0
|
||||
assign yE_uid8_fxpToFPTest_a = {1'b0, xXorSign_uid7_fxpToFPTest_q};
|
||||
assign yE_uid8_fxpToFPTest_b = {32'b00000000000000000000000000000000, signX_uid6_fxpToFPTest_b};
|
||||
assign yE_uid8_fxpToFPTest_o = $unsigned(yE_uid8_fxpToFPTest_a) + $unsigned(yE_uid8_fxpToFPTest_b);
|
||||
assign yE_uid8_fxpToFPTest_q = yE_uid8_fxpToFPTest_o[32:0];
|
||||
|
||||
// y_uid9_fxpToFPTest(BITSELECT,8)@0
|
||||
assign y_uid9_fxpToFPTest_in = yE_uid8_fxpToFPTest_q[31:0];
|
||||
assign y_uid9_fxpToFPTest_b = y_uid9_fxpToFPTest_in[31:0];
|
||||
|
||||
// redist9_y_uid9_fxpToFPTest_b_1(DELAY,104)
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
redist9_y_uid9_fxpToFPTest_b_1_q <= '0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
redist9_y_uid9_fxpToFPTest_b_1_q <= y_uid9_fxpToFPTest_b;
|
||||
end
|
||||
end
|
||||
|
||||
// redist10_y_uid9_fxpToFPTest_b_2(DELAY,105)
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
redist10_y_uid9_fxpToFPTest_b_2_q <= '0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
redist10_y_uid9_fxpToFPTest_b_2_q <= redist9_y_uid9_fxpToFPTest_b_1_q;
|
||||
end
|
||||
end
|
||||
|
||||
// vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest(LOGICAL,43)@1 + 1
|
||||
assign vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_qi = redist9_y_uid9_fxpToFPTest_b_1_q == zs_uid42_lzcShifterZ1_uid10_fxpToFPTest_q ? 1'b1 : 1'b0;
|
||||
dspba_delay_ver #( .width(1), .depth(1), .reset_kind("SYNC"), .phase(0), .modulus(1) )
|
||||
vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_delay ( .xin(vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_qi), .xout(vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest(MUX,45)@2
|
||||
assign vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest_s = vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
always @(vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest_s or en or redist10_y_uid9_fxpToFPTest_b_2_q or zs_uid42_lzcShifterZ1_uid10_fxpToFPTest_q)
|
||||
begin
|
||||
unique case (vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest_s)
|
||||
1'b0 : vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest_q = redist10_y_uid9_fxpToFPTest_b_2_q;
|
||||
1'b1 : vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest_q = zs_uid42_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
default : vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest_q = 32'b0;
|
||||
endcase
|
||||
end
|
||||
|
||||
// vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest(LOGICAL,48)@2
|
||||
assign vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q = rVStage_uid48_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b == zs_uid47_lzcShifterZ1_uid10_fxpToFPTest_q ? 1'b1 : 1'b0;
|
||||
|
||||
// vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest(MUX,52)@2 + 1
|
||||
assign vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest_s = vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest_q <= 32'b0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
unique case (vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest_s)
|
||||
1'b0 : vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest_q <= vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
1'b1 : vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest_q <= cStage_uid52_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
default : vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest_q <= 32'b0;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
// vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest(LOGICAL,55)@3
|
||||
assign vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest_q = rVStage_uid55_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b == expZ_uid37_fxpToFPTest_q ? 1'b1 : 1'b0;
|
||||
|
||||
// vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest(MUX,59)@3 + 1
|
||||
assign vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_s = vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_q <= 32'b0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
unique case (vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_s)
|
||||
1'b0 : vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_q <= vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
1'b1 : vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_q <= cStage_uid59_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
default : vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_q <= 32'b0;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
// vCount_uid63_lzcShifterZ1_uid10_fxpToFPTest(LOGICAL,62)@4
|
||||
assign vCount_uid63_lzcShifterZ1_uid10_fxpToFPTest_q = rVStage_uid62_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b == zs_uid61_lzcShifterZ1_uid10_fxpToFPTest_q ? 1'b1 : 1'b0;
|
||||
|
||||
// vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest(MUX,66)@4
|
||||
assign vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_s = vCount_uid63_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
always @(vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_s or en or vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_q or cStage_uid66_lzcShifterZ1_uid10_fxpToFPTest_q)
|
||||
begin
|
||||
unique case (vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_s)
|
||||
1'b0 : vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_q = vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
1'b1 : vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_q = cStage_uid66_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
default : vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_q = 32'b0;
|
||||
endcase
|
||||
end
|
||||
|
||||
// vCount_uid70_lzcShifterZ1_uid10_fxpToFPTest(LOGICAL,69)@4
|
||||
assign vCount_uid70_lzcShifterZ1_uid10_fxpToFPTest_q = rVStage_uid69_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b == zs_uid68_lzcShifterZ1_uid10_fxpToFPTest_q ? 1'b1 : 1'b0;
|
||||
|
||||
// vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest(MUX,73)@4 + 1
|
||||
assign vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_s = vCount_uid70_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_q <= 32'b0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
unique case (vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_s)
|
||||
1'b0 : vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_q <= vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
1'b1 : vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_q <= cStage_uid73_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
default : vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_q <= 32'b0;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
// vCount_uid77_lzcShifterZ1_uid10_fxpToFPTest(LOGICAL,76)@5
|
||||
assign vCount_uid77_lzcShifterZ1_uid10_fxpToFPTest_q = rVStage_uid76_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b == GND_q ? 1'b1 : 1'b0;
|
||||
|
||||
// vStagei_uid81_lzcShifterZ1_uid10_fxpToFPTest(MUX,80)@5
|
||||
assign vStagei_uid81_lzcShifterZ1_uid10_fxpToFPTest_s = vCount_uid77_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
always @(vStagei_uid81_lzcShifterZ1_uid10_fxpToFPTest_s or en or vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_q or cStage_uid80_lzcShifterZ1_uid10_fxpToFPTest_q)
|
||||
begin
|
||||
unique case (vStagei_uid81_lzcShifterZ1_uid10_fxpToFPTest_s)
|
||||
1'b0 : vStagei_uid81_lzcShifterZ1_uid10_fxpToFPTest_q = vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
1'b1 : vStagei_uid81_lzcShifterZ1_uid10_fxpToFPTest_q = cStage_uid80_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
default : vStagei_uid81_lzcShifterZ1_uid10_fxpToFPTest_q = 32'b0;
|
||||
endcase
|
||||
end
|
||||
|
||||
// fracRnd_uid15_fxpToFPTest_merged_bit_select(BITSELECT,94)@5
|
||||
assign fracRnd_uid15_fxpToFPTest_merged_bit_select_in = vStagei_uid81_lzcShifterZ1_uid10_fxpToFPTest_q[30:0];
|
||||
assign fracRnd_uid15_fxpToFPTest_merged_bit_select_b = fracRnd_uid15_fxpToFPTest_merged_bit_select_in[30:7];
|
||||
assign fracRnd_uid15_fxpToFPTest_merged_bit_select_c = fracRnd_uid15_fxpToFPTest_merged_bit_select_in[6:0];
|
||||
|
||||
// sticky_uid20_fxpToFPTest(LOGICAL,19)@5 + 1
|
||||
assign sticky_uid20_fxpToFPTest_qi = fracRnd_uid15_fxpToFPTest_merged_bit_select_c != 7'b0000000 ? 1'b1 : 1'b0;
|
||||
dspba_delay_ver #( .width(1), .depth(1), .reset_kind("SYNC"), .phase(0), .modulus(1) )
|
||||
sticky_uid20_fxpToFPTest_delay ( .xin(sticky_uid20_fxpToFPTest_qi), .xout(sticky_uid20_fxpToFPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// nr_uid21_fxpToFPTest(LOGICAL,20)@6
|
||||
assign nr_uid21_fxpToFPTest_q = ~ (l_uid17_fxpToFPTest_merged_bit_select_c);
|
||||
|
||||
// l_uid17_fxpToFPTest_merged_bit_select(BITSELECT,88)@6
|
||||
assign l_uid17_fxpToFPTest_merged_bit_select_in = expFracRnd_uid16_fxpToFPTest_q[1:0];
|
||||
assign l_uid17_fxpToFPTest_merged_bit_select_b = l_uid17_fxpToFPTest_merged_bit_select_in[1:1];
|
||||
assign l_uid17_fxpToFPTest_merged_bit_select_c = l_uid17_fxpToFPTest_merged_bit_select_in[0:0];
|
||||
|
||||
// rnd_uid22_fxpToFPTest(LOGICAL,21)@6
|
||||
assign rnd_uid22_fxpToFPTest_q = l_uid17_fxpToFPTest_merged_bit_select_b | nr_uid21_fxpToFPTest_q | sticky_uid20_fxpToFPTest_q;
|
||||
|
||||
// maxCount_uid11_fxpToFPTest(CONSTANT,10)
|
||||
assign maxCount_uid11_fxpToFPTest_q = 6'b100000;
|
||||
|
||||
// redist5_vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q_4(DELAY,100)
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
redist5_vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q_4_delay_0 <= '0;
|
||||
redist5_vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q_4_delay_1 <= '0;
|
||||
redist5_vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q_4_q <= '0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
redist5_vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q_4_delay_0 <= vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
redist5_vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q_4_delay_1 <= redist5_vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q_4_delay_0;
|
||||
redist5_vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q_4_q <= redist5_vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q_4_delay_1;
|
||||
end
|
||||
end
|
||||
|
||||
// redist4_vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q_3(DELAY,99)
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
redist4_vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q_3_delay_0 <= '0;
|
||||
redist4_vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q_3_delay_1 <= '0;
|
||||
redist4_vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q_3_q <= '0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
redist4_vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q_3_delay_0 <= vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
redist4_vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q_3_delay_1 <= redist4_vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q_3_delay_0;
|
||||
redist4_vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q_3_q <= redist4_vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q_3_delay_1;
|
||||
end
|
||||
end
|
||||
|
||||
// redist3_vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest_q_2(DELAY,98)
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
redist3_vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest_q_2_delay_0 <= '0;
|
||||
redist3_vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest_q_2_q <= '0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
redist3_vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest_q_2_delay_0 <= vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
redist3_vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest_q_2_q <= redist3_vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest_q_2_delay_0;
|
||||
end
|
||||
end
|
||||
|
||||
// redist2_vCount_uid63_lzcShifterZ1_uid10_fxpToFPTest_q_1(DELAY,97)
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
redist2_vCount_uid63_lzcShifterZ1_uid10_fxpToFPTest_q_1_q <= '0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
redist2_vCount_uid63_lzcShifterZ1_uid10_fxpToFPTest_q_1_q <= vCount_uid63_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
end
|
||||
end
|
||||
|
||||
// redist1_vCount_uid70_lzcShifterZ1_uid10_fxpToFPTest_q_1(DELAY,96)
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
redist1_vCount_uid70_lzcShifterZ1_uid10_fxpToFPTest_q_1_q <= '0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
redist1_vCount_uid70_lzcShifterZ1_uid10_fxpToFPTest_q_1_q <= vCount_uid70_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
end
|
||||
end
|
||||
|
||||
// vCount_uid82_lzcShifterZ1_uid10_fxpToFPTest(BITJOIN,81)@5
|
||||
assign vCount_uid82_lzcShifterZ1_uid10_fxpToFPTest_q = {redist5_vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q_4_q, redist4_vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q_3_q, redist3_vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest_q_2_q, redist2_vCount_uid63_lzcShifterZ1_uid10_fxpToFPTest_q_1_q, redist1_vCount_uid70_lzcShifterZ1_uid10_fxpToFPTest_q_1_q, vCount_uid77_lzcShifterZ1_uid10_fxpToFPTest_q};
|
||||
|
||||
// vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest(COMPARE,83)@5
|
||||
assign vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_a = {2'b00, maxCount_uid11_fxpToFPTest_q};
|
||||
assign vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_b = {2'b00, vCount_uid82_lzcShifterZ1_uid10_fxpToFPTest_q};
|
||||
assign vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_o = $unsigned(vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_a) - $unsigned(vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_b);
|
||||
assign vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_c[0] = vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_o[7];
|
||||
|
||||
// vCountFinal_uid86_lzcShifterZ1_uid10_fxpToFPTest(MUX,85)@5
|
||||
assign vCountFinal_uid86_lzcShifterZ1_uid10_fxpToFPTest_s = vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_c;
|
||||
always @(vCountFinal_uid86_lzcShifterZ1_uid10_fxpToFPTest_s or en or vCount_uid82_lzcShifterZ1_uid10_fxpToFPTest_q or maxCount_uid11_fxpToFPTest_q)
|
||||
begin
|
||||
unique case (vCountFinal_uid86_lzcShifterZ1_uid10_fxpToFPTest_s)
|
||||
1'b0 : vCountFinal_uid86_lzcShifterZ1_uid10_fxpToFPTest_q = vCount_uid82_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
1'b1 : vCountFinal_uid86_lzcShifterZ1_uid10_fxpToFPTest_q = maxCount_uid11_fxpToFPTest_q;
|
||||
default : vCountFinal_uid86_lzcShifterZ1_uid10_fxpToFPTest_q = 6'b0;
|
||||
endcase
|
||||
end
|
||||
|
||||
// msbIn_uid13_fxpToFPTest(CONSTANT,12)
|
||||
assign msbIn_uid13_fxpToFPTest_q = 8'b10011110;
|
||||
|
||||
// expPreRnd_uid14_fxpToFPTest(SUB,13)@5 + 1
|
||||
assign expPreRnd_uid14_fxpToFPTest_a = {1'b0, msbIn_uid13_fxpToFPTest_q};
|
||||
assign expPreRnd_uid14_fxpToFPTest_b = {3'b000, vCountFinal_uid86_lzcShifterZ1_uid10_fxpToFPTest_q};
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
expPreRnd_uid14_fxpToFPTest_o <= 9'b0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
expPreRnd_uid14_fxpToFPTest_o <= $unsigned(expPreRnd_uid14_fxpToFPTest_a) - $unsigned(expPreRnd_uid14_fxpToFPTest_b);
|
||||
end
|
||||
end
|
||||
assign expPreRnd_uid14_fxpToFPTest_q = expPreRnd_uid14_fxpToFPTest_o[8:0];
|
||||
|
||||
// redist0_fracRnd_uid15_fxpToFPTest_merged_bit_select_b_1(DELAY,95)
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
redist0_fracRnd_uid15_fxpToFPTest_merged_bit_select_b_1_q <= '0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
redist0_fracRnd_uid15_fxpToFPTest_merged_bit_select_b_1_q <= fracRnd_uid15_fxpToFPTest_merged_bit_select_b;
|
||||
end
|
||||
end
|
||||
|
||||
// expFracRnd_uid16_fxpToFPTest(BITJOIN,15)@6
|
||||
assign expFracRnd_uid16_fxpToFPTest_q = {expPreRnd_uid14_fxpToFPTest_q, redist0_fracRnd_uid15_fxpToFPTest_merged_bit_select_b_1_q};
|
||||
|
||||
// expFracR_uid24_fxpToFPTest(ADD,23)@6
|
||||
assign expFracR_uid24_fxpToFPTest_a = {{2{expFracRnd_uid16_fxpToFPTest_q[32]}}, expFracRnd_uid16_fxpToFPTest_q};
|
||||
assign expFracR_uid24_fxpToFPTest_b = {34'b0000000000000000000000000000000000, rnd_uid22_fxpToFPTest_q};
|
||||
assign expFracR_uid24_fxpToFPTest_o = $signed(expFracR_uid24_fxpToFPTest_a) + $signed(expFracR_uid24_fxpToFPTest_b);
|
||||
assign expFracR_uid24_fxpToFPTest_q = expFracR_uid24_fxpToFPTest_o[33:0];
|
||||
|
||||
// expR_uid26_fxpToFPTest(BITSELECT,25)@6
|
||||
assign expR_uid26_fxpToFPTest_b = expFracR_uid24_fxpToFPTest_q[33:24];
|
||||
|
||||
// redist6_expR_uid26_fxpToFPTest_b_1(DELAY,101)
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
redist6_expR_uid26_fxpToFPTest_b_1_q <= '0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
redist6_expR_uid26_fxpToFPTest_b_1_q <= expR_uid26_fxpToFPTest_b;
|
||||
end
|
||||
end
|
||||
|
||||
// expR_uid38_fxpToFPTest(BITSELECT,37)@7
|
||||
assign expR_uid38_fxpToFPTest_in = redist6_expR_uid26_fxpToFPTest_b_1_q[7:0];
|
||||
assign expR_uid38_fxpToFPTest_b = expR_uid38_fxpToFPTest_in[7:0];
|
||||
|
||||
// ovf_uid29_fxpToFPTest(COMPARE,28)@7
|
||||
assign ovf_uid29_fxpToFPTest_a = {{2{redist6_expR_uid26_fxpToFPTest_b_1_q[9]}}, redist6_expR_uid26_fxpToFPTest_b_1_q};
|
||||
assign ovf_uid29_fxpToFPTest_b = {4'b0000, expInf_uid28_fxpToFPTest_q};
|
||||
assign ovf_uid29_fxpToFPTest_o = $signed(ovf_uid29_fxpToFPTest_a) - $signed(ovf_uid29_fxpToFPTest_b);
|
||||
assign ovf_uid29_fxpToFPTest_n[0] = ~ (ovf_uid29_fxpToFPTest_o[11]);
|
||||
|
||||
// inIsZero_uid12_fxpToFPTest(LOGICAL,11)@5 + 1
|
||||
assign inIsZero_uid12_fxpToFPTest_qi = vCountFinal_uid86_lzcShifterZ1_uid10_fxpToFPTest_q == maxCount_uid11_fxpToFPTest_q ? 1'b1 : 1'b0;
|
||||
dspba_delay_ver #( .width(1), .depth(1), .reset_kind("SYNC"), .phase(0), .modulus(1) )
|
||||
inIsZero_uid12_fxpToFPTest_delay ( .xin(inIsZero_uid12_fxpToFPTest_qi), .xout(inIsZero_uid12_fxpToFPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// redist8_inIsZero_uid12_fxpToFPTest_q_2(DELAY,103)
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
redist8_inIsZero_uid12_fxpToFPTest_q_2_q <= '0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
redist8_inIsZero_uid12_fxpToFPTest_q_2_q <= inIsZero_uid12_fxpToFPTest_q;
|
||||
end
|
||||
end
|
||||
|
||||
// udf_uid27_fxpToFPTest(COMPARE,26)@7
|
||||
assign udf_uid27_fxpToFPTest_a = {11'b00000000000, GND_q};
|
||||
assign udf_uid27_fxpToFPTest_b = {{2{redist6_expR_uid26_fxpToFPTest_b_1_q[9]}}, redist6_expR_uid26_fxpToFPTest_b_1_q};
|
||||
assign udf_uid27_fxpToFPTest_o = $signed(udf_uid27_fxpToFPTest_a) - $signed(udf_uid27_fxpToFPTest_b);
|
||||
assign udf_uid27_fxpToFPTest_n[0] = ~ (udf_uid27_fxpToFPTest_o[11]);
|
||||
|
||||
// udfOrInZero_uid33_fxpToFPTest(LOGICAL,32)@7
|
||||
assign udfOrInZero_uid33_fxpToFPTest_q = udf_uid27_fxpToFPTest_n | redist8_inIsZero_uid12_fxpToFPTest_q_2_q;
|
||||
|
||||
// excSelector_uid34_fxpToFPTest(BITJOIN,33)@7
|
||||
assign excSelector_uid34_fxpToFPTest_q = {ovf_uid29_fxpToFPTest_n, udfOrInZero_uid33_fxpToFPTest_q};
|
||||
|
||||
// expRPostExc_uid39_fxpToFPTest(MUX,38)@7
|
||||
assign expRPostExc_uid39_fxpToFPTest_s = excSelector_uid34_fxpToFPTest_q;
|
||||
always @(expRPostExc_uid39_fxpToFPTest_s or en or expR_uid38_fxpToFPTest_b or expZ_uid37_fxpToFPTest_q or expInf_uid28_fxpToFPTest_q)
|
||||
begin
|
||||
unique case (expRPostExc_uid39_fxpToFPTest_s)
|
||||
2'b00 : expRPostExc_uid39_fxpToFPTest_q = expR_uid38_fxpToFPTest_b;
|
||||
2'b01 : expRPostExc_uid39_fxpToFPTest_q = expZ_uid37_fxpToFPTest_q;
|
||||
2'b10 : expRPostExc_uid39_fxpToFPTest_q = expInf_uid28_fxpToFPTest_q;
|
||||
2'b11 : expRPostExc_uid39_fxpToFPTest_q = expInf_uid28_fxpToFPTest_q;
|
||||
default : expRPostExc_uid39_fxpToFPTest_q = 8'b0;
|
||||
endcase
|
||||
end
|
||||
|
||||
// fracZ_uid31_fxpToFPTest(CONSTANT,30)
|
||||
assign fracZ_uid31_fxpToFPTest_q = 23'b00000000000000000000000;
|
||||
|
||||
// fracR_uid25_fxpToFPTest(BITSELECT,24)@6
|
||||
assign fracR_uid25_fxpToFPTest_in = expFracR_uid24_fxpToFPTest_q[23:0];
|
||||
assign fracR_uid25_fxpToFPTest_b = fracR_uid25_fxpToFPTest_in[23:1];
|
||||
|
||||
// redist7_fracR_uid25_fxpToFPTest_b_1(DELAY,102)
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
redist7_fracR_uid25_fxpToFPTest_b_1_q <= '0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
redist7_fracR_uid25_fxpToFPTest_b_1_q <= fracR_uid25_fxpToFPTest_b;
|
||||
end
|
||||
end
|
||||
|
||||
// excSelector_uid30_fxpToFPTest(LOGICAL,29)@7
|
||||
assign excSelector_uid30_fxpToFPTest_q = redist8_inIsZero_uid12_fxpToFPTest_q_2_q | ovf_uid29_fxpToFPTest_n | udf_uid27_fxpToFPTest_n;
|
||||
|
||||
// fracRPostExc_uid32_fxpToFPTest(MUX,31)@7
|
||||
assign fracRPostExc_uid32_fxpToFPTest_s = excSelector_uid30_fxpToFPTest_q;
|
||||
always @(fracRPostExc_uid32_fxpToFPTest_s or en or redist7_fracR_uid25_fxpToFPTest_b_1_q or fracZ_uid31_fxpToFPTest_q)
|
||||
begin
|
||||
unique case (fracRPostExc_uid32_fxpToFPTest_s)
|
||||
1'b0 : fracRPostExc_uid32_fxpToFPTest_q = redist7_fracR_uid25_fxpToFPTest_b_1_q;
|
||||
1'b1 : fracRPostExc_uid32_fxpToFPTest_q = fracZ_uid31_fxpToFPTest_q;
|
||||
default : fracRPostExc_uid32_fxpToFPTest_q = 23'b0;
|
||||
endcase
|
||||
end
|
||||
|
||||
// outRes_uid40_fxpToFPTest(BITJOIN,39)@7
|
||||
assign outRes_uid40_fxpToFPTest_q = {redist11_signX_uid6_fxpToFPTest_b_7_q, expRPostExc_uid39_fxpToFPTest_q, fracRPostExc_uid32_fxpToFPTest_q};
|
||||
|
||||
// xOut(GPOUT,4)@7
|
||||
assign q = outRes_uid40_fxpToFPTest_q;
|
||||
|
||||
endmodule
|
||||
607
hw/rtl/fp_cores/altera/stratix10/acl_utof.sv
Normal file
607
hw/rtl/fp_cores/altera/stratix10/acl_utof.sv
Normal file
|
|
@ -0,0 +1,607 @@
|
|||
// -------------------------------------------------------------------------
|
||||
// High Level Design Compiler for Intel(R) FPGAs Version 18.1 (Release Build #277)
|
||||
// Quartus Prime development tool and MATLAB/Simulink Interface
|
||||
//
|
||||
// Legal Notice: Copyright 2019 Intel Corporation. All rights reserved.
|
||||
// Your use of Intel Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly
|
||||
// subject to the terms and conditions of the Intel FPGA Software License
|
||||
// Agreement, Intel MegaCore Function License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for
|
||||
// the sole purpose of programming logic devices manufactured by Intel
|
||||
// and sold by Intel or its authorized distributors. Please refer to the
|
||||
// applicable agreement for further details.
|
||||
// ---------------------------------------------------------------------------
|
||||
|
||||
// SystemVerilog created from acl_utof
|
||||
// SystemVerilog created on Sun Dec 27 09:48:58 2020
|
||||
|
||||
|
||||
(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *)
|
||||
module acl_utof (
|
||||
input wire [31:0] a,
|
||||
input wire [0:0] en,
|
||||
output wire [31:0] q,
|
||||
input wire clk,
|
||||
input wire areset
|
||||
);
|
||||
|
||||
wire [0:0] GND_q;
|
||||
wire [5:0] maxCount_uid7_fxpToFPTest_q;
|
||||
wire [0:0] inIsZero_uid8_fxpToFPTest_qi;
|
||||
reg [0:0] inIsZero_uid8_fxpToFPTest_q;
|
||||
wire [7:0] msbIn_uid9_fxpToFPTest_q;
|
||||
wire [8:0] expPreRnd_uid10_fxpToFPTest_a;
|
||||
wire [8:0] expPreRnd_uid10_fxpToFPTest_b;
|
||||
logic [8:0] expPreRnd_uid10_fxpToFPTest_o;
|
||||
wire [8:0] expPreRnd_uid10_fxpToFPTest_q;
|
||||
wire [32:0] expFracRnd_uid12_fxpToFPTest_q;
|
||||
wire [0:0] sticky_uid16_fxpToFPTest_q;
|
||||
wire [0:0] nr_uid17_fxpToFPTest_q;
|
||||
wire [0:0] rnd_uid18_fxpToFPTest_qi;
|
||||
reg [0:0] rnd_uid18_fxpToFPTest_q;
|
||||
wire [34:0] expFracR_uid20_fxpToFPTest_a;
|
||||
wire [34:0] expFracR_uid20_fxpToFPTest_b;
|
||||
logic [34:0] expFracR_uid20_fxpToFPTest_o;
|
||||
wire [33:0] expFracR_uid20_fxpToFPTest_q;
|
||||
wire [23:0] fracR_uid21_fxpToFPTest_in;
|
||||
wire [22:0] fracR_uid21_fxpToFPTest_b;
|
||||
wire [9:0] expR_uid22_fxpToFPTest_b;
|
||||
wire [11:0] udf_uid23_fxpToFPTest_a;
|
||||
wire [11:0] udf_uid23_fxpToFPTest_b;
|
||||
logic [11:0] udf_uid23_fxpToFPTest_o;
|
||||
wire [0:0] udf_uid23_fxpToFPTest_n;
|
||||
wire [7:0] expInf_uid24_fxpToFPTest_q;
|
||||
wire [11:0] ovf_uid25_fxpToFPTest_a;
|
||||
wire [11:0] ovf_uid25_fxpToFPTest_b;
|
||||
logic [11:0] ovf_uid25_fxpToFPTest_o;
|
||||
wire [0:0] ovf_uid25_fxpToFPTest_n;
|
||||
wire [0:0] excSelector_uid26_fxpToFPTest_q;
|
||||
wire [22:0] fracZ_uid27_fxpToFPTest_q;
|
||||
wire [0:0] fracRPostExc_uid28_fxpToFPTest_s;
|
||||
reg [22:0] fracRPostExc_uid28_fxpToFPTest_q;
|
||||
wire [0:0] udfOrInZero_uid29_fxpToFPTest_q;
|
||||
wire [1:0] excSelector_uid30_fxpToFPTest_q;
|
||||
wire [7:0] expZ_uid33_fxpToFPTest_q;
|
||||
wire [7:0] expR_uid34_fxpToFPTest_in;
|
||||
wire [7:0] expR_uid34_fxpToFPTest_b;
|
||||
wire [1:0] expRPostExc_uid35_fxpToFPTest_s;
|
||||
reg [7:0] expRPostExc_uid35_fxpToFPTest_q;
|
||||
wire [31:0] outRes_uid36_fxpToFPTest_q;
|
||||
wire [31:0] zs_uid38_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
wire [0:0] vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
wire [0:0] vStagei_uid42_lzcShifterZ1_uid6_fxpToFPTest_s;
|
||||
reg [31:0] vStagei_uid42_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
wire [15:0] zs_uid43_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
wire [0:0] vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
wire [31:0] cStage_uid48_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
wire [0:0] vStagei_uid49_lzcShifterZ1_uid6_fxpToFPTest_s;
|
||||
reg [31:0] vStagei_uid49_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
wire [0:0] vCount_uid52_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
wire [31:0] cStage_uid55_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
wire [0:0] vStagei_uid56_lzcShifterZ1_uid6_fxpToFPTest_s;
|
||||
reg [31:0] vStagei_uid56_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
wire [3:0] zs_uid57_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
wire [0:0] vCount_uid59_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
wire [31:0] cStage_uid62_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
wire [0:0] vStagei_uid63_lzcShifterZ1_uid6_fxpToFPTest_s;
|
||||
reg [31:0] vStagei_uid63_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
wire [1:0] zs_uid64_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
wire [0:0] vCount_uid66_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
wire [31:0] cStage_uid69_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
wire [0:0] vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest_s;
|
||||
reg [31:0] vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
wire [0:0] vCount_uid73_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
wire [31:0] cStage_uid76_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
wire [0:0] vStagei_uid77_lzcShifterZ1_uid6_fxpToFPTest_s;
|
||||
reg [31:0] vStagei_uid77_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
wire [5:0] vCount_uid78_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
wire [7:0] vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest_a;
|
||||
wire [7:0] vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest_b;
|
||||
logic [7:0] vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest_o;
|
||||
wire [0:0] vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest_c;
|
||||
wire [0:0] vCountFinal_uid82_lzcShifterZ1_uid6_fxpToFPTest_s;
|
||||
reg [5:0] vCountFinal_uid82_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
wire [1:0] l_uid13_fxpToFPTest_merged_bit_select_in;
|
||||
wire [0:0] l_uid13_fxpToFPTest_merged_bit_select_b;
|
||||
wire [0:0] l_uid13_fxpToFPTest_merged_bit_select_c;
|
||||
wire [15:0] rVStage_uid44_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b;
|
||||
wire [15:0] rVStage_uid44_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c;
|
||||
wire [7:0] rVStage_uid51_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b;
|
||||
wire [23:0] rVStage_uid51_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c;
|
||||
wire [3:0] rVStage_uid58_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b;
|
||||
wire [27:0] rVStage_uid58_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c;
|
||||
wire [1:0] rVStage_uid65_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b;
|
||||
wire [29:0] rVStage_uid65_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c;
|
||||
wire [0:0] rVStage_uid72_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b;
|
||||
wire [30:0] rVStage_uid72_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c;
|
||||
wire [30:0] fracRnd_uid11_fxpToFPTest_merged_bit_select_in;
|
||||
wire [23:0] fracRnd_uid11_fxpToFPTest_merged_bit_select_b;
|
||||
wire [6:0] fracRnd_uid11_fxpToFPTest_merged_bit_select_c;
|
||||
reg [23:0] redist0_fracRnd_uid11_fxpToFPTest_merged_bit_select_b_1_q;
|
||||
reg [6:0] redist1_fracRnd_uid11_fxpToFPTest_merged_bit_select_c_1_q;
|
||||
reg [5:0] redist2_vCount_uid78_lzcShifterZ1_uid6_fxpToFPTest_q_1_q;
|
||||
reg [0:0] redist3_vCount_uid59_lzcShifterZ1_uid6_fxpToFPTest_q_1_q;
|
||||
reg [0:0] redist4_vCount_uid52_lzcShifterZ1_uid6_fxpToFPTest_q_2_q;
|
||||
reg [0:0] redist4_vCount_uid52_lzcShifterZ1_uid6_fxpToFPTest_q_2_delay_0;
|
||||
reg [0:0] redist5_vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest_q_3_q;
|
||||
reg [0:0] redist5_vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest_q_3_delay_0;
|
||||
reg [0:0] redist5_vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest_q_3_delay_1;
|
||||
reg [0:0] redist6_vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q_4_q;
|
||||
reg [0:0] redist6_vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q_4_delay_0;
|
||||
reg [0:0] redist6_vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q_4_delay_1;
|
||||
reg [0:0] redist6_vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q_4_delay_2;
|
||||
reg [9:0] redist7_expR_uid22_fxpToFPTest_b_1_q;
|
||||
reg [22:0] redist8_fracR_uid21_fxpToFPTest_b_1_q;
|
||||
reg [32:0] redist9_expFracRnd_uid12_fxpToFPTest_q_1_q;
|
||||
reg [0:0] redist10_inIsZero_uid8_fxpToFPTest_q_2_q;
|
||||
|
||||
|
||||
// GND(CONSTANT,0)
|
||||
assign GND_q = 1'b0;
|
||||
|
||||
// expInf_uid24_fxpToFPTest(CONSTANT,23)
|
||||
assign expInf_uid24_fxpToFPTest_q = 8'b11111111;
|
||||
|
||||
// expZ_uid33_fxpToFPTest(CONSTANT,32)
|
||||
assign expZ_uid33_fxpToFPTest_q = 8'b00000000;
|
||||
|
||||
// rVStage_uid72_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select(BITSELECT,89)@4
|
||||
assign rVStage_uid72_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b = vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest_q[31:31];
|
||||
assign rVStage_uid72_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c = vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest_q[30:0];
|
||||
|
||||
// cStage_uid76_lzcShifterZ1_uid6_fxpToFPTest(BITJOIN,75)@4
|
||||
assign cStage_uid76_lzcShifterZ1_uid6_fxpToFPTest_q = {rVStage_uid72_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c, GND_q};
|
||||
|
||||
// rVStage_uid65_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select(BITSELECT,88)@4
|
||||
assign rVStage_uid65_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b = vStagei_uid63_lzcShifterZ1_uid6_fxpToFPTest_q[31:30];
|
||||
assign rVStage_uid65_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c = vStagei_uid63_lzcShifterZ1_uid6_fxpToFPTest_q[29:0];
|
||||
|
||||
// zs_uid64_lzcShifterZ1_uid6_fxpToFPTest(CONSTANT,63)
|
||||
assign zs_uid64_lzcShifterZ1_uid6_fxpToFPTest_q = 2'b00;
|
||||
|
||||
// cStage_uid69_lzcShifterZ1_uid6_fxpToFPTest(BITJOIN,68)@4
|
||||
assign cStage_uid69_lzcShifterZ1_uid6_fxpToFPTest_q = {rVStage_uid65_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c, zs_uid64_lzcShifterZ1_uid6_fxpToFPTest_q};
|
||||
|
||||
// rVStage_uid58_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select(BITSELECT,87)@3
|
||||
assign rVStage_uid58_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b = vStagei_uid56_lzcShifterZ1_uid6_fxpToFPTest_q[31:28];
|
||||
assign rVStage_uid58_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c = vStagei_uid56_lzcShifterZ1_uid6_fxpToFPTest_q[27:0];
|
||||
|
||||
// zs_uid57_lzcShifterZ1_uid6_fxpToFPTest(CONSTANT,56)
|
||||
assign zs_uid57_lzcShifterZ1_uid6_fxpToFPTest_q = 4'b0000;
|
||||
|
||||
// cStage_uid62_lzcShifterZ1_uid6_fxpToFPTest(BITJOIN,61)@3
|
||||
assign cStage_uid62_lzcShifterZ1_uid6_fxpToFPTest_q = {rVStage_uid58_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c, zs_uid57_lzcShifterZ1_uid6_fxpToFPTest_q};
|
||||
|
||||
// rVStage_uid51_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select(BITSELECT,86)@2
|
||||
assign rVStage_uid51_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b = vStagei_uid49_lzcShifterZ1_uid6_fxpToFPTest_q[31:24];
|
||||
assign rVStage_uid51_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c = vStagei_uid49_lzcShifterZ1_uid6_fxpToFPTest_q[23:0];
|
||||
|
||||
// cStage_uid55_lzcShifterZ1_uid6_fxpToFPTest(BITJOIN,54)@2
|
||||
assign cStage_uid55_lzcShifterZ1_uid6_fxpToFPTest_q = {rVStage_uid51_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c, expZ_uid33_fxpToFPTest_q};
|
||||
|
||||
// rVStage_uid44_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select(BITSELECT,85)@1
|
||||
assign rVStage_uid44_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b = vStagei_uid42_lzcShifterZ1_uid6_fxpToFPTest_q[31:16];
|
||||
assign rVStage_uid44_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c = vStagei_uid42_lzcShifterZ1_uid6_fxpToFPTest_q[15:0];
|
||||
|
||||
// zs_uid43_lzcShifterZ1_uid6_fxpToFPTest(CONSTANT,42)
|
||||
assign zs_uid43_lzcShifterZ1_uid6_fxpToFPTest_q = 16'b0000000000000000;
|
||||
|
||||
// cStage_uid48_lzcShifterZ1_uid6_fxpToFPTest(BITJOIN,47)@1
|
||||
assign cStage_uid48_lzcShifterZ1_uid6_fxpToFPTest_q = {rVStage_uid44_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c, zs_uid43_lzcShifterZ1_uid6_fxpToFPTest_q};
|
||||
|
||||
// zs_uid38_lzcShifterZ1_uid6_fxpToFPTest(CONSTANT,37)
|
||||
assign zs_uid38_lzcShifterZ1_uid6_fxpToFPTest_q = 32'b00000000000000000000000000000000;
|
||||
|
||||
// vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest(LOGICAL,39)@0
|
||||
assign vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q = a == zs_uid38_lzcShifterZ1_uid6_fxpToFPTest_q ? 1'b1 : 1'b0;
|
||||
|
||||
// vStagei_uid42_lzcShifterZ1_uid6_fxpToFPTest(MUX,41)@0 + 1
|
||||
assign vStagei_uid42_lzcShifterZ1_uid6_fxpToFPTest_s = vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
vStagei_uid42_lzcShifterZ1_uid6_fxpToFPTest_q <= 32'b0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
unique case (vStagei_uid42_lzcShifterZ1_uid6_fxpToFPTest_s)
|
||||
1'b0 : vStagei_uid42_lzcShifterZ1_uid6_fxpToFPTest_q <= a;
|
||||
1'b1 : vStagei_uid42_lzcShifterZ1_uid6_fxpToFPTest_q <= zs_uid38_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
default : vStagei_uid42_lzcShifterZ1_uid6_fxpToFPTest_q <= 32'b0;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
// vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest(LOGICAL,44)@1
|
||||
assign vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest_q = rVStage_uid44_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b == zs_uid43_lzcShifterZ1_uid6_fxpToFPTest_q ? 1'b1 : 1'b0;
|
||||
|
||||
// vStagei_uid49_lzcShifterZ1_uid6_fxpToFPTest(MUX,48)@1 + 1
|
||||
assign vStagei_uid49_lzcShifterZ1_uid6_fxpToFPTest_s = vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
vStagei_uid49_lzcShifterZ1_uid6_fxpToFPTest_q <= 32'b0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
unique case (vStagei_uid49_lzcShifterZ1_uid6_fxpToFPTest_s)
|
||||
1'b0 : vStagei_uid49_lzcShifterZ1_uid6_fxpToFPTest_q <= vStagei_uid42_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
1'b1 : vStagei_uid49_lzcShifterZ1_uid6_fxpToFPTest_q <= cStage_uid48_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
default : vStagei_uid49_lzcShifterZ1_uid6_fxpToFPTest_q <= 32'b0;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
// vCount_uid52_lzcShifterZ1_uid6_fxpToFPTest(LOGICAL,51)@2
|
||||
assign vCount_uid52_lzcShifterZ1_uid6_fxpToFPTest_q = rVStage_uid51_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b == expZ_uid33_fxpToFPTest_q ? 1'b1 : 1'b0;
|
||||
|
||||
// vStagei_uid56_lzcShifterZ1_uid6_fxpToFPTest(MUX,55)@2 + 1
|
||||
assign vStagei_uid56_lzcShifterZ1_uid6_fxpToFPTest_s = vCount_uid52_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
vStagei_uid56_lzcShifterZ1_uid6_fxpToFPTest_q <= 32'b0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
unique case (vStagei_uid56_lzcShifterZ1_uid6_fxpToFPTest_s)
|
||||
1'b0 : vStagei_uid56_lzcShifterZ1_uid6_fxpToFPTest_q <= vStagei_uid49_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
1'b1 : vStagei_uid56_lzcShifterZ1_uid6_fxpToFPTest_q <= cStage_uid55_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
default : vStagei_uid56_lzcShifterZ1_uid6_fxpToFPTest_q <= 32'b0;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
// vCount_uid59_lzcShifterZ1_uid6_fxpToFPTest(LOGICAL,58)@3
|
||||
assign vCount_uid59_lzcShifterZ1_uid6_fxpToFPTest_q = rVStage_uid58_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b == zs_uid57_lzcShifterZ1_uid6_fxpToFPTest_q ? 1'b1 : 1'b0;
|
||||
|
||||
// vStagei_uid63_lzcShifterZ1_uid6_fxpToFPTest(MUX,62)@3 + 1
|
||||
assign vStagei_uid63_lzcShifterZ1_uid6_fxpToFPTest_s = vCount_uid59_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
vStagei_uid63_lzcShifterZ1_uid6_fxpToFPTest_q <= 32'b0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
unique case (vStagei_uid63_lzcShifterZ1_uid6_fxpToFPTest_s)
|
||||
1'b0 : vStagei_uid63_lzcShifterZ1_uid6_fxpToFPTest_q <= vStagei_uid56_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
1'b1 : vStagei_uid63_lzcShifterZ1_uid6_fxpToFPTest_q <= cStage_uid62_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
default : vStagei_uid63_lzcShifterZ1_uid6_fxpToFPTest_q <= 32'b0;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
// vCount_uid66_lzcShifterZ1_uid6_fxpToFPTest(LOGICAL,65)@4
|
||||
assign vCount_uid66_lzcShifterZ1_uid6_fxpToFPTest_q = rVStage_uid65_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b == zs_uid64_lzcShifterZ1_uid6_fxpToFPTest_q ? 1'b1 : 1'b0;
|
||||
|
||||
// vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest(MUX,69)@4
|
||||
assign vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest_s = vCount_uid66_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
always @(vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest_s or en or vStagei_uid63_lzcShifterZ1_uid6_fxpToFPTest_q or cStage_uid69_lzcShifterZ1_uid6_fxpToFPTest_q)
|
||||
begin
|
||||
unique case (vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest_s)
|
||||
1'b0 : vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest_q = vStagei_uid63_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
1'b1 : vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest_q = cStage_uid69_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
default : vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest_q = 32'b0;
|
||||
endcase
|
||||
end
|
||||
|
||||
// vCount_uid73_lzcShifterZ1_uid6_fxpToFPTest(LOGICAL,72)@4
|
||||
assign vCount_uid73_lzcShifterZ1_uid6_fxpToFPTest_q = rVStage_uid72_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b == GND_q ? 1'b1 : 1'b0;
|
||||
|
||||
// vStagei_uid77_lzcShifterZ1_uid6_fxpToFPTest(MUX,76)@4
|
||||
assign vStagei_uid77_lzcShifterZ1_uid6_fxpToFPTest_s = vCount_uid73_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
always @(vStagei_uid77_lzcShifterZ1_uid6_fxpToFPTest_s or en or vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest_q or cStage_uid76_lzcShifterZ1_uid6_fxpToFPTest_q)
|
||||
begin
|
||||
unique case (vStagei_uid77_lzcShifterZ1_uid6_fxpToFPTest_s)
|
||||
1'b0 : vStagei_uid77_lzcShifterZ1_uid6_fxpToFPTest_q = vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
1'b1 : vStagei_uid77_lzcShifterZ1_uid6_fxpToFPTest_q = cStage_uid76_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
default : vStagei_uid77_lzcShifterZ1_uid6_fxpToFPTest_q = 32'b0;
|
||||
endcase
|
||||
end
|
||||
|
||||
// fracRnd_uid11_fxpToFPTest_merged_bit_select(BITSELECT,90)@4
|
||||
assign fracRnd_uid11_fxpToFPTest_merged_bit_select_in = vStagei_uid77_lzcShifterZ1_uid6_fxpToFPTest_q[30:0];
|
||||
assign fracRnd_uid11_fxpToFPTest_merged_bit_select_b = fracRnd_uid11_fxpToFPTest_merged_bit_select_in[30:7];
|
||||
assign fracRnd_uid11_fxpToFPTest_merged_bit_select_c = fracRnd_uid11_fxpToFPTest_merged_bit_select_in[6:0];
|
||||
|
||||
// redist1_fracRnd_uid11_fxpToFPTest_merged_bit_select_c_1(DELAY,92)
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
redist1_fracRnd_uid11_fxpToFPTest_merged_bit_select_c_1_q <= '0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
redist1_fracRnd_uid11_fxpToFPTest_merged_bit_select_c_1_q <= fracRnd_uid11_fxpToFPTest_merged_bit_select_c;
|
||||
end
|
||||
end
|
||||
|
||||
// sticky_uid16_fxpToFPTest(LOGICAL,15)@5
|
||||
assign sticky_uid16_fxpToFPTest_q = redist1_fracRnd_uid11_fxpToFPTest_merged_bit_select_c_1_q != 7'b0000000 ? 1'b1 : 1'b0;
|
||||
|
||||
// nr_uid17_fxpToFPTest(LOGICAL,16)@5
|
||||
assign nr_uid17_fxpToFPTest_q = ~ (l_uid13_fxpToFPTest_merged_bit_select_c);
|
||||
|
||||
// maxCount_uid7_fxpToFPTest(CONSTANT,6)
|
||||
assign maxCount_uid7_fxpToFPTest_q = 6'b100000;
|
||||
|
||||
// redist6_vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q_4(DELAY,97)
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
redist6_vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q_4_delay_0 <= '0;
|
||||
redist6_vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q_4_delay_1 <= '0;
|
||||
redist6_vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q_4_delay_2 <= '0;
|
||||
redist6_vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q_4_q <= '0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
redist6_vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q_4_delay_0 <= vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
redist6_vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q_4_delay_1 <= redist6_vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q_4_delay_0;
|
||||
redist6_vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q_4_delay_2 <= redist6_vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q_4_delay_1;
|
||||
redist6_vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q_4_q <= redist6_vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q_4_delay_2;
|
||||
end
|
||||
end
|
||||
|
||||
// redist5_vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest_q_3(DELAY,96)
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
redist5_vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest_q_3_delay_0 <= '0;
|
||||
redist5_vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest_q_3_delay_1 <= '0;
|
||||
redist5_vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest_q_3_q <= '0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
redist5_vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest_q_3_delay_0 <= vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
redist5_vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest_q_3_delay_1 <= redist5_vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest_q_3_delay_0;
|
||||
redist5_vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest_q_3_q <= redist5_vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest_q_3_delay_1;
|
||||
end
|
||||
end
|
||||
|
||||
// redist4_vCount_uid52_lzcShifterZ1_uid6_fxpToFPTest_q_2(DELAY,95)
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
redist4_vCount_uid52_lzcShifterZ1_uid6_fxpToFPTest_q_2_delay_0 <= '0;
|
||||
redist4_vCount_uid52_lzcShifterZ1_uid6_fxpToFPTest_q_2_q <= '0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
redist4_vCount_uid52_lzcShifterZ1_uid6_fxpToFPTest_q_2_delay_0 <= vCount_uid52_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
redist4_vCount_uid52_lzcShifterZ1_uid6_fxpToFPTest_q_2_q <= redist4_vCount_uid52_lzcShifterZ1_uid6_fxpToFPTest_q_2_delay_0;
|
||||
end
|
||||
end
|
||||
|
||||
// redist3_vCount_uid59_lzcShifterZ1_uid6_fxpToFPTest_q_1(DELAY,94)
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
redist3_vCount_uid59_lzcShifterZ1_uid6_fxpToFPTest_q_1_q <= '0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
redist3_vCount_uid59_lzcShifterZ1_uid6_fxpToFPTest_q_1_q <= vCount_uid59_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
end
|
||||
end
|
||||
|
||||
// vCount_uid78_lzcShifterZ1_uid6_fxpToFPTest(BITJOIN,77)@4
|
||||
assign vCount_uid78_lzcShifterZ1_uid6_fxpToFPTest_q = {redist6_vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q_4_q, redist5_vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest_q_3_q, redist4_vCount_uid52_lzcShifterZ1_uid6_fxpToFPTest_q_2_q, redist3_vCount_uid59_lzcShifterZ1_uid6_fxpToFPTest_q_1_q, vCount_uid66_lzcShifterZ1_uid6_fxpToFPTest_q, vCount_uid73_lzcShifterZ1_uid6_fxpToFPTest_q};
|
||||
|
||||
// redist2_vCount_uid78_lzcShifterZ1_uid6_fxpToFPTest_q_1(DELAY,93)
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
redist2_vCount_uid78_lzcShifterZ1_uid6_fxpToFPTest_q_1_q <= '0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
redist2_vCount_uid78_lzcShifterZ1_uid6_fxpToFPTest_q_1_q <= vCount_uid78_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
end
|
||||
end
|
||||
|
||||
// vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest(COMPARE,79)@4 + 1
|
||||
assign vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest_a = {2'b00, maxCount_uid7_fxpToFPTest_q};
|
||||
assign vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest_b = {2'b00, vCount_uid78_lzcShifterZ1_uid6_fxpToFPTest_q};
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest_o <= 8'b0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest_o <= $unsigned(vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest_a) - $unsigned(vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest_b);
|
||||
end
|
||||
end
|
||||
assign vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest_c[0] = vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest_o[7];
|
||||
|
||||
// vCountFinal_uid82_lzcShifterZ1_uid6_fxpToFPTest(MUX,81)@5
|
||||
assign vCountFinal_uid82_lzcShifterZ1_uid6_fxpToFPTest_s = vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest_c;
|
||||
always @(vCountFinal_uid82_lzcShifterZ1_uid6_fxpToFPTest_s or en or redist2_vCount_uid78_lzcShifterZ1_uid6_fxpToFPTest_q_1_q or maxCount_uid7_fxpToFPTest_q)
|
||||
begin
|
||||
unique case (vCountFinal_uid82_lzcShifterZ1_uid6_fxpToFPTest_s)
|
||||
1'b0 : vCountFinal_uid82_lzcShifterZ1_uid6_fxpToFPTest_q = redist2_vCount_uid78_lzcShifterZ1_uid6_fxpToFPTest_q_1_q;
|
||||
1'b1 : vCountFinal_uid82_lzcShifterZ1_uid6_fxpToFPTest_q = maxCount_uid7_fxpToFPTest_q;
|
||||
default : vCountFinal_uid82_lzcShifterZ1_uid6_fxpToFPTest_q = 6'b0;
|
||||
endcase
|
||||
end
|
||||
|
||||
// msbIn_uid9_fxpToFPTest(CONSTANT,8)
|
||||
assign msbIn_uid9_fxpToFPTest_q = 8'b10011110;
|
||||
|
||||
// expPreRnd_uid10_fxpToFPTest(SUB,9)@5
|
||||
assign expPreRnd_uid10_fxpToFPTest_a = {1'b0, msbIn_uid9_fxpToFPTest_q};
|
||||
assign expPreRnd_uid10_fxpToFPTest_b = {3'b000, vCountFinal_uid82_lzcShifterZ1_uid6_fxpToFPTest_q};
|
||||
assign expPreRnd_uid10_fxpToFPTest_o = $unsigned(expPreRnd_uid10_fxpToFPTest_a) - $unsigned(expPreRnd_uid10_fxpToFPTest_b);
|
||||
assign expPreRnd_uid10_fxpToFPTest_q = expPreRnd_uid10_fxpToFPTest_o[8:0];
|
||||
|
||||
// redist0_fracRnd_uid11_fxpToFPTest_merged_bit_select_b_1(DELAY,91)
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
redist0_fracRnd_uid11_fxpToFPTest_merged_bit_select_b_1_q <= '0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
redist0_fracRnd_uid11_fxpToFPTest_merged_bit_select_b_1_q <= fracRnd_uid11_fxpToFPTest_merged_bit_select_b;
|
||||
end
|
||||
end
|
||||
|
||||
// expFracRnd_uid12_fxpToFPTest(BITJOIN,11)@5
|
||||
assign expFracRnd_uid12_fxpToFPTest_q = {expPreRnd_uid10_fxpToFPTest_q, redist0_fracRnd_uid11_fxpToFPTest_merged_bit_select_b_1_q};
|
||||
|
||||
// l_uid13_fxpToFPTest_merged_bit_select(BITSELECT,84)@5
|
||||
assign l_uid13_fxpToFPTest_merged_bit_select_in = expFracRnd_uid12_fxpToFPTest_q[1:0];
|
||||
assign l_uid13_fxpToFPTest_merged_bit_select_b = l_uid13_fxpToFPTest_merged_bit_select_in[1:1];
|
||||
assign l_uid13_fxpToFPTest_merged_bit_select_c = l_uid13_fxpToFPTest_merged_bit_select_in[0:0];
|
||||
|
||||
// rnd_uid18_fxpToFPTest(LOGICAL,17)@5 + 1
|
||||
assign rnd_uid18_fxpToFPTest_qi = l_uid13_fxpToFPTest_merged_bit_select_b | nr_uid17_fxpToFPTest_q | sticky_uid16_fxpToFPTest_q;
|
||||
dspba_delay_ver #( .width(1), .depth(1), .reset_kind("SYNC"), .phase(0), .modulus(1) )
|
||||
rnd_uid18_fxpToFPTest_delay ( .xin(rnd_uid18_fxpToFPTest_qi), .xout(rnd_uid18_fxpToFPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// redist9_expFracRnd_uid12_fxpToFPTest_q_1(DELAY,100)
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
redist9_expFracRnd_uid12_fxpToFPTest_q_1_q <= '0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
redist9_expFracRnd_uid12_fxpToFPTest_q_1_q <= expFracRnd_uid12_fxpToFPTest_q;
|
||||
end
|
||||
end
|
||||
|
||||
// expFracR_uid20_fxpToFPTest(ADD,19)@6
|
||||
assign expFracR_uid20_fxpToFPTest_a = {{2{redist9_expFracRnd_uid12_fxpToFPTest_q_1_q[32]}}, redist9_expFracRnd_uid12_fxpToFPTest_q_1_q};
|
||||
assign expFracR_uid20_fxpToFPTest_b = {34'b0000000000000000000000000000000000, rnd_uid18_fxpToFPTest_q};
|
||||
assign expFracR_uid20_fxpToFPTest_o = $signed(expFracR_uid20_fxpToFPTest_a) + $signed(expFracR_uid20_fxpToFPTest_b);
|
||||
assign expFracR_uid20_fxpToFPTest_q = expFracR_uid20_fxpToFPTest_o[33:0];
|
||||
|
||||
// expR_uid22_fxpToFPTest(BITSELECT,21)@6
|
||||
assign expR_uid22_fxpToFPTest_b = expFracR_uid20_fxpToFPTest_q[33:24];
|
||||
|
||||
// redist7_expR_uid22_fxpToFPTest_b_1(DELAY,98)
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
redist7_expR_uid22_fxpToFPTest_b_1_q <= '0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
redist7_expR_uid22_fxpToFPTest_b_1_q <= expR_uid22_fxpToFPTest_b;
|
||||
end
|
||||
end
|
||||
|
||||
// expR_uid34_fxpToFPTest(BITSELECT,33)@7
|
||||
assign expR_uid34_fxpToFPTest_in = redist7_expR_uid22_fxpToFPTest_b_1_q[7:0];
|
||||
assign expR_uid34_fxpToFPTest_b = expR_uid34_fxpToFPTest_in[7:0];
|
||||
|
||||
// ovf_uid25_fxpToFPTest(COMPARE,24)@7
|
||||
assign ovf_uid25_fxpToFPTest_a = {{2{redist7_expR_uid22_fxpToFPTest_b_1_q[9]}}, redist7_expR_uid22_fxpToFPTest_b_1_q};
|
||||
assign ovf_uid25_fxpToFPTest_b = {4'b0000, expInf_uid24_fxpToFPTest_q};
|
||||
assign ovf_uid25_fxpToFPTest_o = $signed(ovf_uid25_fxpToFPTest_a) - $signed(ovf_uid25_fxpToFPTest_b);
|
||||
assign ovf_uid25_fxpToFPTest_n[0] = ~ (ovf_uid25_fxpToFPTest_o[11]);
|
||||
|
||||
// inIsZero_uid8_fxpToFPTest(LOGICAL,7)@5 + 1
|
||||
assign inIsZero_uid8_fxpToFPTest_qi = vCountFinal_uid82_lzcShifterZ1_uid6_fxpToFPTest_q == maxCount_uid7_fxpToFPTest_q ? 1'b1 : 1'b0;
|
||||
dspba_delay_ver #( .width(1), .depth(1), .reset_kind("SYNC"), .phase(0), .modulus(1) )
|
||||
inIsZero_uid8_fxpToFPTest_delay ( .xin(inIsZero_uid8_fxpToFPTest_qi), .xout(inIsZero_uid8_fxpToFPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// redist10_inIsZero_uid8_fxpToFPTest_q_2(DELAY,101)
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
redist10_inIsZero_uid8_fxpToFPTest_q_2_q <= '0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
redist10_inIsZero_uid8_fxpToFPTest_q_2_q <= inIsZero_uid8_fxpToFPTest_q;
|
||||
end
|
||||
end
|
||||
|
||||
// udf_uid23_fxpToFPTest(COMPARE,22)@7
|
||||
assign udf_uid23_fxpToFPTest_a = {11'b00000000000, GND_q};
|
||||
assign udf_uid23_fxpToFPTest_b = {{2{redist7_expR_uid22_fxpToFPTest_b_1_q[9]}}, redist7_expR_uid22_fxpToFPTest_b_1_q};
|
||||
assign udf_uid23_fxpToFPTest_o = $signed(udf_uid23_fxpToFPTest_a) - $signed(udf_uid23_fxpToFPTest_b);
|
||||
assign udf_uid23_fxpToFPTest_n[0] = ~ (udf_uid23_fxpToFPTest_o[11]);
|
||||
|
||||
// udfOrInZero_uid29_fxpToFPTest(LOGICAL,28)@7
|
||||
assign udfOrInZero_uid29_fxpToFPTest_q = udf_uid23_fxpToFPTest_n | redist10_inIsZero_uid8_fxpToFPTest_q_2_q;
|
||||
|
||||
// excSelector_uid30_fxpToFPTest(BITJOIN,29)@7
|
||||
assign excSelector_uid30_fxpToFPTest_q = {ovf_uid25_fxpToFPTest_n, udfOrInZero_uid29_fxpToFPTest_q};
|
||||
|
||||
// expRPostExc_uid35_fxpToFPTest(MUX,34)@7
|
||||
assign expRPostExc_uid35_fxpToFPTest_s = excSelector_uid30_fxpToFPTest_q;
|
||||
always @(expRPostExc_uid35_fxpToFPTest_s or en or expR_uid34_fxpToFPTest_b or expZ_uid33_fxpToFPTest_q or expInf_uid24_fxpToFPTest_q)
|
||||
begin
|
||||
unique case (expRPostExc_uid35_fxpToFPTest_s)
|
||||
2'b00 : expRPostExc_uid35_fxpToFPTest_q = expR_uid34_fxpToFPTest_b;
|
||||
2'b01 : expRPostExc_uid35_fxpToFPTest_q = expZ_uid33_fxpToFPTest_q;
|
||||
2'b10 : expRPostExc_uid35_fxpToFPTest_q = expInf_uid24_fxpToFPTest_q;
|
||||
2'b11 : expRPostExc_uid35_fxpToFPTest_q = expInf_uid24_fxpToFPTest_q;
|
||||
default : expRPostExc_uid35_fxpToFPTest_q = 8'b0;
|
||||
endcase
|
||||
end
|
||||
|
||||
// fracZ_uid27_fxpToFPTest(CONSTANT,26)
|
||||
assign fracZ_uid27_fxpToFPTest_q = 23'b00000000000000000000000;
|
||||
|
||||
// fracR_uid21_fxpToFPTest(BITSELECT,20)@6
|
||||
assign fracR_uid21_fxpToFPTest_in = expFracR_uid20_fxpToFPTest_q[23:0];
|
||||
assign fracR_uid21_fxpToFPTest_b = fracR_uid21_fxpToFPTest_in[23:1];
|
||||
|
||||
// redist8_fracR_uid21_fxpToFPTest_b_1(DELAY,99)
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
redist8_fracR_uid21_fxpToFPTest_b_1_q <= '0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
redist8_fracR_uid21_fxpToFPTest_b_1_q <= fracR_uid21_fxpToFPTest_b;
|
||||
end
|
||||
end
|
||||
|
||||
// excSelector_uid26_fxpToFPTest(LOGICAL,25)@7
|
||||
assign excSelector_uid26_fxpToFPTest_q = redist10_inIsZero_uid8_fxpToFPTest_q_2_q | ovf_uid25_fxpToFPTest_n | udf_uid23_fxpToFPTest_n;
|
||||
|
||||
// fracRPostExc_uid28_fxpToFPTest(MUX,27)@7
|
||||
assign fracRPostExc_uid28_fxpToFPTest_s = excSelector_uid26_fxpToFPTest_q;
|
||||
always @(fracRPostExc_uid28_fxpToFPTest_s or en or redist8_fracR_uid21_fxpToFPTest_b_1_q or fracZ_uid27_fxpToFPTest_q)
|
||||
begin
|
||||
unique case (fracRPostExc_uid28_fxpToFPTest_s)
|
||||
1'b0 : fracRPostExc_uid28_fxpToFPTest_q = redist8_fracR_uid21_fxpToFPTest_b_1_q;
|
||||
1'b1 : fracRPostExc_uid28_fxpToFPTest_q = fracZ_uid27_fxpToFPTest_q;
|
||||
default : fracRPostExc_uid28_fxpToFPTest_q = 23'b0;
|
||||
endcase
|
||||
end
|
||||
|
||||
// outRes_uid36_fxpToFPTest(BITJOIN,35)@7
|
||||
assign outRes_uid36_fxpToFPTest_q = {GND_q, expRPostExc_uid35_fxpToFPTest_q, fracRPostExc_uid28_fxpToFPTest_q};
|
||||
|
||||
// xOut(GPOUT,4)@7
|
||||
assign q = outRes_uid36_fxpToFPTest_q;
|
||||
|
||||
endmodule
|
||||
98
hw/rtl/fp_cores/altera/stratix10/dspba_delay_ver.sv
Normal file
98
hw/rtl/fp_cores/altera/stratix10/dspba_delay_ver.sv
Normal file
|
|
@ -0,0 +1,98 @@
|
|||
// Legal Notice: Copyright 2017 Intel Corporation. All rights reserved.
|
||||
// Your use of Intel Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files any of the foregoing device programming or simulation files), and
|
||||
// any associated documentation or information are expressly subject to the
|
||||
// terms and conditions of the Intel FPGA Software License Agreement,
|
||||
// Intel MegaCore Function License Agreement, or other applicable license
|
||||
// agreement, including, without limitation, that your use is for the sole
|
||||
// purpose of programming logic devices manufactured by Intel and sold by
|
||||
// Intel or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
module dspba_delay_ver
|
||||
#(
|
||||
parameter width = 8,
|
||||
parameter depth = 1,
|
||||
parameter reset_high = 1'b1,
|
||||
parameter reset_kind = "ASYNC",
|
||||
parameter phase = 0,
|
||||
parameter modulus = 1
|
||||
) (
|
||||
input clk,
|
||||
input aclr,
|
||||
input ena,
|
||||
input [width-1:0] xin,
|
||||
output [width-1:0] xout
|
||||
);
|
||||
|
||||
wire reset;
|
||||
reg [width-1:0] delays [depth-1:0];
|
||||
|
||||
assign reset = aclr ^ reset_high;
|
||||
|
||||
generate
|
||||
if (depth > 0)
|
||||
begin
|
||||
genvar i;
|
||||
for (i = 0; i < depth; ++i)
|
||||
begin : delay_block
|
||||
if ((reset_kind == "ASYNC") && (0 == (phase + i) % modulus))
|
||||
begin : async_reset
|
||||
always @ (posedge clk or negedge reset)
|
||||
begin: a
|
||||
if (!reset) begin
|
||||
delays[i] <= 0;
|
||||
end else begin
|
||||
if (ena) begin
|
||||
if (i > 0) begin
|
||||
delays[i] <= delays[i - 1];
|
||||
end else begin
|
||||
delays[i] <= xin;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
if ((reset_kind == "SYNC") && (0 == (phase + i) % modulus))
|
||||
begin : sync_reset
|
||||
always @ (posedge clk)
|
||||
begin: a
|
||||
if (!reset) begin
|
||||
delays[i] <= 0;
|
||||
end else begin
|
||||
if (ena) begin
|
||||
if (i > 0) begin
|
||||
delays[i] <= delays[i - 1];
|
||||
end else begin
|
||||
delays[i] <= xin;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
if ((reset_kind == "NONE") || (0 != (phase + i) % modulus))
|
||||
begin : no_reset
|
||||
always @ (posedge clk)
|
||||
begin: a
|
||||
if (ena) begin
|
||||
if (i > 0) begin
|
||||
delays[i] <= delays[i - 1];
|
||||
end else begin
|
||||
delays[i] <= xin;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
assign xout = delays[depth - 1];
|
||||
end else begin
|
||||
assign xout = xin;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
|
|
@ -1,7 +1,7 @@
|
|||
PROJECT = Core
|
||||
TOP_LEVEL_ENTITY = VX_core
|
||||
SRC_FILE = VX_core.v
|
||||
FPU_INCLUDE = ../../../rtl/fp_cores;../../../rtl/fp_cores/altera;../../../rtl/fp_cores/fpnew/src;../../../rtl/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl;../../../rtl/fp_cores/fpnew/src/common_cells/include;../../../rtl/fp_cores/fpnew/src/common_cells/src
|
||||
FPU_INCLUDE = ../../../rtl/fp_cores;../../../rtl/fp_cores/altera/arria10;../../../rtl/fp_cores/fpnew/src;../../../rtl/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl;../../../rtl/fp_cores/fpnew/src/common_cells/include;../../../rtl/fp_cores/fpnew/src/common_cells/src
|
||||
RTL_INCLUDE = $(FPU_INCLUDE);../../../rtl;../../../rtl/libs;../../../rtl/interfaces;../../../rtl/cache
|
||||
PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf
|
||||
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
PROJECT = Core
|
||||
TOP_LEVEL_ENTITY = VX_core
|
||||
SRC_FILE = VX_core.v
|
||||
FPU_INCLUDE = ../../../rtl/fp_cores;../../../rtl/fp_cores/altera;../../../rtl/fp_cores/fpnew/src;../../../rtl/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl;../../../rtl/fp_cores/fpnew/src/common_cells/include;../../../rtl/fp_cores/fpnew/src/common_cells/src
|
||||
FPU_INCLUDE = ../../../rtl/fp_cores;../../../rtl/fp_cores/altera/arria10;../../../rtl/fp_cores/fpnew/src;../../../rtl/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl;../../../rtl/fp_cores/fpnew/src/common_cells/include;../../../rtl/fp_cores/fpnew/src/common_cells/src
|
||||
RTL_INCLUDE = $(FPU_INCLUDE);../../../rtl;../../../rtl/libs;../../../rtl/interfaces;../../../rtl/cache
|
||||
PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf
|
||||
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
PROJECT = VX_pipeline
|
||||
TOP_LEVEL_ENTITY = VX_pipeline
|
||||
SRC_FILE = VX_pipeline.v
|
||||
FPU_INCLUDE = ../../../rtl/fp_cores;../../../rtl/fp_cores/altera;../../../rtl/fp_cores/fpnew/src;../../../rtl/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl;../../../rtl/fp_cores/fpnew/src/common_cells/include;../../../rtl/fp_cores/fpnew/src/common_cells/src
|
||||
FPU_INCLUDE = ../../../rtl/fp_cores;../../../rtl/fp_cores/altera/arria10;../../../rtl/fp_cores/fpnew/src;../../../rtl/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl;../../../rtl/fp_cores/fpnew/src/common_cells/include;../../../rtl/fp_cores/fpnew/src/common_cells/src
|
||||
RTL_INCLUDE = $(FPU_INCLUDE);../../../rtl;../../../rtl/libs;../../../rtl/interfaces
|
||||
PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf
|
||||
|
||||
|
|
|
|||
|
|
@ -59,6 +59,19 @@ set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
|
|||
set_global_assignment -name POWER_USE_TA_VALUE 65
|
||||
set_global_assignment -name SEED 1
|
||||
|
||||
switch $opts(family) {
|
||||
"Arria 10" {
|
||||
set_global_assignment -name VERILOG_MACRO ALTERA_A10
|
||||
}
|
||||
"Stratix 10" {
|
||||
set_global_assignment -name VERILOG_MACRO ALTERA_S10
|
||||
}
|
||||
default {
|
||||
puts stderr "Invalid device family"
|
||||
exit 1
|
||||
}
|
||||
}
|
||||
|
||||
set idx 0
|
||||
foreach arg $q_args_orig {
|
||||
incr idx
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
PROJECT = vortex_afu
|
||||
TOP_LEVEL_ENTITY = vortex_afu
|
||||
SRC_FILE = vortex_afu.sv
|
||||
FPU_INCLUDE = ../../../rtl/fp_cores;../../../rtl/fp_cores/altera;../../../rtl/fp_cores/fpnew/src;../../../rtl/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl;../../../rtl/fp_cores/fpnew/src/common_cells/include;../../../rtl/fp_cores/fpnew/src/common_cells/src
|
||||
FPU_INCLUDE = ../../../rtl/fp_cores;../../../rtl/fp_cores/altera/arria10;../../../rtl/fp_cores/fpnew/src;../../../rtl/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl;../../../rtl/fp_cores/fpnew/src/common_cells/include;../../../rtl/fp_cores/fpnew/src/common_cells/src
|
||||
RTL_INCLUDE = $(FPU_INCLUDE);../../../rtl;../../../rtl/libs;../../../rtl/interfaces;../../../rtl/cache;../../../rtl/afu;../../../rtl/afu/ccip
|
||||
PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf
|
||||
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
PROJECT = vortex_afu
|
||||
TOP_LEVEL_ENTITY = vortex_afu
|
||||
SRC_FILE = vortex_afu.sv
|
||||
FPU_INCLUDE = ../../../rtl/fp_cores;../../../rtl/fp_cores/altera;../../../rtl/fp_cores/fpnew/src;../../../rtl/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl;../../../rtl/fp_cores/fpnew/src/common_cells/include;../../../rtl/fp_cores/fpnew/src/common_cells/src
|
||||
FPU_INCLUDE = ../../../rtl/fp_cores;../../../rtl/fp_cores/altera/arria10;../../../rtl/fp_cores/fpnew/src;../../../rtl/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl;../../../rtl/fp_cores/fpnew/src/common_cells/include;../../../rtl/fp_cores/fpnew/src/common_cells/src
|
||||
RTL_INCLUDE = $(FPU_INCLUDE);../../../rtl;../../../rtl/libs;../../../rtl/interfaces;../../../rtl/cache;../../../rtl/afu;../../../rtl/afu/ccip
|
||||
PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf
|
||||
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
PROJECT = vortex_afu
|
||||
TOP_LEVEL_ENTITY = vortex_afu
|
||||
SRC_FILE = vortex_afu.sv
|
||||
FPU_INCLUDE = ../../../rtl/fp_cores;../../../rtl/fp_cores/altera;../../../rtl/fp_cores/fpnew/src;../../../rtl/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl;../../../rtl/fp_cores/fpnew/src/common_cells/include;../../../rtl/fp_cores/fpnew/src/common_cells/src
|
||||
FPU_INCLUDE = ../../../rtl/fp_cores;../../../rtl/fp_cores/altera/arria10;../../../rtl/fp_cores/fpnew/src;../../../rtl/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl;../../../rtl/fp_cores/fpnew/src/common_cells/include;../../../rtl/fp_cores/fpnew/src/common_cells/src
|
||||
RTL_INCLUDE = $(FPU_INCLUDE);../../../rtl;../../../rtl/libs;../../../rtl/interfaces;../../../rtl/cache;../../../rtl/afu;../../../rtl/afu/ccip
|
||||
PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf
|
||||
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
PROJECT = vortex_afu
|
||||
TOP_LEVEL_ENTITY = vortex_afu
|
||||
SRC_FILE = vortex_afu.sv
|
||||
FPU_INCLUDE = ../../../rtl/fp_cores;../../../rtl/fp_cores/altera;../../../rtl/fp_cores/fpnew/src;../../../rtl/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl;../../../rtl/fp_cores/fpnew/src/common_cells/include;../../../rtl/fp_cores/fpnew/src/common_cells/src
|
||||
FPU_INCLUDE = ../../../rtl/fp_cores;../../../rtl/fp_cores/altera/stratix10;../../../rtl/fp_cores/fpnew/src;../../../rtl/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl;../../../rtl/fp_cores/fpnew/src/common_cells/include;../../../rtl/fp_cores/fpnew/src/common_cells/src
|
||||
RTL_INCLUDE = $(FPU_INCLUDE);../../../rtl;../../../rtl/libs;../../../rtl/interfaces;../../../rtl/cache;../../../rtl/afu;../../../rtl/afu/ccip
|
||||
PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf
|
||||
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
PROJECT = Vortex
|
||||
TOP_LEVEL_ENTITY = Vortex
|
||||
SRC_FILE = Vortex.v
|
||||
FPU_INCLUDE = ../../../rtl/fp_cores;../../../rtl/fp_cores/altera;../../../rtl/fp_cores/fpnew/src;../../../rtl/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl;../../../rtl/fp_cores/fpnew/src/common_cells/include;../../../rtl/fp_cores/fpnew/src/common_cells/src
|
||||
FPU_INCLUDE = ../../../rtl/fp_cores;../../../rtl/fp_cores/altera/arria10;../../../rtl/fp_cores/fpnew/src;../../../rtl/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl;../../../rtl/fp_cores/fpnew/src/common_cells/include;../../../rtl/fp_cores/fpnew/src/common_cells/src
|
||||
RTL_INCLUDE = $(FPU_INCLUDE);../../../rtl;../../../rtl/libs;../../../rtl/interfaces;../../../rtl/cache
|
||||
PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue