minor update

hw/rtl/VX_define.vh

@@ -395,11 +395,10 @@
     if (latency != 0) begin \
         VX_pipe_register #( \
             .DATAW  (1 + `VX_DCR_ADDR_WIDTH + `VX_DCR_DATA_WIDTH), \
-            .RESETW (1 + `VX_DCR_ADDR_WIDTH + `VX_DCR_DATA_WIDTH), \
             .DEPTH  (latency) \
         ) pipe_reg ( \
             .clk      (clk), \
-            .reset    (reset), \
+            .reset    (1'b0), \
             .enable   (1'b1), \
             .data_in  ({src.write_valid && ena, src.write_addr, src.write_data}), \
             .data_out ({dst.write_valid, dst.write_addr, dst.write_data}) \

hw/rtl/cache/VX_cache.sv

@@ -310,7 +310,7 @@ module VX_cache import VX_gpu_pkg::*; #(
     end
 
     for (genvar i = 0; i < NUM_REQS; ++i) begin : g_core_req_bid
-        if (NUM_BANKS > 1) begin : g_multibank
+        if (NUM_BANKS > 1) begin : g_multibanks
             assign core_req_bid[i] = core_req_addr[i][WORD_SEL_BITS +: BANK_SEL_BITS];
         end else begin : g_singlebank
             assign core_req_bid[i] = '0;
@@ -448,7 +448,7 @@ module VX_cache import VX_gpu_pkg::*; #(
 
         if (NUM_BANKS == 1) begin : g_per_bank_mem_req_addr_multibanks
             assign per_bank_mem_req_addr[bank_id] = curr_bank_mem_req_addr;
-        end else begin : g_per_bank_mem_req_addr_one_bank
+        end else begin : g_per_bank_mem_req_addr_singlebank
             assign per_bank_mem_req_addr[bank_id] = `CS_LINE_TO_MEM_ADDR(curr_bank_mem_req_addr, bank_id);
         end
     end
@@ -521,7 +521,7 @@ module VX_cache import VX_gpu_pkg::*; #(
     if (NUM_BANKS > 1) begin : g_mem_req_tag_multibanks
         wire [`CS_BANK_SEL_BITS-1:0] mem_req_bank_id = `CS_MEM_ADDR_TO_BANK_ID(mem_req_addr);
         assign mem_req_tag = MEM_TAG_WIDTH'({bank_mem_req_tag, mem_req_bank_id});
-    end else begin : g_mem_req_tag_one_bank
+    end else begin : g_mem_req_tag
         assign mem_req_tag = MEM_TAG_WIDTH'(bank_mem_req_tag);
     end
 

hw/rtl/cache/VX_cache_bypass.sv

@@ -268,6 +268,7 @@ module VX_cache_bypass #(
     for (genvar i = 0; i < NUM_REQS; ++i) begin : g_core_rsp_in_valid
         assign core_rsp_in_valid[i] = core_bus_out_if[i].rsp_valid || (is_mem_rsp_nc && rsp_idx == REQ_SEL_WIDTH'(i));
     end
+    
     for (genvar i = 0; i < NUM_REQS; ++i) begin : g_core_rsp_in_ready
         assign core_bus_out_if[i].rsp_ready = core_rsp_in_ready[i];
     end

hw/rtl/cache/VX_cache_data.sv

@@ -76,13 +76,16 @@ module VX_cache_data #(
     wire [`LOG2UP(NUM_WAYS)-1:0] way_idx;
 
     if (WRITEBACK) begin : g_dirty_data
-        wire [NUM_WAYS-1:0][`CS_WORDS_PER_LINE-1:0][`CS_WORD_WIDTH-1:0] flipped_rdata;
-        for (genvar i = 0; i < `CS_WORDS_PER_LINE; ++i) begin : g_flipped_rdata
-            for (genvar j = 0; j < NUM_WAYS; ++j) begin : g_j
-                assign flipped_rdata[j][i] = line_rdata[i][j];
-            end
-        end
-        assign dirty_data = flipped_rdata[way_idx];
+        wire [NUM_WAYS-1:0][`CS_WORDS_PER_LINE-1:0][`CS_WORD_WIDTH-1:0] transposed_rdata;
+        VX_transpose #(
+            .DATAW (`CS_WORD_WIDTH),
+            .N (`CS_WORDS_PER_LINE),
+            .M (NUM_WAYS)
+        ) transpose (
+            .data_in  (line_rdata),
+            .data_out (transposed_rdata)
+        );
+        assign dirty_data = transposed_rdata[way_idx];
     end else begin : g_dirty_data_0
         assign dirty_data = '0;
     end

hw/rtl/core/VX_operands.sv

@@ -90,9 +90,9 @@ module VX_operands import VX_gpu_pkg::*; #(
     end
 
     for (genvar i = 0; i < NUM_SRC_OPDS; ++i) begin : g_req_bank_idx
-        if (NUM_BANKS != 1) begin : g_banks
+        if (NUM_BANKS != 1) begin : g_multibanks
             assign req_bank_idx[i] = src_opds[i][BANK_SEL_BITS-1:0];
-        end else begin : g_1bank
+        end else begin : g_singlebank
             assign req_bank_idx[i] = '0;
         end
     end
@@ -250,10 +250,10 @@ module VX_operands import VX_gpu_pkg::*; #(
 
     for (genvar b = 0; b < NUM_BANKS; ++b) begin : g_gpr_rams
         wire gpr_wr_enabled;
-        if (BANK_SEL_BITS != 0) begin : g_gpr_wr_enabled
+        if (BANK_SEL_BITS != 0) begin : g_gpr_wr_enabled_multibanks
             assign gpr_wr_enabled = writeback_if.valid
                                  && (gpr_wr_bank_idx == BANK_SEL_BITS'(b));
-        end else begin : g_gpr_wr_enabled_1bank
+        end else begin : g_gpr_wr_enabled
             assign gpr_wr_enabled = writeback_if.valid;
         end
 

hw/rtl/libs/VX_transpose.sv

@@ -15,11 +15,12 @@
 
 `TRACING_OFF
 module VX_transpose #(
+    parameter DATAW = 1,
     parameter N = 1,
     parameter M = 1
 ) (
-    input wire [N-1:0][M-1:0] data_in,
-    output wire [M-1:0][N-1:0] data_out
+    input wire [N-1:0][M-1:0][DATAW-1:0] data_in,
+    output wire [M-1:0][N-1:0][DATAW-1:0] data_out
 );
     for (genvar i = 0; i < N; ++i) begin : g_i
         for (genvar j = 0; j < M; ++j) begin : g_j