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cache area optimization by disabling BRAM read-during-write bypassing for tag/data stores

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This commit is contained in:
Blaise Tine 2021-08-26 12:27:38 -07:00
parent 74a45e2772
commit 26e94dde44
5 changed files with 23 additions and 10 deletions
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3
hw/rtl/cache/VX_bank.v vendored
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@ -161,6 +161,8 @@ module VX_bank #(
wire mreq_alm_full;
wire creq_fire = creq_valid && creq_ready;
wire fill_in_st0 = valid_st0 && is_fill_st0;
// determine which queue to pop next in priority order
wire mshr_grant = 1;
@ -172,6 +174,7 @@ module VX_bank #(
wire creq_grant = !mshr_enable && !mrsq_enable && !flush_enable;
wire mshr_ready = mshr_grant
&& !fill_in_st0 // prevent tag read-during-write with fill
&& !crsq_stall; // ensure core response ready
assign mem_rsp_ready = mrsq_grant

7
hw/rtl/cache/VX_data_access.v vendored
View file

@ -63,9 +63,10 @@ module VX_data_access #(
end
VX_sp_ram #(
.DATAW (CACHE_LINE_SIZE * 8),
.SIZE (`LINES_PER_BANK),
.BYTEENW (BYTEENW)
.DATAW (CACHE_LINE_SIZE * 8),
.SIZE (`LINES_PER_BANK),
.BYTEENW (BYTEENW),
.NO_RWCHECK (1)
) data_store (
.clk (clk),
.addr (line_addr),

7
hw/rtl/cache/VX_shared_mem.v vendored
View file

@ -171,9 +171,10 @@ module VX_shared_mem #(
&& creq_out_fire;
VX_sp_ram #(
.DATAW (`WORD_WIDTH),
.SIZE (`LINES_PER_BANK),
.BYTEENW (WORD_SIZE)
.DATAW (`WORD_WIDTH),
.SIZE (`LINES_PER_BANK),
.BYTEENW (WORD_SIZE),
.NO_RWCHECK (1)
) data_store (
.clk (clk),
.addr (per_bank_core_req_addr[i]),

9
hw/rtl/cache/VX_tag_access.v vendored
View file

@ -46,10 +46,11 @@ module VX_tag_access #(
wire [`LINE_SELECT_BITS-1:0] line_addr = addr [`LINE_SELECT_BITS-1:0];
VX_sp_ram #(
.DATAW(`TAG_SELECT_BITS + 1),
.SIZE(`LINES_PER_BANK),
.INIT_ENABLE(1),
.INIT_VALUE(0)
.DATAW (`TAG_SELECT_BITS + 1),
.SIZE (`LINES_PER_BANK),
.INIT_ENABLE (1),
.INIT_VALUE (0),
.NO_RWCHECK (1)
) tag_store (
.clk( clk),
.addr (line_addr),

7
hw/syn/opae/fpga_prog.sh Executable file
View file

@ -0,0 +1,7 @@
#!/bin/bash
# FPGA programming
# first argument is the bitstream
echo "fpgaconf --bus 0xaf $1"
fpgaconf --bus 0xaf $1