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minor update

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This commit is contained in:
Blaise Tine 2024-09-25 19:11:40 -07:00
parent 4f11278d2c
commit 27543e240e
4 changed files with 26 additions and 40 deletions
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27
hw/rtl/afu/opae/vortex_afu.sv
View file

@ -1012,11 +1012,6 @@ module vortex_afu import ccip_if_pkg::*; import local_mem_cfg_pkg::*; import VX_
// SCOPE //////////////////////////////////////////////////////////////////////
`ifdef DBG_SCOPE_AFU
wire avs_write_fire = avs_write[0] && ~avs_waitrequest[0];
wire avs_read_fire = avs_read[0] && ~avs_waitrequest[0];
wire vx_mem_req_fire = vx_mem_req_valid && vx_mem_req_ready;
wire vx_mem_rsp_fire = vx_mem_rsp_valid && vx_mem_rsp_ready;
reg [STATE_WIDTH-1:0] state_prev;
always @(posedge clk) begin
state_prev <= state;
@ -1028,12 +1023,15 @@ module vortex_afu import ccip_if_pkg::*; import local_mem_cfg_pkg::*; import VX_
`SCOPE_TAP (0, 0, {
vx_reset,
vx_busy,
vx_mem_req_fire,
vx_mem_rsp_fire,
vx_mem_req_valid,
vx_mem_req_ready,
vx_mem_rsp_valid,
vx_mem_rsp_ready,
vx_dcr_wr_valid,
state_changed,
avs_write_fire,
avs_read_fire,
avs_read[0],
avs_write[0],
avs_waitrequest[0],
avs_waitrequest[0],
avs_readdatavalid[0],
cp2af_sRxPort.c0.mmioRdValid,
@ -1044,14 +1042,7 @@ module vortex_afu import ccip_if_pkg::*; import local_mem_cfg_pkg::*; import VX_
af2cp_sTxPort.c1.valid,
cp2af_sRxPort.c0TxAlmFull,
cp2af_sRxPort.c1TxAlmFull,
af2cp_sTxPort.c2.mmioRdValid,
cci_wr_req_fire,
cci_wr_rsp_fire,
cci_rd_req_fire,
cci_rd_rsp_fire,
cci_pending_reads_full,
cci_pending_writes_empty,
cci_pending_writes_full
af2cp_sTxPort.c2.mmioRdValid
},{
cmd_type,
state,
@ -1081,7 +1072,7 @@ module vortex_afu import ccip_if_pkg::*; import local_mem_cfg_pkg::*; import VX_
reset_negedge, 1'b0, 4096
);
`else
`SCOPE_IO_UNUSED(0)
`SCOPE_IO_UNUSED_W(0)
`endif
///////////////////////////////////////////////////////////////////////////////

15
hw/rtl/core/VX_fetch.sv
View file

@ -41,11 +41,7 @@ module VX_fetch import VX_gpu_pkg::*; #(
wire [`UUID_WIDTH-1:0] rsp_uuid;
wire [`NW_WIDTH-1:0] req_tag, rsp_tag;
wire schedule_fire = schedule_if.valid && schedule_if.ready;
wire icache_req_fire = icache_req_valid && icache_req_ready;
wire icache_rsp_fire = icache_bus_if.rsp_valid && icache_bus_if.rsp_ready;
`UNUSED_VAR (schedule_fire)
`UNUSED_VAR (icache_rsp_fire)
assign req_tag = schedule_if.data.wid;
@ -139,13 +135,16 @@ module VX_fetch import VX_gpu_pkg::*; #(
`ifdef DBG_SCOPE_FETCH
`SCOPE_IO_SWITCH (1);
`NEG_EDGE (reset_negedge, reset);
`SCOPE_TAP_EX (0, 1, 3, (
`SCOPE_TAP_EX (0, 1, 6, (
`UUID_WIDTH + `NW_WIDTH + `NUM_THREADS + `PC_BITS + ICACHE_TAG_WIDTH + ICACHE_WORD_SIZE +
ICACHE_ADDR_WIDTH + (ICACHE_WORD_SIZE * 8) + ICACHE_TAG_WIDTH
), {
schedule_fire,
icache_req_fire,
icache_rsp_fire
schedule_if.valid,
schedule_if.ready,
icache_bus_if.req_valid,
icache_bus_if.req_ready,
icache_bus_if.rsp_valid,
icache_bus_if.rsp_ready
}, {
schedule_if.data.uuid, schedule_if.data.wid, schedule_if.data.tmask, schedule_if.data.PC,
icache_bus_if.req_data.tag, icache_bus_if.req_data.byteen, icache_bus_if.req_data.addr,

14
hw/rtl/core/VX_issue_slice.sv
View file

@ -36,11 +36,6 @@ module VX_issue_slice import VX_gpu_pkg::*; #(
VX_scoreboard_if scoreboard_if();
VX_operands_if operands_if();
wire operands_if_fire = operands_if.valid && operands_if.ready;
wire writeback_if_valid = writeback_if.valid;
`UNUSED_VAR (operands_if_fire)
`UNUSED_VAR (writeback_if_valid)
VX_ibuffer #(
.INSTANCE_ID ($sformatf("%s-ibuffer", INSTANCE_ID))
) ibuffer (
@ -97,13 +92,14 @@ module VX_issue_slice import VX_gpu_pkg::*; #(
`ifdef DBG_SCOPE_ISSUE
`SCOPE_IO_SWITCH (1);
`NEG_EDGE (reset_negedge, reset);
`SCOPE_TAP_EX (0, 2, 2, (
`SCOPE_TAP_EX (0, 2, 3, (
`UUID_WIDTH + `NUM_THREADS + `EX_BITS + `INST_OP_BITS +
1 + `NR_BITS + (`NUM_THREADS * 3 * `XLEN) +
`UUID_WIDTH + `NUM_THREADS + `NR_BITS + (`NUM_THREADS*`XLEN) + 1
), {
operands_if_fire,
writeback_if_valid
operands_if.valid,
operands_if.ready,
writeback_if.valid
}, {
operands_if.data.uuid,
operands_if.data.tmask,
@ -138,7 +134,7 @@ module VX_issue_slice import VX_gpu_pkg::*; #(
`ifdef DBG_TRACE_PIPELINE
always @(posedge clk) begin
if (operands_if_fire) begin
if (operands_if.valid && operands_if.ready) begin
`TRACE(1, ("%t: %s: wid=%0d, PC=0x%0h, ex=", $time, INSTANCE_ID, wis_to_wid(operands_if.data.wis, ISSUE_ID), {operands_if.data.PC, 1'b0}))
trace_ex_type(1, operands_if.data.ex_type);
`TRACE(1, (", op="))

10
hw/rtl/core/VX_lsu_slice.sv
View file

@ -102,8 +102,6 @@ module VX_lsu_slice import VX_gpu_pkg::*; #(
wire mem_req_fire = mem_req_valid && mem_req_ready;
wire mem_rsp_fire = mem_rsp_valid && mem_rsp_ready;
`UNUSED_VAR (mem_req_fire)
`UNUSED_VAR (mem_rsp_fire)
wire mem_rsp_sop_pkt, mem_rsp_eop_pkt;
wire no_rsp_buf_valid, no_rsp_buf_ready;
@ -538,11 +536,13 @@ module VX_lsu_slice import VX_gpu_pkg::*; #(
`ifdef DBG_SCOPE_LSU
`SCOPE_IO_SWITCH (1);
`NEG_EDGE (reset_negedge, reset);
`SCOPE_TAP_EX (0, 3, 2, (
`SCOPE_TAP_EX (0, 3, 4, (
1 + NUM_LANES * (`XLEN + LSU_WORD_SIZE + LSU_WORD_SIZE * 8) + `UUID_WIDTH + NUM_LANES * LSU_WORD_SIZE * 8 + `UUID_WIDTH
), {
mem_req_fire,
mem_rsp_fire
mem_req_valid,
mem_req_ready,
mem_rsp_valid,
mem_rsp_ready
}, {
mem_req_rw,
full_addr,