mirror of
https://github.com/vortexgpgpu/vortex.git
synced 2025-04-23 21:39:10 -04:00
minor update
This commit is contained in:
parent
6d0e345073
commit
2776f2cdf0
17 changed files with 22 additions and 27 deletions
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@ -194,7 +194,7 @@ module Vortex import VX_gpu_pkg::*; (
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`endif
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`ifdef DBG_TRACE_CORE_MEM
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`ifdef DBG_TRACE_MEM
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always @(posedge clk) begin
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if (mem_req_fire) begin
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if (mem_req_rw)
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@ -178,7 +178,7 @@ module VX_commit import VX_gpu_pkg::*; #(
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end
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assign sim_wb_value = sim_wb_value_r;
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`ifdef DBG_TRACE_CORE_PIPELINE
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`ifdef DBG_TRACE_PIPELINE
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for (genvar i = 0; i < `ISSUE_WIDTH; ++i) begin
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for (genvar j = 0; j < `NUM_EX_UNITS; ++j) begin
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always @(posedge clk) begin
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@ -44,7 +44,7 @@ module VX_dcr_data import VX_gpu_pkg::*; (
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assign base_dcrs = dcrs;
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`ifdef DBG_TRACE_CORE_PIPELINE
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`ifdef DBG_TRACE_PIPELINE
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always @(posedge clk) begin
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if (dcr_bus_if.write_valid) begin
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`TRACE(1, ("%d: base-dcr: state=", $time));
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@ -537,7 +537,7 @@ module VX_decode #(
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assign fetch_if.ibuf_pop = decode_if.ibuf_pop;
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`endif
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`ifdef DBG_TRACE_CORE_PIPELINE
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`ifdef DBG_TRACE_PIPELINE
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`ifdef FLEN_64
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wire fdst_d = decode_if.data.imm[0];
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`else
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@ -117,7 +117,7 @@ module VX_dispatch import VX_gpu_pkg::*; #(
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end
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`endif
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`ifdef DBG_TRACE_CORE_PIPELINE
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`ifdef DBG_TRACE_PIPELINE
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for (genvar i=0; i < `ISSUE_WIDTH; ++i) begin
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always @(posedge clk) begin
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if (operands_if[i].valid && operands_if[i].ready) begin
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@ -170,7 +170,7 @@ module VX_fetch import VX_gpu_pkg::*; #(
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`SCOPE_IO_UNUSED()
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`endif
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`ifdef DBG_TRACE_CORE_MEM
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`ifdef DBG_TRACE_MEM
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wire schedule_fire = schedule_if.valid && schedule_if.ready;
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wire fetch_fire = fetch_if.valid && fetch_if.ready;
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always @(posedge clk) begin
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@ -179,7 +179,7 @@ module VX_int_unit #(
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assign commit_if.data.PC = PC_r;
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`ifdef DBG_TRACE_CORE_PIPELINE
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`ifdef DBG_TRACE_PIPELINE
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always @(posedge clk) begin
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if (branch_ctl_if.valid) begin
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`TRACE(1, ("%d: core%0d-branch: wid=%0d, PC=0x%0h, taken=%b, dest=0x%0h (#%0d)\n",
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@ -475,7 +475,7 @@ module VX_lsu_slice import VX_gpu_pkg::*; #(
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`UNUSED_PIN (sel_out)
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);
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`ifdef DBG_TRACE_CORE_MEM
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`ifdef DBG_TRACE_MEM
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always @(posedge clk) begin
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if (execute_if.valid && fence_wait) begin
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`TRACE(1, ("%d: *** D$%0d fence wait\n", $time, CORE_ID));
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@ -264,7 +264,7 @@ module VX_scoreboard import VX_gpu_pkg::*; #(
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timeout_ctr <= '0;
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end else begin
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if (staging_if[i].valid && ~staging_if[i].ready) begin
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`ifdef DBG_TRACE_CORE_PIPELINE
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`ifdef DBG_TRACE_PIPELINE
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`TRACE(3, ("%d: *** core%0d-scoreboard-stall: wid=%0d, PC=0x%0h, tmask=%b, cycles=%0d, inuse=%b (#%0d)\n",
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$time, CORE_ID, i, staging_if[i].data.PC, staging_if[i].data.tmask, timeout_ctr,
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operands_busy_r, staging_if[i].data.uuid));
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@ -323,7 +323,7 @@ module VX_mem_coalescer #(
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assign in_rsp_tag = {out_rsp_tag[OUT_TAG_WIDTH-1 -: UUID_WIDTH], ibuf_dout_tag};
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assign out_rsp_ready = in_rsp_ready;
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`ifndef NDEBUG
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`ifdef DBG_TRACE_MEM
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wire [`UP(UUID_WIDTH)-1:0] out_req_uuid;
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wire [`UP(UUID_WIDTH)-1:0] out_rsp_uuid;
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@ -557,7 +557,7 @@ module VX_mem_scheduler #(
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///////////////////////////////////////////////////////////////////////////
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`ifndef NDEBUG
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`ifdef DBG_TRACE_MEM
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wire [`UP(UUID_WIDTH)-1:0] mem_req_dbg_uuid;
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wire [`UP(UUID_WIDTH)-1:0] mem_rsp_dbg_uuid;
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wire [`UP(UUID_WIDTH)-1:0] rsp_dbg_uuid;
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@ -275,7 +275,7 @@ module VX_local_mem import VX_gpu_pkg::*; #(
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`endif
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`ifdef DBG_TRACE_LMEM
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`ifdef DBG_TRACE_MEM
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wire [NUM_REQS-1:0][`UP(UUID_WIDTH)-1:0] req_uuid;
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wire [NUM_REQS-1:0][`UP(UUID_WIDTH)-1:0] rsp_uuid;
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@ -20,10 +20,9 @@ else
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endif
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# control RTL debug tracing states
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DBG_TRACE_FLAGS += -DDBG_TRACE_CORE_PIPELINE
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DBG_TRACE_FLAGS += -DDBG_TRACE_CORE_MEM
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DBG_TRACE_FLAGS += -DDBG_TRACE_PIPELINE
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DBG_TRACE_FLAGS += -DDBG_TRACE_MEM
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DBG_TRACE_FLAGS += -DDBG_TRACE_CACHE
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DBG_TRACE_FLAGS += -DDBG_TRACE_LMEM
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DBG_TRACE_FLAGS += -DDBG_TRACE_AFU
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DBG_TRACE_FLAGS += -DDBG_TRACE_GBAR
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@ -44,10 +44,9 @@ XO_CONTAINER = $(BIN_DIR)/vortex_afu.xo
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XCLBIN_CONTAINER = $(BIN_DIR)/vortex_afu.xclbin
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# Control RTL debug tracing states
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DBG_TRACE_FLAGS += -DDBG_TRACE_CORE_PIPELINE
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DBG_TRACE_FLAGS += -DDBG_TRACE_CORE_MEM
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DBG_TRACE_FLAGS += -DDBG_TRACE_PIPELINE
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DBG_TRACE_FLAGS += -DDBG_TRACE_MEM
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DBG_TRACE_FLAGS += -DDBG_TRACE_CACHE
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DBG_TRACE_FLAGS += -DDBG_TRACE_LMEM
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DBG_TRACE_FLAGS += -DDBG_TRACE_AFU
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DBG_TRACE_FLAGS += -DDBG_TRACE_GBAR
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@ -16,10 +16,9 @@ BUILD_DIR = $(PREFIX)_$(TOP_LEVEL_ENTITY)
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BIN_DIR = $(BUILD_DIR)/bin
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# control RTL debug tracing states
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DBG_TRACE_FLAGS += -DDBG_TRACE_CORE_PIPELINE
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DBG_TRACE_FLAGS += -DDBG_TRACE_CORE_MEM
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DBG_TRACE_FLAGS += -DDBG_TRACE_PIPELINE
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DBG_TRACE_FLAGS += -DDBG_TRACE_MEM
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DBG_TRACE_FLAGS += -DDBG_TRACE_CACHE
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DBG_TRACE_FLAGS += -DDBG_TRACE_LMEM
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DBG_TRACE_FLAGS += -DDBG_TRACE_AFU
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DBG_TRACE_FLAGS += -DDBG_TRACE_GBAR
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@ -19,10 +19,9 @@ LDFLAGS += -shared $(THIRD_PARTY_DIR)/softfloat/build/Linux-x86_64-GCC/softfloat
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LDFLAGS += -L$(THIRD_PARTY_DIR)/ramulator -lramulator -pthread
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# control RTL debug tracing states
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DBG_TRACE_FLAGS += -DDBG_TRACE_CORE_PIPELINE
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DBG_TRACE_FLAGS += -DDBG_TRACE_CORE_MEM
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DBG_TRACE_FLAGS += -DDBG_TRACE_PIPELINE
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DBG_TRACE_FLAGS += -DDBG_TRACE_MEM
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DBG_TRACE_FLAGS += -DDBG_TRACE_CACHE
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DBG_TRACE_FLAGS += -DDBG_TRACE_LMEM
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DBG_TRACE_FLAGS += -DDBG_TRACE_AFU
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DBG_TRACE_FLAGS += -DDBG_TRACE_SCOPE
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DBG_TRACE_FLAGS += -DDBG_TRACE_GBAR
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@ -17,10 +17,9 @@ LDFLAGS += $(THIRD_PARTY_DIR)/softfloat/build/Linux-x86_64-GCC/softfloat.a
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LDFLAGS += -L$(THIRD_PARTY_DIR)/ramulator -lramulator
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# control RTL debug tracing states
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DBG_TRACE_FLAGS += -DDBG_TRACE_CORE_PIPELINE
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DBG_TRACE_FLAGS += -DDBG_TRACE_CORE_MEM
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DBG_TRACE_FLAGS += -DDBG_TRACE_PIPELINE
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DBG_TRACE_FLAGS += -DDBG_TRACE_MEM
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DBG_TRACE_FLAGS += -DDBG_TRACE_CACHE
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DBG_TRACE_FLAGS += -DDBG_TRACE_LMEM
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DBG_TRACE_FLAGS += -DDBG_TRACE_AFU
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DBG_TRACE_FLAGS += -DDBG_TRACE_SCOPE
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DBG_TRACE_FLAGS += -DDBG_TRACE_GBAR
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