minor update

This commit is contained in:
Blaise Tine 2024-03-20 14:31:00 -07:00
parent 6d0e345073
commit 2776f2cdf0
17 changed files with 22 additions and 27 deletions

View file

@ -194,7 +194,7 @@ module Vortex import VX_gpu_pkg::*; (
`endif
`ifdef DBG_TRACE_CORE_MEM
`ifdef DBG_TRACE_MEM
always @(posedge clk) begin
if (mem_req_fire) begin
if (mem_req_rw)

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@ -178,7 +178,7 @@ module VX_commit import VX_gpu_pkg::*; #(
end
assign sim_wb_value = sim_wb_value_r;
`ifdef DBG_TRACE_CORE_PIPELINE
`ifdef DBG_TRACE_PIPELINE
for (genvar i = 0; i < `ISSUE_WIDTH; ++i) begin
for (genvar j = 0; j < `NUM_EX_UNITS; ++j) begin
always @(posedge clk) begin

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@ -44,7 +44,7 @@ module VX_dcr_data import VX_gpu_pkg::*; (
assign base_dcrs = dcrs;
`ifdef DBG_TRACE_CORE_PIPELINE
`ifdef DBG_TRACE_PIPELINE
always @(posedge clk) begin
if (dcr_bus_if.write_valid) begin
`TRACE(1, ("%d: base-dcr: state=", $time));

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@ -537,7 +537,7 @@ module VX_decode #(
assign fetch_if.ibuf_pop = decode_if.ibuf_pop;
`endif
`ifdef DBG_TRACE_CORE_PIPELINE
`ifdef DBG_TRACE_PIPELINE
`ifdef FLEN_64
wire fdst_d = decode_if.data.imm[0];
`else

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@ -117,7 +117,7 @@ module VX_dispatch import VX_gpu_pkg::*; #(
end
`endif
`ifdef DBG_TRACE_CORE_PIPELINE
`ifdef DBG_TRACE_PIPELINE
for (genvar i=0; i < `ISSUE_WIDTH; ++i) begin
always @(posedge clk) begin
if (operands_if[i].valid && operands_if[i].ready) begin

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@ -170,7 +170,7 @@ module VX_fetch import VX_gpu_pkg::*; #(
`SCOPE_IO_UNUSED()
`endif
`ifdef DBG_TRACE_CORE_MEM
`ifdef DBG_TRACE_MEM
wire schedule_fire = schedule_if.valid && schedule_if.ready;
wire fetch_fire = fetch_if.valid && fetch_if.ready;
always @(posedge clk) begin

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@ -179,7 +179,7 @@ module VX_int_unit #(
assign commit_if.data.PC = PC_r;
`ifdef DBG_TRACE_CORE_PIPELINE
`ifdef DBG_TRACE_PIPELINE
always @(posedge clk) begin
if (branch_ctl_if.valid) begin
`TRACE(1, ("%d: core%0d-branch: wid=%0d, PC=0x%0h, taken=%b, dest=0x%0h (#%0d)\n",

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@ -475,7 +475,7 @@ module VX_lsu_slice import VX_gpu_pkg::*; #(
`UNUSED_PIN (sel_out)
);
`ifdef DBG_TRACE_CORE_MEM
`ifdef DBG_TRACE_MEM
always @(posedge clk) begin
if (execute_if.valid && fence_wait) begin
`TRACE(1, ("%d: *** D$%0d fence wait\n", $time, CORE_ID));

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@ -264,7 +264,7 @@ module VX_scoreboard import VX_gpu_pkg::*; #(
timeout_ctr <= '0;
end else begin
if (staging_if[i].valid && ~staging_if[i].ready) begin
`ifdef DBG_TRACE_CORE_PIPELINE
`ifdef DBG_TRACE_PIPELINE
`TRACE(3, ("%d: *** core%0d-scoreboard-stall: wid=%0d, PC=0x%0h, tmask=%b, cycles=%0d, inuse=%b (#%0d)\n",
$time, CORE_ID, i, staging_if[i].data.PC, staging_if[i].data.tmask, timeout_ctr,
operands_busy_r, staging_if[i].data.uuid));

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@ -323,7 +323,7 @@ module VX_mem_coalescer #(
assign in_rsp_tag = {out_rsp_tag[OUT_TAG_WIDTH-1 -: UUID_WIDTH], ibuf_dout_tag};
assign out_rsp_ready = in_rsp_ready;
`ifndef NDEBUG
`ifdef DBG_TRACE_MEM
wire [`UP(UUID_WIDTH)-1:0] out_req_uuid;
wire [`UP(UUID_WIDTH)-1:0] out_rsp_uuid;

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@ -557,7 +557,7 @@ module VX_mem_scheduler #(
///////////////////////////////////////////////////////////////////////////
`ifndef NDEBUG
`ifdef DBG_TRACE_MEM
wire [`UP(UUID_WIDTH)-1:0] mem_req_dbg_uuid;
wire [`UP(UUID_WIDTH)-1:0] mem_rsp_dbg_uuid;
wire [`UP(UUID_WIDTH)-1:0] rsp_dbg_uuid;

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@ -275,7 +275,7 @@ module VX_local_mem import VX_gpu_pkg::*; #(
`endif
`ifdef DBG_TRACE_LMEM
`ifdef DBG_TRACE_MEM
wire [NUM_REQS-1:0][`UP(UUID_WIDTH)-1:0] req_uuid;
wire [NUM_REQS-1:0][`UP(UUID_WIDTH)-1:0] rsp_uuid;

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@ -20,10 +20,9 @@ else
endif
# control RTL debug tracing states
DBG_TRACE_FLAGS += -DDBG_TRACE_CORE_PIPELINE
DBG_TRACE_FLAGS += -DDBG_TRACE_CORE_MEM
DBG_TRACE_FLAGS += -DDBG_TRACE_PIPELINE
DBG_TRACE_FLAGS += -DDBG_TRACE_MEM
DBG_TRACE_FLAGS += -DDBG_TRACE_CACHE
DBG_TRACE_FLAGS += -DDBG_TRACE_LMEM
DBG_TRACE_FLAGS += -DDBG_TRACE_AFU
DBG_TRACE_FLAGS += -DDBG_TRACE_GBAR

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@ -44,10 +44,9 @@ XO_CONTAINER = $(BIN_DIR)/vortex_afu.xo
XCLBIN_CONTAINER = $(BIN_DIR)/vortex_afu.xclbin
# Control RTL debug tracing states
DBG_TRACE_FLAGS += -DDBG_TRACE_CORE_PIPELINE
DBG_TRACE_FLAGS += -DDBG_TRACE_CORE_MEM
DBG_TRACE_FLAGS += -DDBG_TRACE_PIPELINE
DBG_TRACE_FLAGS += -DDBG_TRACE_MEM
DBG_TRACE_FLAGS += -DDBG_TRACE_CACHE
DBG_TRACE_FLAGS += -DDBG_TRACE_LMEM
DBG_TRACE_FLAGS += -DDBG_TRACE_AFU
DBG_TRACE_FLAGS += -DDBG_TRACE_GBAR

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@ -16,10 +16,9 @@ BUILD_DIR = $(PREFIX)_$(TOP_LEVEL_ENTITY)
BIN_DIR = $(BUILD_DIR)/bin
# control RTL debug tracing states
DBG_TRACE_FLAGS += -DDBG_TRACE_CORE_PIPELINE
DBG_TRACE_FLAGS += -DDBG_TRACE_CORE_MEM
DBG_TRACE_FLAGS += -DDBG_TRACE_PIPELINE
DBG_TRACE_FLAGS += -DDBG_TRACE_MEM
DBG_TRACE_FLAGS += -DDBG_TRACE_CACHE
DBG_TRACE_FLAGS += -DDBG_TRACE_LMEM
DBG_TRACE_FLAGS += -DDBG_TRACE_AFU
DBG_TRACE_FLAGS += -DDBG_TRACE_GBAR

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@ -19,10 +19,9 @@ LDFLAGS += -shared $(THIRD_PARTY_DIR)/softfloat/build/Linux-x86_64-GCC/softfloat
LDFLAGS += -L$(THIRD_PARTY_DIR)/ramulator -lramulator -pthread
# control RTL debug tracing states
DBG_TRACE_FLAGS += -DDBG_TRACE_CORE_PIPELINE
DBG_TRACE_FLAGS += -DDBG_TRACE_CORE_MEM
DBG_TRACE_FLAGS += -DDBG_TRACE_PIPELINE
DBG_TRACE_FLAGS += -DDBG_TRACE_MEM
DBG_TRACE_FLAGS += -DDBG_TRACE_CACHE
DBG_TRACE_FLAGS += -DDBG_TRACE_LMEM
DBG_TRACE_FLAGS += -DDBG_TRACE_AFU
DBG_TRACE_FLAGS += -DDBG_TRACE_SCOPE
DBG_TRACE_FLAGS += -DDBG_TRACE_GBAR

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@ -17,10 +17,9 @@ LDFLAGS += $(THIRD_PARTY_DIR)/softfloat/build/Linux-x86_64-GCC/softfloat.a
LDFLAGS += -L$(THIRD_PARTY_DIR)/ramulator -lramulator
# control RTL debug tracing states
DBG_TRACE_FLAGS += -DDBG_TRACE_CORE_PIPELINE
DBG_TRACE_FLAGS += -DDBG_TRACE_CORE_MEM
DBG_TRACE_FLAGS += -DDBG_TRACE_PIPELINE
DBG_TRACE_FLAGS += -DDBG_TRACE_MEM
DBG_TRACE_FLAGS += -DDBG_TRACE_CACHE
DBG_TRACE_FLAGS += -DDBG_TRACE_LMEM
DBG_TRACE_FLAGS += -DDBG_TRACE_AFU
DBG_TRACE_FLAGS += -DDBG_TRACE_SCOPE
DBG_TRACE_FLAGS += -DDBG_TRACE_GBAR