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RTL code refactoring

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This commit is contained in:
Blaise Tine 2020-04-23 14:12:08 -04:00
parent f79067fb52
commit 2846809823
3 changed files with 68 additions and 68 deletions
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50
hw/rtl/Vortex.v
View file

@ -13,17 +13,17 @@ module Vortex #(
output wire [31:0] io_data,
// DRAM Dcache Req
output wire dram_req_read,
output wire dram_req_write,
output wire [31:0] dram_req_addr,
output wire [`DBANK_LINE_SIZE-1:0] dram_req_data,
input wire dram_req_ready,
output wire D_dram_req_read,
output wire D_dram_req_write,
output wire [31:0] D_dram_req_addr,
output wire [`DBANK_LINE_SIZE-1:0] D_dram_req_data,
input wire D_dram_req_ready,
// DRAM Dcache Rsp
input wire dram_rsp_valid,
input wire [31:0] dram_rsp_addr,
input wire [`DBANK_LINE_SIZE-1:0] dram_rsp_data,
output wire dram_rsp_ready,
input wire D_dram_rsp_valid,
input wire [31:0] D_dram_rsp_addr,
input wire [`DBANK_LINE_SIZE-1:0] D_dram_rsp_data,
output wire D_dram_rsp_ready,
// DRAM Icache Req
output wire I_dram_req_read,
@ -66,24 +66,24 @@ module Vortex #(
VX_cache_core_req_if #(.NUM_REQUESTS(`DNUM_REQUESTS)) dcache_core_req_if();
VX_cache_core_req_if #(.NUM_REQUESTS(`DNUM_REQUESTS)) dcache_core_req_qual_if();
VX_cache_dram_req_if #(.BANK_LINE_WORDS(`DBANK_LINE_WORDS)) cache_dram_req_if();
VX_cache_dram_rsp_if #(.BANK_LINE_WORDS(`DBANK_LINE_WORDS)) cache_dram_rsp_if();
VX_cache_dram_req_if #(.BANK_LINE_WORDS(`DBANK_LINE_WORDS)) dcache_dram_req_if();
VX_cache_dram_rsp_if #(.BANK_LINE_WORDS(`DBANK_LINE_WORDS)) dcache_dram_rsp_if();
assign cache_dram_rsp_if.dram_rsp_valid = dram_rsp_valid;
assign cache_dram_rsp_if.dram_rsp_addr = dram_rsp_addr;
assign dcache_dram_rsp_if.dram_rsp_valid = D_dram_rsp_valid;
assign dcache_dram_rsp_if.dram_rsp_addr = D_dram_rsp_addr;
assign dram_req_write = cache_dram_req_if.dram_req_write;
assign dram_req_read = cache_dram_req_if.dram_req_read;
assign dram_req_addr = cache_dram_req_if.dram_req_addr;
assign dram_rsp_ready = cache_dram_req_if.dram_rsp_ready;
assign D_dram_req_write = dcache_dram_req_if.dram_req_write;
assign D_dram_req_read = dcache_dram_req_if.dram_req_read;
assign D_dram_req_addr = dcache_dram_req_if.dram_req_addr;
assign D_dram_rsp_ready = dcache_dram_req_if.dram_rsp_ready;
assign cache_dram_req_if.dram_req_ready = dram_req_ready;
assign dcache_dram_req_if.dram_req_ready = D_dram_req_ready;
genvar i;
generate
for (i = 0; i < `DBANK_LINE_WORDS; i=i+1) begin
assign cache_dram_rsp_if.dram_rsp_data[i] = dram_rsp_data[i * 32 +: 32];
assign dram_req_data[i * 32 +: 32] = cache_dram_req_if.dram_req_data[i];
assign dcache_dram_rsp_if.dram_rsp_data[i] = D_dram_rsp_data[i * 32 +: 32];
assign D_dram_req_data[i * 32 +: 32] = dcache_dram_req_if.dram_req_data[i];
end
endgenerate
@ -115,8 +115,8 @@ module Vortex #(
VX_cache_dram_req_if #(.BANK_LINE_WORDS(`IBANK_LINE_WORDS)) icache_dram_req_if();
VX_cache_dram_rsp_if #(.BANK_LINE_WORDS(`IBANK_LINE_WORDS)) icache_dram_rsp_if();
assign icache_dram_rsp_if.dram_rsp_valid = I_dram_rsp_valid;
assign icache_dram_rsp_if.dram_rsp_addr = I_dram_rsp_addr;
assign icache_dram_rsp_if.dram_rsp_valid = I_dram_rsp_valid;
assign icache_dram_rsp_if.dram_rsp_addr = I_dram_rsp_addr;
assign I_dram_req_write = icache_dram_req_if.dram_req_write;
assign I_dram_req_read = icache_dram_req_if.dram_req_read;
@ -129,7 +129,7 @@ module Vortex #(
generate
for (j = 0; j < `IBANK_LINE_WORDS; j = j + 1) begin
assign icache_dram_rsp_if.dram_rsp_data[j] = I_dram_rsp_data[j * 32 +: 32];
assign I_dram_req_data[j * 32 +: 32] = icache_dram_req_if.dram_req_data[j];
assign I_dram_req_data[j * 32 +: 32] = icache_dram_req_if.dram_req_data[j];
end
endgenerate
@ -201,8 +201,8 @@ VX_dmem_ctrl dmem_ctrl (
.reset (reset),
// Dram <-> Dcache
.dcache_dram_req_if (cache_dram_req_if),
.dcache_dram_rsp_if (cache_dram_rsp_if),
.dcache_dram_req_if (dcache_dram_req_if),
.dcache_dram_rsp_if (dcache_dram_rsp_if),
.dcache_snp_req_if (dcache_snp_req_if),
// Dram <-> Icache

62
hw/rtl/Vortex_Cluster.v
View file

@ -33,16 +33,16 @@ module Vortex_Cluster #(
output wire ebreak
);
// DRAM Dcache Req
wire[`NUM_CORES-1:0] per_core_dram_req_read;
wire[`NUM_CORES-1:0] per_core_dram_req_write;
wire[`NUM_CORES-1:0] [31:0] per_core_dram_req_addr;
wire[`NUM_CORES-1:0][`DBANK_LINE_WORDS-1:0][31:0] per_core_dram_req_data;
wire[`NUM_CORES-1:0] per_core_D_dram_req_read;
wire[`NUM_CORES-1:0] per_core_D_dram_req_write;
wire[`NUM_CORES-1:0] [31:0] per_core_D_dram_req_addr;
wire[`NUM_CORES-1:0][`DBANK_LINE_WORDS-1:0][31:0] per_core_D_dram_req_data;
// DRAM Dcache Rsp
wire[`NUM_CORES-1:0] per_core_dram_rsp_valid;
wire[`NUM_CORES-1:0] [31:0] per_core_dram_rsp_addr;
wire[`NUM_CORES-1:0][`DBANK_LINE_WORDS-1:0][31:0] per_core_dram_rsp_data;
wire[`NUM_CORES-1:0] per_core_dram_rsp_ready;
wire[`NUM_CORES-1:0] per_core_D_dram_rsp_valid;
wire[`NUM_CORES-1:0] [31:0] per_core_D_dram_rsp_addr;
wire[`NUM_CORES-1:0][`DBANK_LINE_WORDS-1:0][31:0] per_core_D_dram_rsp_data;
wire[`NUM_CORES-1:0] per_core_D_dram_rsp_ready;
// DRAM Icache Req
wire[`NUM_CORES-1:0] per_core_I_dram_req_read;
@ -75,8 +75,8 @@ module Vortex_Cluster #(
for (curr_core = 0; curr_core < `NUM_CORES; curr_core=curr_core+1) begin
wire [`IBANK_LINE_WORDS-1:0][31:0] curr_core_I_dram_req_data;
wire [`DBANK_LINE_WORDS-1:0][31:0] curr_core_dram_req_data ;
wire [`IBANK_LINE_WORDS-1:0][31:0] curr_core_D_dram_req_data;
wire [`DBANK_LINE_WORDS-1:0][31:0] curr_core_I_dram_req_data ;
assign io_valid[curr_core] = per_core_io_valid[curr_core];
assign io_data [curr_core] = per_core_io_data [curr_core];
@ -88,15 +88,15 @@ module Vortex_Cluster #(
.reset (reset),
.io_valid (per_core_io_valid [curr_core]),
.io_data (per_core_io_data [curr_core]),
.dram_req_read (per_core_dram_req_read [curr_core]),
.dram_req_write (per_core_dram_req_write [curr_core]),
.dram_req_addr (per_core_dram_req_addr [curr_core]),
.dram_req_data (curr_core_dram_req_data ),
.dram_req_ready (l2c_core_req_ready ),
.dram_rsp_valid (per_core_dram_rsp_valid [curr_core]),
.dram_rsp_addr (per_core_dram_rsp_addr [curr_core]),
.dram_rsp_data (per_core_dram_rsp_data [curr_core]),
.dram_rsp_ready (per_core_dram_rsp_ready [curr_core]),
.D_dram_req_read (per_core_D_dram_req_read [curr_core]),
.D_dram_req_write (per_core_D_dram_req_write [curr_core]),
.D_dram_req_addr (per_core_D_dram_req_addr [curr_core]),
.D_dram_req_data (curr_core_D_dram_req_data ),
.D_dram_req_ready (l2c_core_req_ready ),
.D_dram_rsp_valid (per_core_D_dram_rsp_valid [curr_core]),
.D_dram_rsp_addr (per_core_D_dram_rsp_addr [curr_core]),
.D_dram_rsp_data (per_core_D_dram_rsp_data [curr_core]),
.D_dram_rsp_ready (per_core_D_dram_rsp_ready [curr_core]),
.I_dram_req_read (per_core_I_dram_req_read [curr_core]),
.I_dram_req_write (per_core_I_dram_req_write [curr_core]),
.I_dram_req_addr (per_core_I_dram_req_addr [curr_core]),
@ -112,8 +112,8 @@ module Vortex_Cluster #(
.ebreak (per_core_ebreak [curr_core])
);
assign per_core_dram_req_data [curr_core] = curr_core_dram_req_data;
assign per_core_I_dram_req_data[curr_core] = curr_core_I_dram_req_data;
assign per_core_D_dram_req_data [curr_core] = curr_core_D_dram_req_data;
assign per_core_I_dram_req_data [curr_core] = curr_core_I_dram_req_data;
end
endgenerate
@ -147,36 +147,36 @@ module Vortex_Cluster #(
generate
for (l2c_curr_core = 0; l2c_curr_core < `L2NUM_REQUESTS; l2c_curr_core=l2c_curr_core+2) begin
// Core Request
assign l2c_core_req_valid [l2c_curr_core] = (per_core_dram_req_read[(l2c_curr_core/2)] | per_core_dram_req_write[(l2c_curr_core/2)]);
assign l2c_core_req_valid [l2c_curr_core] = (per_core_D_dram_req_read[(l2c_curr_core/2)] | per_core_D_dram_req_write[(l2c_curr_core/2)]);
assign l2c_core_req_valid [l2c_curr_core+1] = (per_core_I_dram_req_read[(l2c_curr_core/2)] | per_core_I_dram_req_write[(l2c_curr_core/2)]);
assign l2c_core_req_mem_write [l2c_curr_core] = per_core_dram_req_write[(l2c_curr_core/2)] ? `SW_MEM_WRITE : `NO_MEM_WRITE;
assign l2c_core_req_mem_write [l2c_curr_core] = per_core_D_dram_req_write[(l2c_curr_core/2)] ? `SW_MEM_WRITE : `NO_MEM_WRITE;
assign l2c_core_req_mem_write [l2c_curr_core+1] = `NO_MEM_WRITE; // I caches don't write
assign l2c_core_req_mem_read [l2c_curr_core] = per_core_dram_req_read[(l2c_curr_core/2)] ? `LW_MEM_READ : `NO_MEM_READ;
assign l2c_core_req_mem_read [l2c_curr_core] = per_core_D_dram_req_read[(l2c_curr_core/2)] ? `LW_MEM_READ : `NO_MEM_READ;
assign l2c_core_req_mem_read [l2c_curr_core+1] = `LW_MEM_READ; // I caches don't write
assign l2c_core_req_wb [l2c_curr_core] = per_core_dram_req_read[(l2c_curr_core/2)] ? 1 : 0;
assign l2c_core_req_wb [l2c_curr_core] = per_core_D_dram_req_read[(l2c_curr_core/2)] ? 1 : 0;
assign l2c_core_req_wb [l2c_curr_core+1] = 1; // I caches don't write
assign l2c_core_req_addr [l2c_curr_core] = per_core_dram_req_addr [(l2c_curr_core/2)];
assign l2c_core_req_addr [l2c_curr_core] = per_core_D_dram_req_addr [(l2c_curr_core/2)];
assign l2c_core_req_addr [l2c_curr_core+1] = per_core_I_dram_req_addr[(l2c_curr_core/2)];
assign l2c_core_req_data [l2c_curr_core] = per_core_dram_req_data [(l2c_curr_core/2)];
assign l2c_core_req_data [l2c_curr_core] = per_core_D_dram_req_data [(l2c_curr_core/2)];
assign l2c_core_req_data [l2c_curr_core+1] = per_core_I_dram_req_data[(l2c_curr_core/2)];
// Core can't accept Response
assign l2c_core_rsp_ready [l2c_curr_core] = per_core_dram_rsp_ready [(l2c_curr_core/2)];
assign l2c_core_rsp_ready [l2c_curr_core] = per_core_D_dram_rsp_ready [(l2c_curr_core/2)];
assign l2c_core_rsp_ready [l2c_curr_core+1] = per_core_I_dram_rsp_ready[(l2c_curr_core/2)];
// Cache Fill Response
assign per_core_dram_rsp_valid [(l2c_curr_core/2)] = l2c_wb[l2c_curr_core];
assign per_core_D_dram_rsp_valid [(l2c_curr_core/2)] = l2c_wb[l2c_curr_core];
assign per_core_I_dram_rsp_valid [(l2c_curr_core/2)] = l2c_wb[l2c_curr_core+1];
assign per_core_dram_rsp_data [(l2c_curr_core/2)] = l2c_wb_data[l2c_curr_core];
assign per_core_D_dram_rsp_data [(l2c_curr_core/2)] = l2c_wb_data[l2c_curr_core];
assign per_core_I_dram_rsp_data [(l2c_curr_core/2)] = l2c_wb_data[l2c_curr_core+1];
assign per_core_dram_rsp_addr [(l2c_curr_core/2)] = l2c_wb_addr[l2c_curr_core];
assign per_core_D_dram_rsp_addr [(l2c_curr_core/2)] = l2c_wb_addr[l2c_curr_core];
assign per_core_I_dram_rsp_addr [(l2c_curr_core/2)] = l2c_wb_addr[l2c_curr_core+1];
end
endgenerate

24
hw/simulate/simulator.cpp
View file

@ -60,11 +60,11 @@ void Simulator::dbus_driver() {
#endif
if (!dram_stalled_) {
if (vortex_->dram_req_read) {
if (vortex_->D_dram_req_read) {
// Need to add an element
dram_req_t dram_req;
dram_req.cycles_left = DRAM_LATENCY;
dram_req.base_addr = vortex_->dram_req_addr;
dram_req.base_addr = vortex_->D_dram_req_addr;
dram_req.data = (unsigned *)malloc(GLOBAL_BLOCK_SIZE_BYTES);
for (int i = 0; i < (GLOBAL_BLOCK_SIZE_BYTES / 4); i++) {
@ -76,33 +76,33 @@ void Simulator::dbus_driver() {
dram_req_vec_.push_back(dram_req);
}
if (vortex_->dram_req_write) {
unsigned base_addr = vortex_->dram_req_addr;
if (vortex_->D_dram_req_write) {
unsigned base_addr = vortex_->D_dram_req_addr;
for (int i = 0; i < (GLOBAL_BLOCK_SIZE_BYTES / 4); i++) {
unsigned curr_addr = base_addr + (i * 4);
unsigned data_wr = vortex_->dram_req_data[i];
unsigned data_wr = vortex_->D_dram_req_data[i];
ram_->writeWord(curr_addr, &data_wr);
}
}
}
if (vortex_->dram_rsp_ready && dequeue_valid) {
vortex_->dram_rsp_valid = 1;
vortex_->dram_rsp_addr = dram_req_vec_[dequeue_index].base_addr;
if (vortex_->D_dram_rsp_ready && dequeue_valid) {
vortex_->D_dram_rsp_valid = 1;
vortex_->D_dram_rsp_addr = dram_req_vec_[dequeue_index].base_addr;
for (int i = 0; i < (GLOBAL_BLOCK_SIZE_BYTES / 4); i++) {
vortex_->dram_rsp_data[i] = dram_req_vec_[dequeue_index].data[i];
vortex_->D_dram_rsp_data[i] = dram_req_vec_[dequeue_index].data[i];
}
free(dram_req_vec_[dequeue_index].data);
dram_req_vec_.erase(dram_req_vec_.begin() + dequeue_index);
} else {
vortex_->dram_rsp_valid = 0;
vortex_->dram_rsp_addr = 0;
vortex_->D_dram_rsp_valid = 0;
vortex_->D_dram_rsp_addr = 0;
}
vortex_->dram_req_ready = ~dram_stalled_;
vortex_->D_dram_req_ready = ~dram_stalled_;
}
#ifndef USE_MULTICORE