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https://github.com/vortexgpgpu/vortex.git
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minor update
This commit is contained in:
Blaise Tine
parent
3e87cab7e5
commit
29466b0cef
1 changed files with 53 additions and 46 deletions
99
hw/rtl/cache/VX_cache_bank.sv
vendored
99
hw/rtl/cache/VX_cache_bank.sv
vendored
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@ -135,7 +135,6 @@ module VX_cache_bank #(
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wire mshr_deq_valid;
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wire mshr_deq_ready;
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wire [MSHR_ADDR_WIDTH-1:0] mshr_alloc_id;
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wire mshr_alm_full;
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wire [MSHR_ADDR_WIDTH-1:0] mshr_deq_id;
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wire [`LINE_ADDR_WIDTH-1:0] mshr_deq_addr;
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@ -144,22 +143,23 @@ module VX_cache_bank #(
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wire [NUM_PORTS-1:0][REQ_SEL_WIDTH-1:0] mshr_idx;
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wire [NUM_PORTS-1:0] mshr_pmask;
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wire [`LINE_ADDR_WIDTH-1:0] addr_st0, addr_st1;
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wire [`LINE_ADDR_WIDTH-1:0] req_addr, addr_st0, addr_st1;
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wire is_read_st0, is_read_st1;
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wire is_write_st0, is_write_st1;
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wire [NUM_PORTS-1:0][WORD_SEL_WIDTH-1:0] wsel_st0, wsel_st1;
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wire [NUM_PORTS-1:0][WORD_SEL_WIDTH-1:0] wsel_st0, wsel_st1;
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wire [NUM_PORTS-1:0][WORD_SIZE-1:0] byteen_st0, byteen_st1;
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wire [NUM_PORTS-1:0][REQ_SEL_WIDTH-1:0] req_idx_st0, req_idx_st1;
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wire [NUM_PORTS-1:0] pmask_st0, pmask_st1;
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wire [NUM_PORTS-1:0][TAG_WIDTH-1:0] tag_st0, tag_st1;
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wire [NUM_PORTS-1:0][`WORD_WIDTH-1:0] rdata_st1;
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wire [`LINE_WIDTH-1:0] wdata_st0, wdata_st1;
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wire [`LINE_WIDTH-1:0] req_data, data_st0, data_st1;
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wire [MSHR_ADDR_WIDTH-1:0] mshr_id_st0, mshr_id_st1;
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wire valid_st0, valid_st1;
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wire req_valid, valid_st0, valid_st1;
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wire is_fill_st0, is_fill_st1;
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wire is_mshr_st0, is_mshr_st1;
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wire is_hit_st0, is_hit_st1;
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wire is_init_st0;
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wire [MSHR_ADDR_WIDTH-1:0] mshr_alloc_id_st0;
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wire mshr_pending_st0, mshr_pending_st1;
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wire rdw_hazard_st0;
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@ -167,7 +167,9 @@ module VX_cache_bank #(
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wire pipe_stall = crsq_stall || rdw_hazard_st1;
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// determine which input to select in priority order
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// inputs arbitration:
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// mshr replay has highest priority to maximize utilization since there is no miss.
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// handle memory responses next to prevent deadlock with potential memory request from a miss.
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wire mshr_grant = ~init_enable;
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wire mshr_enable = mshr_grant && mshr_deq_valid;
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@ -204,36 +206,41 @@ module VX_cache_bank #(
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`UNUSED_VAR (mshr_creq_tag)
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wire [`LINE_WIDTH-1:0] wdata_sel;
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assign wdata_sel[(NUM_PORTS * `WORD_WIDTH)-1:0] = (mem_rsp_valid || !WRITE_ENABLE) ? mem_rsp_data[(NUM_PORTS * `WORD_WIDTH)-1:0] : creq_data;
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assign req_valid = init_fire || mshr_deq_fire || mem_rsp_fire || creq_fire;
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assign req_addr = init_enable ? `LINE_ADDR_WIDTH'(init_addr) :
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(mshr_deq_valid ? mshr_deq_addr :
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(mem_rsp_valid ? mem_rsp_addr : creq_addr));
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assign req_data[(NUM_PORTS * `WORD_WIDTH)-1:0] = (mem_rsp_valid || !WRITE_ENABLE) ? mem_rsp_data[(NUM_PORTS * `WORD_WIDTH)-1:0] : creq_data;
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for (genvar i = NUM_PORTS * `WORD_WIDTH; i < `LINE_WIDTH; ++i) begin
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assign wdata_sel[i] = mem_rsp_data[i];
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end
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assign req_data[i] = mem_rsp_data[i];
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end
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VX_pipe_register #(
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.DATAW (1 + 1 + 1 + 1 + 1 + 1 + `LINE_ADDR_WIDTH + `LINE_WIDTH + NUM_PORTS * (WORD_SEL_WIDTH + WORD_SIZE + REQ_SEL_WIDTH + 1 + TAG_WIDTH) + MSHR_ADDR_WIDTH),
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.DATAW (1 + 1 + 1 + 1 + 1 + 1 + `LINE_ADDR_WIDTH + `LINE_WIDTH + NUM_PORTS * (WORD_SIZE + WORD_SEL_WIDTH + REQ_SEL_WIDTH + 1 + TAG_WIDTH) + MSHR_ADDR_WIDTH),
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.RESETW (1)
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) pipe_reg0 (
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.clk (clk),
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.reset (reset),
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.enable (~pipe_stall),
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.data_in ({
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init_fire || mshr_deq_fire || mem_rsp_fire || creq_fire,
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req_valid,
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init_enable,
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mshr_enable,
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mrsq_enable,
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creq_enable && ~creq_rw,
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creq_enable && creq_rw,
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init_enable ? `LINE_ADDR_WIDTH'(init_addr) : (mshr_deq_valid ? mshr_deq_addr : (mem_rsp_valid ? mem_rsp_addr : creq_addr)),
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wdata_sel,
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mshr_deq_valid ? mshr_wsel : creq_wsel,
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req_addr,
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req_data,
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creq_byteen,
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mshr_deq_valid ? mshr_wsel : creq_wsel,
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mshr_deq_valid ? mshr_idx : creq_idx,
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mshr_deq_valid ? mshr_pmask : creq_pmask,
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mshr_deq_valid ? mshr_tag : creq_tag,
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mshr_deq_id
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}),
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.data_out ({valid_st0, is_init_st0, is_mshr_st0, is_fill_st0, is_read_st0, is_write_st0, addr_st0, wdata_st0, wsel_st0, byteen_st0, req_idx_st0, pmask_st0, tag_st0, mshr_id_st0})
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.data_out ({valid_st0, is_init_st0, is_mshr_st0, is_fill_st0, is_read_st0, is_write_st0, addr_st0, data_st0, byteen_st0, wsel_st0, req_idx_st0, pmask_st0, tag_st0, mshr_id_st0})
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);
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if (UUID_WIDTH != 0) begin
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@ -283,20 +290,20 @@ module VX_cache_bank #(
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// we have a tag match
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assign is_hit_st0 = tag_match_st0;
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// ensure mshr reply never get a miss
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`RUNTIME_ASSERT (is_hit_st0 || ~do_mshr_st0, ("runtime error"));
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// ensure mshr replay always get a hit
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`RUNTIME_ASSERT (~do_mshr_st0 || is_hit_st0, ("runtime error: invalid mshr replay"));
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wire [MSHR_ADDR_WIDTH-1:0] mshr_id_a_st0 = is_read_st0 ? mshr_alloc_id : mshr_id_st0;
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wire [MSHR_ADDR_WIDTH-1:0] mshr_id_a_st0 = is_read_st0 ? mshr_alloc_id_st0 : mshr_id_st0;
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VX_pipe_register #(
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.DATAW (1 + 1 + 1 + 1 + 1 + 1 + NUM_WAYS + `LINE_ADDR_WIDTH + `LINE_WIDTH + NUM_PORTS * (WORD_SEL_WIDTH + WORD_SIZE + REQ_SEL_WIDTH + 1 + TAG_WIDTH) + MSHR_ADDR_WIDTH + 1),
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.DATAW (1 + 1 + 1 + 1 + 1 + `LINE_ADDR_WIDTH + `LINE_WIDTH + NUM_PORTS * (WORD_SIZE + WORD_SEL_WIDTH + REQ_SEL_WIDTH + 1 + TAG_WIDTH) + MSHR_ADDR_WIDTH + 1 + NUM_WAYS + 1),
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.RESETW (1)
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) pipe_reg1 (
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.clk (clk),
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.reset (reset),
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.enable (~pipe_stall),
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.data_in ({valid_st0, is_mshr_st0, is_fill_st0, is_read_st0, is_write_st0, is_hit_st0, way_sel_st0, addr_st0, wdata_st0, wsel_st0, byteen_st0, req_idx_st0, pmask_st0, tag_st0, mshr_id_a_st0, mshr_pending_st0}),
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.data_out ({valid_st1, is_mshr_st1, is_fill_st1, is_read_st1, is_write_st1, is_hit_st1, way_sel_st1, addr_st1, wdata_st1, wsel_st1, byteen_st1, req_idx_st1, pmask_st1, tag_st1, mshr_id_st1, mshr_pending_st1})
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.data_in ({valid_st0, is_mshr_st0, is_fill_st0, is_read_st0, is_write_st0, addr_st0, data_st0, byteen_st0, wsel_st0, req_idx_st0, pmask_st0, tag_st0, mshr_id_a_st0, is_hit_st0, way_sel_st0, mshr_pending_st0}),
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.data_out ({valid_st1, is_mshr_st1, is_fill_st1, is_read_st1, is_write_st1, addr_st1, data_st1, byteen_st1, wsel_st1, req_idx_st1, pmask_st1, tag_st1, mshr_id_st1, is_hit_st1, way_sel_st1, mshr_pending_st1})
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);
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if (UUID_WIDTH != 0) begin
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@ -318,16 +325,16 @@ module VX_cache_bank #(
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`UNUSED_VAR (do_write_miss_st1)
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// detect read during write data hazard
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assign rdw_hazard_st0 = do_fill_st0;
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// detect BRAM's read-during-write hazard
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assign rdw_hazard_st0 = do_fill_st0; // after a fill
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always @(posedge clk) begin
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rdw_hazard_st1 <= (do_read_st0 && do_write_hit_st1 && (addr_st0 == addr_st1))
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&& ~rdw_hazard_st1;
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&& ~rdw_hazard_st1; // after a write to same address
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end
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wire [NUM_PORTS-1:0][`WORD_WIDTH-1:0] creq_data_st1 = wdata_st1[0 +: NUM_PORTS * `WORD_WIDTH];
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`UNUSED_VAR (wdata_st1)
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wire [NUM_PORTS-1:0][`WORD_WIDTH-1:0] wdata_st1 = data_st1[0 +: NUM_PORTS * `WORD_WIDTH];
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wire [`LINE_WIDTH-1:0] fdata_st1 = data_st1;
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VX_cache_data #(
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.INSTANCE_ID (INSTANCE_ID),
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.BANK_ID (BANK_ID),
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@ -355,16 +362,16 @@ module VX_cache_bank #(
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.wsel (wsel_st1),
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.pmask (pmask_st1),
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.byteen (byteen_st1),
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.fill_data (wdata_st1),
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.write_data (creq_data_st1),
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.fill_data (fdata_st1),
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.write_data (wdata_st1),
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.read_data (rdata_st1)
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);
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wire [MSHR_SIZE-1:0] mshr_matches;
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wire mshr_allocate = do_read_st0 && ~pipe_stall;
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wire mshr_replay = do_fill_st0 && ~pipe_stall;
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wire mshr_lookup = mshr_allocate;
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wire mshr_release = do_read_hit_st1 && ~pipe_stall;
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wire [MSHR_SIZE-1:0] mshr_matches_st0;
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wire mshr_allocate_st0 = do_read_st0 && ~pipe_stall;
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wire mshr_replay_st0 = do_fill_st0 && ~pipe_stall;
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wire mshr_lookup_st0 = mshr_allocate_st0;
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wire mshr_release_st1 = do_read_hit_st1 && ~pipe_stall;
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VX_pending_size #(
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.SIZE (MSHR_SIZE)
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@ -372,13 +379,13 @@ module VX_cache_bank #(
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.clk (clk),
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.reset (reset),
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.incr (creq_fire && ~creq_rw),
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.decr (mshr_deq_fire || mshr_release),
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.decr (mshr_deq_fire || mshr_release_st1),
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.full (mshr_alm_full),
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`UNUSED_PIN (size),
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`UNUSED_PIN (empty)
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);
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`RESET_RELAY (miss_resrv_reset, reset);
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`RESET_RELAY (mshr_reset, reset);
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VX_cache_mshr #(
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.INSTANCE_ID (INSTANCE_ID),
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@ -393,24 +400,24 @@ module VX_cache_bank #(
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.TAG_WIDTH (TAG_WIDTH)
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) cache_mshr (
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.clk (clk),
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.reset (miss_resrv_reset),
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.reset (mshr_reset),
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.deq_req_uuid (req_uuid_sel),
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.lkp_req_uuid (req_uuid_st0),
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.rel_req_uuid (req_uuid_st1),
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// allocate
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.allocate_valid (mshr_allocate),
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.allocate_valid (mshr_allocate_st0),
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.allocate_addr (addr_st0),
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.allocate_data ({wsel_st0, tag_st0, req_idx_st0, pmask_st0}),
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.allocate_id (mshr_alloc_id),
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.allocate_id (mshr_alloc_id_st0),
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`UNUSED_PIN (allocate_ready),
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// lookup
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.lookup_find (mshr_lookup),
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.lookup_replay (mshr_replay),
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.lookup_find (mshr_lookup_st0),
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.lookup_replay (mshr_replay_st0),
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.lookup_addr (addr_st0),
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.lookup_matches (mshr_matches),
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.lookup_matches (mshr_matches_st0),
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// fill
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.fill_valid (mem_rsp_fire),
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@ -425,14 +432,14 @@ module VX_cache_bank #(
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.dequeue_ready (mshr_deq_ready),
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// release
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.release_valid (mshr_release),
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.release_valid (mshr_release_st1),
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.release_id (mshr_id_st1)
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);
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// ignore allocated id from mshr matches
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wire [MSHR_SIZE-1:0] lookup_matches;
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for (genvar i = 0; i < MSHR_SIZE; ++i) begin
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assign lookup_matches[i] = (i != mshr_alloc_id) && mshr_matches[i];
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assign lookup_matches[i] = (i != mshr_alloc_id_st0) && mshr_matches_st0[i];
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end
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assign mshr_pending_st0 = (| lookup_matches);
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@ -489,7 +496,7 @@ module VX_cache_bank #(
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assign mreq_pmask= pmask_st1;
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assign mreq_wsel = wsel_st1;
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assign mreq_byteen = byteen_st1;
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assign mreq_data = creq_data_st1;
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assign mreq_data = wdata_st1;
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VX_fifo_queue #(
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.DATAW (1 + `LINE_ADDR_WIDTH + MSHR_ADDR_WIDTH + NUM_PORTS * (1 + WORD_SIZE + WORD_SEL_WIDTH + `WORD_WIDTH)),
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