github-mirrors/vortex
1
0
Fork 0
mirror of https://github.com/vortexgpgpu/vortex.git synced 2025-04-23 21:39:10 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions

minor update

Browse source
This commit is contained in:
Blaise Tine 2024-08-15 05:11:19 -07:00
parent 98db249500
commit 2b22d47dd9
6 changed files with 32 additions and 32 deletions
Download patch file Download diff file Expand all files Collapse all files

20
hw/rtl/VX_define.vh
View file

@ -362,10 +362,10 @@
`define ASSIGN_VX_MEM_BUS_RO_IF(dst, src) \
assign dst.req_valid = src.req_valid; \
assign dst.req_data.rw = 0; \
assign dst.req_data.byteen = '0; \
assign dst.req_data.addr = src.req_data.addr; \
assign dst.req_data.flags = src.req_data.flags; \
assign dst.req_data.data = '0; \
assign dst.req_data.byteen = '0; \
assign dst.req_data.flags = src.req_data.flags; \
assign dst.req_data.tag = src.req_data.tag; \
assign src.req_ready = dst.req_ready; \
assign src.rsp_valid = dst.rsp_valid; \
@ -376,10 +376,10 @@
`define ASSIGN_VX_MEM_BUS_IF_X(dst, src, TD, TS) \
assign dst.req_valid = src.req_valid; \
assign dst.req_data.rw = src.req_data.rw; \
assign dst.req_data.byteen = src.req_data.byteen; \
assign dst.req_data.addr = src.req_data.addr; \
assign dst.req_data.flags = src.req_data.flags; \
assign dst.req_data.data = src.req_data.data; \
assign dst.req_data.byteen = src.req_data.byteen; \
assign dst.req_data.flags = src.req_data.flags; \
if (TD != TS) \
assign dst.req_data.tag = {src.req_data.tag, {(TD-TS){1'b0}}}; \
else \
@ -391,12 +391,12 @@
assign dst.rsp_ready = src.rsp_ready
`define ASSIGN_VX_LSU_MEM_IF(dst, src) \
assign dst.req_valid = src.req_valid; \
assign dst.req_data = src.req_data; \
assign src.req_ready = dst.req_ready; \
assign src.rsp_valid = dst.rsp_valid; \
assign src.rsp_data = dst.rsp_data; \
assign dst.rsp_ready = src.rsp_ready
assign dst.req_valid = src.req_valid; \
assign dst.req_data = src.req_data; \
assign src.req_ready = dst.req_ready; \
assign src.rsp_valid = dst.rsp_valid; \
assign src.rsp_data = dst.rsp_data; \
assign dst.rsp_ready = src.rsp_ready
`define BUFFER_DCR_BUS_IF(dst, src, enable) \
if (enable) begin \

8
hw/rtl/cache/VX_cache_bypass.sv vendored
View file

@ -129,20 +129,20 @@ module VX_cache_bypass #(
for (genvar i = 0; i < NUM_REQS; ++i) begin
assign core_req_nc_mux_in[i] = {
core_bus_in_if[i].req_data.rw,
core_bus_in_if[i].req_data.byteen,
core_bus_in_if[i].req_data.addr,
core_bus_in_if[i].req_data.flags,
core_bus_in_if[i].req_data.data,
core_bus_in_if[i].req_data.byteen,
core_bus_in_if[i].req_data.flags,
core_bus_in_if[i].req_data.tag
};
end
assign {
core_req_nc_sel_rw,
core_req_nc_sel_byteen,
core_req_nc_sel_addr,
core_req_nc_sel_flags,
core_req_nc_sel_data,
core_req_nc_sel_byteen,
core_req_nc_sel_flags,
core_req_nc_sel_tag
} = core_req_nc_mux_in[core_req_nc_idx];

16
hw/rtl/core/VX_lmem_unit.sv
View file

@ -65,10 +65,10 @@ module VX_lmem_unit import VX_gpu_pkg::*; #(
.data_in ({
lsu_mem_in_if[i].req_data.mask & ~is_addr_local_mask,
lsu_mem_in_if[i].req_data.rw,
lsu_mem_in_if[i].req_data.byteen,
lsu_mem_in_if[i].req_data.addr,
lsu_mem_in_if[i].req_data.flags,
lsu_mem_in_if[i].req_data.data,
lsu_mem_in_if[i].req_data.byteen,
lsu_mem_in_if[i].req_data.flags,
lsu_mem_in_if[i].req_data.tag
}),
.ready_in (req_global_ready),
@ -76,10 +76,10 @@ module VX_lmem_unit import VX_gpu_pkg::*; #(
.data_out ({
lsu_mem_out_if[i].req_data.mask,
lsu_mem_out_if[i].req_data.rw,
lsu_mem_out_if[i].req_data.byteen,
lsu_mem_out_if[i].req_data.addr,
lsu_mem_out_if[i].req_data.flags,
lsu_mem_out_if[i].req_data.data,
lsu_mem_out_if[i].req_data.byteen,
lsu_mem_out_if[i].req_data.flags,
lsu_mem_out_if[i].req_data.tag
}),
.ready_out (lsu_mem_out_if[i].req_ready)
@ -96,10 +96,10 @@ module VX_lmem_unit import VX_gpu_pkg::*; #(
.data_in ({
lsu_mem_in_if[i].req_data.mask & is_addr_local_mask,
lsu_mem_in_if[i].req_data.rw,
lsu_mem_in_if[i].req_data.byteen,
lsu_mem_in_if[i].req_data.addr,
lsu_mem_in_if[i].req_data.flags,
lsu_mem_in_if[i].req_data.data,
lsu_mem_in_if[i].req_data.byteen,
lsu_mem_in_if[i].req_data.flags,
lsu_mem_in_if[i].req_data.tag
}),
.ready_in (req_local_ready),
@ -107,10 +107,10 @@ module VX_lmem_unit import VX_gpu_pkg::*; #(
.data_out ({
lsu_lmem_if[i].req_data.mask,
lsu_lmem_if[i].req_data.rw,
lsu_lmem_if[i].req_data.byteen,
lsu_lmem_if[i].req_data.addr,
lsu_lmem_if[i].req_data.flags,
lsu_lmem_if[i].req_data.data,
lsu_lmem_if[i].req_data.byteen,
lsu_lmem_if[i].req_data.flags,
lsu_lmem_if[i].req_data.tag
}),
.ready_out (lsu_lmem_if[i].req_ready)

12
hw/rtl/core/VX_lsu_adapter.sv
View file

@ -44,10 +44,10 @@ module VX_lsu_adapter import VX_gpu_pkg::*; #(
for (genvar i = 0; i < NUM_LANES; ++i) begin
assign req_data_in[i] = {
lsu_mem_if.req_data.rw,
lsu_mem_if.req_data.byteen[i],
lsu_mem_if.req_data.addr[i],
lsu_mem_if.req_data.flags[i],
lsu_mem_if.req_data.data[i]
lsu_mem_if.req_data.data[i],
lsu_mem_if.req_data.byteen[i],
lsu_mem_if.req_data.flags[i]
};
end
@ -55,10 +55,10 @@ module VX_lsu_adapter import VX_gpu_pkg::*; #(
assign mem_bus_if[i].req_valid = req_valid_out[i];
assign {
mem_bus_if[i].req_data.rw,
mem_bus_if[i].req_data.byteen,
mem_bus_if[i].req_data.addr,
mem_bus_if[i].req_data.flags,
mem_bus_if[i].req_data.data
mem_bus_if[i].req_data.data,
mem_bus_if[i].req_data.byteen,
mem_bus_if[i].req_data.flags
} = req_data_out[i];
assign mem_bus_if[i].req_data.tag = req_tag_out[i];
assign req_ready_out[i] = mem_bus_if[i].req_ready;

4
hw/rtl/interfaces/VX_lsu_mem_if.sv
View file

@ -25,10 +25,10 @@ interface VX_lsu_mem_if #(
typedef struct packed {
logic rw;
logic [NUM_LANES-1:0] mask;
logic [NUM_LANES-1:0][DATA_SIZE-1:0] byteen;
logic [NUM_LANES-1:0][ADDR_WIDTH-1:0] addr;
logic [NUM_LANES-1:0][FLAGS_WIDTH-1:0] flags;
logic [NUM_LANES-1:0][DATA_SIZE*8-1:0] data;
logic [NUM_LANES-1:0][DATA_SIZE-1:0] byteen;
logic [NUM_LANES-1:0][FLAGS_WIDTH-1:0] flags;
logic [TAG_WIDTH-1:0] tag;
} req_data_t;

4
hw/rtl/mem/VX_mem_bus_if.sv
View file

@ -23,10 +23,10 @@ interface VX_mem_bus_if #(
typedef struct packed {
logic rw;
logic [DATA_SIZE-1:0] byteen;
logic [ADDR_WIDTH-1:0] addr;
logic [FLAGS_WIDTH-1:0] flags;
logic [DATA_SIZE*8-1:0] data;
logic [DATA_SIZE-1:0] byteen;
logic [FLAGS_WIDTH-1:0] flags;
logic [TAG_WIDTH-1:0] tag;
} req_data_t;