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fixed trace log formatting

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This commit is contained in:
Blaise Tine 2024-07-30 12:05:36 -07:00
parent abf8d2c51a
commit 2bc8a881b6
10 changed files with 58 additions and 58 deletions
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10
sim/common/mem.cpp
View file

@ -48,7 +48,7 @@ void RamMemDevice::read(void* data, uint64_t addr, uint64_t size) {
if ((addr & (wordSize_-1))
|| (addr_end & (wordSize_-1))
|| (addr_end <= contents_.size())) {
std::cout << "lookup of 0x" << std::hex << (addr_end-1) << " failed.\n";
std::cout << "lookup of 0x" << std::hex << (addr_end-1) << std::dec << " failed.\n";
throw BadAddress();
}
@ -63,7 +63,7 @@ void RamMemDevice::write(const void* data, uint64_t addr, uint64_t size) {
if ((addr & (wordSize_-1))
|| (addr_end & (wordSize_-1))
|| (addr_end <= contents_.size())) {
std::cout << "lookup of 0x" << std::hex << (addr_end-1) << " failed.\n";
std::cout << "lookup of 0x" << std::hex << (addr_end-1) << std::dec << " failed.\n";
throw BadAddress();
}
@ -104,7 +104,7 @@ void MemoryUnit::ADecoder::map(uint64_t start, uint64_t end, MemDevice &md) {
void MemoryUnit::ADecoder::read(void* data, uint64_t addr, uint64_t size) {
mem_accessor_t ma;
if (!this->lookup(addr, size, &ma)) {
std::cout << "lookup of 0x" << std::hex << addr << " failed.\n";
std::cout << "lookup of 0x" << std::hex << addr << std::dec << " failed.\n";
throw BadAddress();
}
ma.md->read(data, ma.addr, size);
@ -113,7 +113,7 @@ void MemoryUnit::ADecoder::read(void* data, uint64_t addr, uint64_t size) {
void MemoryUnit::ADecoder::write(const void* data, uint64_t addr, uint64_t size) {
mem_accessor_t ma;
if (!this->lookup(addr, size, &ma)) {
std::cout << "lookup of 0x" << std::hex << addr << " failed.\n";
std::cout << "lookup of 0x" << std::hex << addr << std::dec << " failed.\n";
throw BadAddress();
}
ma.md->write(data, ma.addr, size);
@ -252,7 +252,7 @@ bool ACLManager::check(uint64_t addr, uint64_t size, int flags) const {
while (it != acl_map_.end() && it->first < end) {
if (it->second.end > addr) {
if ((it->second.flags & flags) != flags) {
std::cout << "Memory access violation from 0x" << std::hex << addr << " to 0x" << end << ", curent flags=" << it->second.flags << ", access flags=" << flags << std::endl;
std::cout << "Memory access violation from 0x" << std::hex << addr << " to 0x" << end << ", curent flags=" << it->second.flags << ", access flags=" << flags << std::dec << std::endl;
return false; // Overlapping entry is missing at least one required flag bit
}
addr = it->second.end; // Move to the end of the current matching range

6
sim/opaesim/opae_sim.cpp
View file

@ -380,7 +380,7 @@ private:
device_->vcp2af_sRxPort_c0_hdr_resp_type = 0;
memcpy(device_->vcp2af_sRxPort_c0_data, cci_rd_it->data.data(), CACHE_BLOCK_SIZE);
device_->vcp2af_sRxPort_c0_hdr_mdata = cci_rd_it->mdata;
/*printf("%0ld: [sim] CCI Rd Rsp: addr=%ld, mdata=%d, data=", timestamp, cci_rd_it->addr, cci_rd_it->mdata);
/*printf("%0ld: [sim] CCI Rd Rsp: addr=0x%lx, mdata=0x%x, data=0x", timestamp, cci_rd_it->addr, cci_rd_it->mdata);
for (int i = 0; i < CACHE_BLOCK_SIZE; ++i)
printf("%02x", cci_rd_it->data[CACHE_BLOCK_SIZE-1-i]);
printf("\n");*/
@ -398,7 +398,7 @@ private:
cci_req.mdata = device_->af2cp_sTxPort_c0_hdr_mdata;
auto host_ptr = (uint64_t*)(device_->af2cp_sTxPort_c0_hdr_address * CACHE_BLOCK_SIZE);
memcpy(cci_req.data.data(), host_ptr, CACHE_BLOCK_SIZE);
//printf("%0ld: [sim] CCI Rd Req: addr=%ld, mdata=%d\n", timestamp, device_->af2cp_sTxPort_c0_hdr_address, cci_req.mdata);
//printf("%0ld: [sim] CCI Rd Req: addr=0x%lx, mdata=0x%x\n", timestamp, device_->af2cp_sTxPort_c0_hdr_address, cci_req.mdata);
cci_reads_.emplace_back(cci_req);
}
@ -453,7 +453,7 @@ private:
}
}
/*printf("%0ld: [sim] MEM Wr Req: bank=%d, addr=%x, data=", timestamp, b, byte_addr);
/*printf("%0ld: [sim] MEM Wr Req: bank=%d, 0x%x, data=0x", timestamp, b, byte_addr);
for (int i = 0; i < MEM_BLOCK_SIZE; i++) {
printf("%02x", data[(MEM_BLOCK_SIZE-1)-i]);
}

4
sim/simx/core.cpp
View file

@ -215,7 +215,7 @@ void Core::fetch() {
auto& mem_rsp = icache_rsp_port.front();
auto trace = pending_icache_.at(mem_rsp.tag);
decode_latch_.push(trace);
DT(3, "icache-rsp: addr=0x" << std::hex << trace->PC << ", tag=" << mem_rsp.tag << ", " << *trace);
DT(3, "icache-rsp: addr=0x" << std::hex << trace->PC << ", tag=0x" << mem_rsp.tag << std::dec << ", " << *trace);
pending_icache_.release(mem_rsp.tag);
icache_rsp_port.pop();
--pending_ifetches_;
@ -232,7 +232,7 @@ void Core::fetch() {
mem_req.cid = trace->cid;
mem_req.uuid = trace->uuid;
icache_req_ports.at(0).push(mem_req, 2);
DT(3, "icache-req: addr=0x" << std::hex << mem_req.addr << ", tag=" << mem_req.tag << ", " << *trace);
DT(3, "icache-req: addr=0x" << std::hex << mem_req.addr << ", tag=0x" << mem_req.tag << std::dec << ", " << *trace);
fetch_latch_.pop();
++perf_stats_.ifetches;
++pending_ifetches_;

8
sim/simx/dcrs.cpp
View file

@ -1,10 +1,10 @@
// Copyright © 2019-2023
//
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
@ -16,13 +16,13 @@
using namespace vortex;
void DCRS::write(uint32_t addr, uint32_t value) {
void DCRS::write(uint32_t addr, uint32_t value) {
if (addr >= VX_DCR_BASE_STATE_BEGIN
&& addr < VX_DCR_BASE_STATE_END) {
base_dcrs.write(addr, value);
return;
}
std::cout << std::hex << "Error: invalid global DCR addr=0x" << addr << std::endl;
std::cout << "Error: invalid global DCR addr=0x" << std::hex << addr << std::dec << std::endl;
std::abort();
}

10
sim/simx/decode.cpp
View file

@ -416,19 +416,19 @@ std::ostream &operator<<(std::ostream &os, const Instr &instr) {
int sep = 0;
if (instr.getRDType() != RegType::None) {
if (sep++ != 0) { os << ", "; } else { os << " "; }
os << instr.getRDType() << std::dec << instr.getRDest();
os << instr.getRDType() << instr.getRDest();
}
for (uint32_t i = 0; i < instr.getNRSrc(); ++i) {
if (sep++ != 0) { os << ", "; } else { os << " "; }
if (instr.getRSType(i) != RegType::None) {
os << instr.getRSType(i) << std::dec << instr.getRSrc(i);
os << instr.getRSType(i) << instr.getRSrc(i);
} else {
os << "0x" << std::hex << instr.getRSrc(0);
os << "0x" << std::hex << instr.getRSrc(0) << std::dec;
}
}
if (instr.hasImm()) {
if (sep++ != 0) { os << ", "; } else { os << " "; }
os << "0x" << std::hex << instr.getImm();
os << "0x" << std::hex << instr.getImm() << std::dec;
}
return os;
}
@ -450,7 +450,7 @@ std::shared_ptr<Instr> Emulator::decode(uint32_t code) const {
auto op_it = sc_instTable.find(op);
if (op_it == sc_instTable.end()) {
std::cout << std::hex << "Error: invalid opcode: 0x" << static_cast<int>(op) << std::endl;
std::cout << "Error: invalid opcode: 0x" << std::hex << static_cast<int>(op) << std::dec << std::endl;
return nullptr;
}

26
sim/simx/emulator.cpp
View file

@ -138,7 +138,7 @@ instr_trace_t* Emulator::step() {
// process pending wspawn
if (wspawn_.valid && active_warps_.count() == 1) {
DP(3, "*** Activate " << (wspawn_.num_warps-1) << " warps at PC: " << std::hex << wspawn_.nextPC);
DP(3, "*** Activate " << (wspawn_.num_warps-1) << " warps at PC: " << std::hex << wspawn_.nextPC << std::dec);
for (uint32_t i = 1; i < wspawn_.num_warps; ++i) {
auto& warp = warps_.at(i);
warp.PC = wspawn_.nextPC;
@ -185,11 +185,11 @@ instr_trace_t* Emulator::step() {
// Decode
auto instr = this->decode(instr_code);
if (!instr) {
std::cout << std::hex << "Error: invalid instruction 0x" << instr_code << ", at PC=0x" << warp.PC << " (#" << std::dec << uuid << ")" << std::endl;
std::cout << "Error: invalid instruction 0x" << std::hex << instr_code << ", at PC=0x" << warp.PC << " (#" << std::dec << uuid << ")" << std::endl;
std::abort();
}
DP(1, "Instr 0x" << std::hex << instr_code << ": " << *instr);
DP(1, "Instr 0x" << std::hex << instr_code << ": " << std::dec << *instr);
// Create trace
auto trace = new instr_trace_t(uuid, arch_);
@ -199,17 +199,17 @@ instr_trace_t* Emulator::step() {
DP(5, "Register state:");
for (uint32_t i = 0; i < MAX_NUM_REGS; ++i) {
DPN(5, " %r" << std::setfill('0') << std::setw(2) << std::dec << i << ':');
DPN(5, " %r" << std::setfill('0') << std::setw(2) << i << ':' << std::hex);
// Integer register file
for (uint32_t j = 0; j < arch_.num_threads(); ++j) {
DPN(5, ' ' << std::setfill('0') << std::setw(XLEN/4) << std::hex << warp.ireg_file.at(j).at(i) << std::setfill(' ') << ' ');
DPN(5, ' ' << std::setfill('0') << std::setw(XLEN/4) << warp.ireg_file.at(j).at(i) << std::setfill(' ') << ' ');
}
DPN(5, '|');
// Floating point register file
for (uint32_t j = 0; j < arch_.num_threads(); ++j) {
DPN(5, ' ' << std::setfill('0') << std::setw(16) << std::hex << warp.freg_file.at(j).at(i) << std::setfill(' ') << ' ');
DPN(5, ' ' << std::setfill('0') << std::setw(16) << warp.freg_file.at(j).at(i) << std::setfill(' ') << ' ');
}
DPN(5, std::endl);
DPN(5, std::dec << std::endl);
}
return trace;
@ -292,7 +292,7 @@ void Emulator::dcache_read(void *data, uint64_t addr, uint32_t size) {
mmu_.read(data, addr, size, 0);
}
DPH(2, "Mem Read: addr=0x" << std::hex << addr << ", data=0x" << ByteStream(data, size) << " (size=" << size << ", type=" << type << ")" << std::endl);
DPH(2, "Mem Read: addr=0x" << std::hex << addr << ", data=0x" << ByteStream(data, size) << std::dec << " (size=" << size << ", type=" << type << ")" << std::endl);
}
void Emulator::dcache_write(const void* data, uint64_t addr, uint32_t size) {
@ -307,7 +307,7 @@ void Emulator::dcache_write(const void* data, uint64_t addr, uint32_t size) {
mmu_.write(data, addr, size, 0);
}
}
DPH(2, "Mem Write: addr=0x" << std::hex << addr << ", data=0x" << ByteStream(data, size) << " (size=" << size << ", type=" << type << ")" << std::endl);
DPH(2, "Mem Write: addr=0x" << std::hex << addr << ", data=0x" << ByteStream(data, size) << std::dec << " (size=" << size << ", type=" << type << ")" << std::endl);
}
void Emulator::dcache_amo_reserve(uint64_t addr) {
@ -333,7 +333,7 @@ void Emulator::writeToStdOut(const void* data, uint64_t addr, uint32_t size) {
char c = *(char*)data;
ss_buf << c;
if (c == '\n') {
std::cout << std::dec << "#" << tid << ": " << ss_buf.str() << std::flush;
std::cout << "#" << tid << ": " << ss_buf.str() << std::flush;
ss_buf.str("");
}
}
@ -458,12 +458,12 @@ Word Emulator::get_csr(uint32_t addr, uint32_t tid, uint32_t wid) {
}
} break;
default: {
std::cout << std::dec << "Error: invalid MPM CLASS: value=" << perf_class << std::endl;
std::cout << "Error: invalid MPM CLASS: value=" << perf_class << std::endl;
std::abort();
} break;
}
} else {
std::cout << std::hex << "Error: invalid CSR read addr=0x" << addr << std::endl;
std::cout << "Error: invalid CSR read addr=0x"<< std::hex << addr << std::dec << std::endl;
std::abort();
}
}
@ -498,7 +498,7 @@ void Emulator::set_csr(uint32_t addr, Word value, uint32_t tid, uint32_t wid) {
case VX_CSR_MCAUSE:
break;
default: {
std::cout << std::hex << "Error: invalid CSR write addr=0x" << addr << ", value=0x" << value << std::endl;
std::cout << "Error: invalid CSR write addr=0x" << std::hex << addr << ", value=0x" << value << std::dec << std::endl;
std::abort();
}
}

20
sim/simx/execute.cpp
View file

@ -102,7 +102,7 @@ void Emulator::execute(const Instr &instr, uint32_t wid, instr_trace_t *trace) {
auto reg = instr.getRSrc(i);
switch (type) {
case RegType::Integer:
DPH(2, "Src" << std::dec << i << " Reg: " << type << std::dec << reg << "={");
DPH(2, "Src" << i << " Reg: " << type << reg << "={");
for (uint32_t t = 0; t < num_threads; ++t) {
if (t) DPN(2, ", ");
if (!warp.tmask.test(t)) {
@ -110,12 +110,12 @@ void Emulator::execute(const Instr &instr, uint32_t wid, instr_trace_t *trace) {
continue;
}
rsdata[t][i].u = warp.ireg_file.at(t)[reg];
DPN(2, "0x" << std::hex << rsdata[t][i].i);
DPN(2, "0x" << std::hex << rsdata[t][i].i << std::dec);
}
DPN(2, "}" << std::endl);
break;
case RegType::Float:
DPH(2, "Src" << std::dec << i << " Reg: " << type << std::dec << reg << "={");
DPH(2, "Src" << i << " Reg: " << type << reg << "={");
for (uint32_t t = 0; t < num_threads; ++t) {
if (t) DPN(2, ", ");
if (!warp.tmask.test(t)) {
@ -123,7 +123,7 @@ void Emulator::execute(const Instr &instr, uint32_t wid, instr_trace_t *trace) {
continue;
}
rsdata[t][i].u64 = warp.freg_file.at(t)[reg];
DPN(2, "0x" << std::hex << rsdata[t][i].f);
DPN(2, "0x" << std::hex << rsdata[t][i].f << std::dec);
}
DPN(2, "}" << std::endl);
break;
@ -633,7 +633,7 @@ void Emulator::execute(const Instr &instr, uint32_t wid, instr_trace_t *trace) {
all_taken = curr_taken;
} else {
if (all_taken != curr_taken) {
std::cout << "divergent branch! PC=0x" << std::hex << warp.PC << " (#" << std::dec << trace->uuid << ")\n" << std::flush;
std::cout << "divergent branch! PC=0x" << std::hex << warp.PC << std::dec << " (#" << trace->uuid << ")\n" << std::flush;
std::abort();
}
}
@ -1338,7 +1338,7 @@ void Emulator::execute(const Instr &instr, uint32_t wid, instr_trace_t *trace) {
bool is_divergent = then_tmask.any() && else_tmask.any();
if (is_divergent) {
if (stack_size == ipdom_size_) {
std::cout << "IPDOM stack is full! size=" << std::dec << stack_size << ", PC=0x" << std::hex << warp.PC << " (#" << std::dec << trace->uuid << ")\n" << std::flush;
std::cout << "IPDOM stack is full! size=" << stack_size << ", PC=0x" << std::hex << warp.PC << std::dec << " (#" << trace->uuid << ")\n" << std::flush;
std::abort();
}
// set new thread mask to the larger set
@ -1425,7 +1425,7 @@ void Emulator::execute(const Instr &instr, uint32_t wid, instr_trace_t *trace) {
switch (type) {
case RegType::Integer:
if (rdest) {
DPH(2, "Dest Reg: " << type << std::dec << rdest << "={");
DPH(2, "Dest Reg: " << type << rdest << "={");
for (uint32_t t = 0; t < num_threads; ++t) {
if (t) DPN(2, ", ");
if (!warp.tmask.test(t)) {
@ -1433,7 +1433,7 @@ void Emulator::execute(const Instr &instr, uint32_t wid, instr_trace_t *trace) {
continue;
}
warp.ireg_file.at(t)[rdest] = rddata[t].i;
DPN(2, "0x" << std::hex << rddata[t].i);
DPN(2, "0x" << std::hex << rddata[t].i << std::dec);
}
DPN(2, "}" << std::endl);
trace->dst_reg = {type, rdest};
@ -1444,7 +1444,7 @@ void Emulator::execute(const Instr &instr, uint32_t wid, instr_trace_t *trace) {
}
break;
case RegType::Float:
DPH(2, "Dest Reg: " << type << std::dec << rdest << "={");
DPH(2, "Dest Reg: " << type << rdest << "={");
for (uint32_t t = 0; t < num_threads; ++t) {
if (t) DPN(2, ", ");
if (!warp.tmask.test(t)) {
@ -1452,7 +1452,7 @@ void Emulator::execute(const Instr &instr, uint32_t wid, instr_trace_t *trace) {
continue;
}
warp.freg_file.at(t)[rdest] = rddata[t].u64;
DPN(2, "0x" << std::hex << rddata[t].f);
DPN(2, "0x" << std::hex << rddata[t].f << std::dec);
}
DPN(2, "}" << std::endl);
trace->dst_reg = {type, rdest};

8
sim/simx/instr_trace.h
View file

@ -146,14 +146,14 @@ inline std::ostream &operator<<(std::ostream &os, const instr_trace_t& trace) {
for (uint32_t i = 0, n = trace.arch.num_threads(); i < n; ++i) {
os << trace.tmask.test(i);
}
os << ", PC=0x" << std::hex << trace.PC;
os << ", PC=0x" << std::hex << trace.PC << std::dec;
os << ", wb=" << trace.wb;
if (trace.dst_reg.type != RegType::None) {
os << ", rd=" << trace.dst_reg.type << std::dec << trace.dst_reg.idx;
os << ", rd=" << trace.dst_reg.type << trace.dst_reg.idx;
}
for (uint32_t i = 0; i < trace.src_regs.size(); ++i) {
if (trace.src_regs[i].type != RegType::None) {
os << ", rs" << i << "=" << trace.src_regs[i].type << std::dec << trace.src_regs[i].idx;
os << ", rs" << i << "=" << trace.src_regs[i].type << trace.src_regs[i].idx;
}
}
os << ", ex=" << trace.fu_type;
@ -162,7 +162,7 @@ inline std::ostream &operator<<(std::ostream &os, const instr_trace_t& trace) {
os << ", sop=" << trace.sop;
os << ", eop=" << trace.eop;
}
os << " (#" << std::dec << trace.uuid << ")";
os << " (#" << trace.uuid << ")";
return os;
}

4
sim/simx/local_mem.cpp
View file

@ -52,13 +52,13 @@ public:
void read(void* data, uint64_t addr, uint32_t size) {
auto s_addr = to_local_addr(addr);
DPH(3, "Local Mem addr=0x" << std::hex << s_addr << std::endl);
DPH(3, "Local Mem addr=0x" << std::hex << s_addr << std::dec << std::endl);
ram_.read(data, s_addr, size);
}
void write(const void* data, uint64_t addr, uint32_t size) {
auto s_addr = to_local_addr(addr);
DPH(3, "Local Mem addr=0x" << std::hex << s_addr << std::endl);
DPH(3, "Local Mem addr=0x" << std::hex << s_addr << std::dec << std::endl);
ram_.write(data, s_addr, size);
}

20
sim/simx/types.h
View file

@ -264,14 +264,14 @@ inline std::ostream &operator<<(std::ostream &os, const LsuReq& req) {
for (size_t i = 0; i < req.mask.size(); ++i) {
os << "addr" << i << "=";
if (req.mask.test(i)) {
os << "0x" << std::hex << req.addrs.at(i);
os << "0x" << std::hex << req.addrs.at(i) << std::dec;
} else {
os << "-";
}
os << ", ";
}
os << std::dec << "tag=" << req.tag << ", cid=" << req.cid;
os << " (#" << std::dec << req.uuid << ")";
os << "tag=0x" << std::hex << req.tag << std::dec << ", cid=" << req.cid;
os << " (#" << req.uuid << ")";
return os;
}
@ -292,8 +292,8 @@ struct LsuRsp {
};
inline std::ostream &operator<<(std::ostream &os, const LsuRsp& rsp) {
os << "mask=" << rsp.mask << ", tag=" << rsp.tag << ", cid=" << rsp.cid;
os << " (#" << std::dec << rsp.uuid << ")";
os << "mask=" << rsp.mask << ", tag=0x" << std::hex << rsp.tag << std::dec << ", cid=" << rsp.cid;
os << " (#" << rsp.uuid << ")";
return os;
}
@ -324,9 +324,9 @@ struct MemReq {
inline std::ostream &operator<<(std::ostream &os, const MemReq& req) {
os << "rw=" << req.write << ", ";
os << "addr=0x" << std::hex << req.addr << ", type=" << req.type;
os << std::dec << ", tag=" << req.tag << ", cid=" << req.cid;
os << " (#" << std::dec << req.uuid << ")";
os << "addr=0x" << std::hex << req.addr << std::dec << ", type=" << req.type;
os << ", tag=0x" << std::hex << req.tag << std::dec << ", cid=" << req.cid;
os << " (#" << req.uuid << ")";
return os;
}
@ -345,8 +345,8 @@ struct MemRsp {
};
inline std::ostream &operator<<(std::ostream &os, const MemRsp& rsp) {
os << "tag=" << rsp.tag << ", cid=" << rsp.cid;
os << " (#" << std::dec << rsp.uuid << ")";
os << "tag=0x" << std::hex << rsp.tag << std::dec << ", cid=" << rsp.cid;
os << " (#" << rsp.uuid << ")";
return os;
}