minor update

hw/rtl/cache/VX_bank_flush.sv

@@ -55,7 +55,8 @@ module VX_bank_flush #(
     always @(*) begin
         state_n = state;
         case (state)
-            STATE_IDLE: begin
+            //STATE_IDLE:
+            default : begin
                 if (flush_begin) begin
                     state_n = STATE_WAIT1;
                 end

hw/rtl/cache/VX_cache_flush.sv

@@ -128,7 +128,8 @@ module VX_cache_flush #(
         lock_released_n = lock_released;
         flush_uuid_n = flush_uuid_r;
         case (state)
-            STATE_IDLE: begin
+            //STATE_IDLE:
+            default: begin
                 if (flush_req_enable) begin
                     state_n = (BANK_SEL_LATENCY != 0) ? STATE_WAIT1 : STATE_FLUSH;
                     for (integer i = NUM_REQS-1; i >= 0; --i) begin

hw/rtl/libs/VX_dp_ram.sv

@@ -70,7 +70,7 @@ module VX_dp_ram #(
                             end \
                         end
     `define RAM_NO_RWCHECK (* altera_attribute = RAM_NO_RWCHECK_VALUE *)
-`elif VIVADO
+`elsif VIVADO
     localparam `STRING RAM_STYLE_VALUE = USE_BRAM ? "block" : (LUTRAM ? "distributed" : "auto");
     localparam `STRING RAM_NO_RWCHECK_VALUE = NO_RWCHECK ? "no" : "auto";
     `define RAM_ARRAY (* ram_style = RAM_STYLE_VALUE *) reg [DATAW-1:0] ram [0:SIZE-1];