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AXI adapter bug fix
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This commit is contained in:
tinebp 2025-01-21 06:14:22 -08:00
parent fb4527fe95
commit 2c940cf509
3 changed files with 91 additions and 139 deletions
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5
hw/rtl/afu/xrt/VX_afu_wrap.sv
View file

@ -218,7 +218,7 @@ module VX_afu_wrap #(
end
for (genvar i = 0; i < C_M_AXI_MEM_NUM_BANKS; ++i) begin : g_m_axi_wr_rsp_fire
assign m_axi_wr_rsp_fire[i] = m_axi_mem_bvalid_a[i] & m_axi_mem_bready_a[i];
assign m_axi_wr_rsp_fire[i] = m_axi_mem_bvalid_a[i] && m_axi_mem_bready_a[i];
end
`POP_COUNT(cur_wr_reqs, m_axi_wr_req_fire);
@ -468,6 +468,9 @@ module VX_afu_wrap #(
if (m_axi_mem_wvalid_a[i] && m_axi_mem_wready_a[i]) begin
`TRACE(2, ("%t: AXI Wr Req [%0d]: strb=0x%h, data=0x%h\n", $time, i, m_axi_mem_wstrb_a[i], m_axi_mem_wdata_a[i]))
end
if (m_axi_mem_bvalid_a[i] && m_axi_mem_bready_a[i]) begin
`TRACE(2, ("%t: AXI Wr Rsp [%0d]: id=0x%0h\n", $time, i, m_axi_mem_bid_a[i]))
end
if (m_axi_mem_arvalid_a[i] && m_axi_mem_arready_a[i]) begin
`TRACE(2, ("%t: AXI Rd Req [%0d]: addr=0x%0h, id=0x%0h\n", $time, i, m_axi_mem_araddr_a[i], m_axi_mem_arid_a[i]))
end

195
hw/rtl/libs/VX_axi_adapter.sv
View file

@ -109,8 +109,8 @@ module VX_axi_adapter #(
localparam READ_FULL_TAG_WIDTH = READ_TAG_WIDTH + NUM_PORTS_IN_BITS;
localparam WRITE_TAG_WIDTH = `MIN(TAG_WIDTH_IN, TAG_WIDTH_OUT);
localparam DST_TAG_WIDTH = `MAX(READ_FULL_TAG_WIDTH, WRITE_TAG_WIDTH);
localparam ARB_TAG_WIDTH = `MAX(READ_TAG_WIDTH, WRITE_TAG_WIDTH);
localparam ARB_DATAW = 1 + BANK_ADDR_WIDTH + DATA_SIZE + DATA_WIDTH + ARB_TAG_WIDTH;
localparam XBAR_TAG_WIDTH = `MAX(READ_TAG_WIDTH, WRITE_TAG_WIDTH);
localparam REQ_XBAR_DATAW = 1 + BANK_ADDR_WIDTH + DATA_SIZE + DATA_WIDTH + XBAR_TAG_WIDTH;
localparam RSP_XBAR_DATAW = DATA_WIDTH + READ_TAG_WIDTH;
`STATIC_ASSERT ((DST_ADDR_WDITH >= ADDR_WIDTH_IN), ("invalid address width: current=%0d, expected=%0d", DST_ADDR_WDITH, ADDR_WIDTH_IN))
@ -174,115 +174,85 @@ module VX_axi_adapter #(
end
end
// Request ack
// AXI request handling
wire [NUM_BANKS_OUT-1:0][NUM_PORTS_IN-1:0] arb_ready_in;
wire [NUM_PORTS_IN-1:0] req_xbar_valid_in;
wire [NUM_PORTS_IN-1:0][REQ_XBAR_DATAW-1:0] req_xbar_data_in;
wire [NUM_PORTS_IN-1:0] req_xbar_ready_in;
if (NUM_PORTS_IN > 1) begin : g_multi_inputs
wire [NUM_PORTS_IN-1:0][NUM_BANKS_OUT-1:0] arb_ready_in_w;
VX_transpose #(
.N (NUM_BANKS_OUT),
.M (NUM_PORTS_IN)
) rdy_in_transpose (
.data_in (arb_ready_in),
.data_out (arb_ready_in_w)
);
for (genvar i = 0; i < NUM_PORTS_IN; ++i) begin : g_ready_in
assign mem_req_ready[i] = | arb_ready_in_w[i];
end
end else begin : g_single_input
assign mem_req_ready[0] = arb_ready_in[req_bank_sel[0]][0];
wire [NUM_BANKS_OUT-1:0] req_xbar_valid_out;
wire [NUM_BANKS_OUT-1:0][REQ_XBAR_DATAW-1:0] req_xbar_data_out;
wire [NUM_BANKS_OUT-1:0][NUM_PORTS_IN_WIDTH-1:0] req_xbar_sel_out;
wire [NUM_BANKS_OUT-1:0] req_xbar_ready_out;
for (genvar i = 0; i < NUM_PORTS_IN; ++i) begin : g_req_xbar_data_in
wire tag_ready = mem_req_rw[i] || mem_rd_req_tag_ready[i];
wire [XBAR_TAG_WIDTH-1:0] tag_value = mem_req_rw[i] ? XBAR_TAG_WIDTH'(mem_req_tag[i]) : XBAR_TAG_WIDTH'(mem_rd_req_tag[i]);
assign req_xbar_valid_in[i] = mem_req_valid[i] && tag_ready;
assign req_xbar_data_in[i] = {mem_req_rw[i], req_bank_addr[i], mem_req_byteen[i], mem_req_data[i], tag_value};
assign mem_req_ready[i] = req_xbar_ready_in[i] && tag_ready;
end
// AXI request handling
VX_stream_xbar #(
.NUM_INPUTS (NUM_PORTS_IN),
.NUM_OUTPUTS(NUM_BANKS_OUT),
.DATAW (REQ_XBAR_DATAW),
.ARBITER (ARBITER),
.OUT_BUF (REQ_OUT_BUF)
) req_xbar (
.clk (clk),
.reset (reset),
.sel_in (req_bank_sel),
.valid_in (req_xbar_valid_in),
.data_in (req_xbar_data_in),
.ready_in (req_xbar_ready_in),
.valid_out (req_xbar_valid_out),
.data_out (req_xbar_data_out),
.ready_out (req_xbar_ready_out),
.sel_out (req_xbar_sel_out),
`UNUSED_PIN (collisions)
);
for (genvar i = 0; i < NUM_BANKS_OUT; ++i) begin : g_axi_write_req
wire [BANK_ADDR_WIDTH-1:0] arb_addr_out, buf_addr_r_out, buf_addr_w_out;
wire [ARB_TAG_WIDTH-1:0] arb_tag_out;
wire [WRITE_TAG_WIDTH-1:0] buf_tag_w_out;
wire [READ_FULL_TAG_WIDTH-1:0] arb_tag_r_out, buf_tag_r_out;
wire [NUM_PORTS_IN_WIDTH-1:0] arb_sel_out;
wire [DATA_WIDTH-1:0] arb_data_out;
wire [DATA_SIZE-1:0] arb_byteen_out;
wire arb_valid_out, arb_ready_out;
wire arb_rw_out;
wire xbar_rw_out;
wire [BANK_ADDR_WIDTH-1:0] xbar_addr_out;
wire [XBAR_TAG_WIDTH-1:0] xbar_tag_out;
wire [DATA_WIDTH-1:0] xbar_data_out;
wire [DATA_SIZE-1:0] xbar_byteen_out;
wire [NUM_PORTS_IN-1:0][ARB_DATAW-1:0] arb_data_in;
wire [NUM_PORTS_IN-1:0] arb_valid_in;
for (genvar j = 0; j < NUM_PORTS_IN; ++j) begin : g_valid_in
wire tag_ready = mem_req_rw[j] || mem_rd_req_tag_ready[j];
assign arb_valid_in[j] = mem_req_valid[j] && tag_ready && (req_bank_sel[j] == i);
end
for (genvar j = 0; j < NUM_PORTS_IN; ++j) begin : g_data_in
wire [ARB_TAG_WIDTH-1:0] tag_value = mem_req_rw[j] ? ARB_TAG_WIDTH'(mem_req_tag[j]) : ARB_TAG_WIDTH'(mem_rd_req_tag[j]);
assign arb_data_in[j] = {mem_req_rw[j], req_bank_addr[j], mem_req_byteen[j], mem_req_data[j], tag_value};
end
VX_stream_arb #(
.NUM_INPUTS (NUM_PORTS_IN),
.NUM_OUTPUTS(1),
.DATAW (ARB_DATAW),
.ARBITER (ARBITER)
) aw_arb (
.clk (clk),
.reset (reset),
.valid_in (arb_valid_in),
.ready_in (arb_ready_in[i]),
.data_in (arb_data_in),
.data_out ({arb_rw_out, arb_addr_out, arb_byteen_out, arb_data_out, arb_tag_out}),
.valid_out (arb_valid_out),
.ready_out (arb_ready_out),
.sel_out (arb_sel_out)
);
assign {
xbar_rw_out,
xbar_addr_out,
xbar_byteen_out,
xbar_data_out,
xbar_tag_out
} = req_xbar_data_out[i];
// AXi request handshake
wire m_axi_arvalid_w, m_axi_arready_w;
wire m_axi_awvalid_w, m_axi_awready_w;
wire m_axi_wvalid_w, m_axi_wready_w;
wire m_axi_aw_ack, m_axi_w_ack, axi_write_ready;
wire m_axi_aw_ack, m_axi_w_ack, axi_write_ready;
VX_axi_write_ack axi_write_ack (
.clk (clk),
.reset (reset),
.awvalid(m_axi_awvalid_w),
.awready(m_axi_awready_w),
.wvalid (m_axi_wvalid_w),
.wready (m_axi_wready_w),
.awvalid(m_axi_awvalid[i]),
.awready(m_axi_awready[i]),
.wvalid (m_axi_wvalid[i]),
.wready (m_axi_wready[i]),
.aw_ack (m_axi_aw_ack),
.w_ack (m_axi_w_ack),
.tx_rdy (axi_write_ready),
`UNUSED_PIN (tx_ack)
);
assign m_axi_arvalid_w = arb_valid_out && ~arb_rw_out;
assign m_axi_awvalid_w = arb_valid_out && arb_rw_out && ~m_axi_aw_ack;
assign m_axi_wvalid_w = arb_valid_out && arb_rw_out && ~m_axi_w_ack;
assign arb_ready_out = arb_rw_out ? axi_write_ready : m_axi_arready_w;
assign req_xbar_ready_out[i] = xbar_rw_out ? axi_write_ready : m_axi_arready[i];
// AXI write address channel
VX_elastic_buffer #(
.DATAW (BANK_ADDR_WIDTH + WRITE_TAG_WIDTH),
.SIZE (`TO_OUT_BUF_SIZE(REQ_OUT_BUF)),
.OUT_REG (`TO_OUT_BUF_REG(REQ_OUT_BUF)),
.LUTRAM (`TO_OUT_BUF_LUTRAM(REQ_OUT_BUF))
) aw_buf (
.clk (clk),
.reset (reset),
.valid_in (m_axi_awvalid_w),
.ready_in (m_axi_awready_w),
.data_in ({arb_addr_out, WRITE_TAG_WIDTH'(arb_tag_out)}),
.data_out ({buf_addr_w_out, buf_tag_w_out}),
.valid_out (m_axi_awvalid[i]),
.ready_out (m_axi_awready[i])
);
assign m_axi_awaddr[i] = ADDR_WIDTH_OUT'(buf_addr_w_out) << LOG2_DATA_SIZE;
assign m_axi_awid[i] = TAG_WIDTH_OUT'(buf_tag_w_out);
assign m_axi_awvalid[i] = req_xbar_valid_out[i] && xbar_rw_out && ~m_axi_aw_ack;
assign m_axi_awaddr[i] = ADDR_WIDTH_OUT'(xbar_addr_out) << LOG2_DATA_SIZE;
assign m_axi_awid[i] = TAG_WIDTH_OUT'(xbar_tag_out);
assign m_axi_awlen[i] = 8'b00000000;
assign m_axi_awsize[i] = 3'(LOG2_DATA_SIZE);
assign m_axi_awburst[i] = 2'b00;
@ -294,51 +264,24 @@ module VX_axi_adapter #(
// AXI write data channel
VX_elastic_buffer #(
.DATAW (DATA_SIZE + DATA_WIDTH),
.SIZE (`TO_OUT_BUF_SIZE(REQ_OUT_BUF)),
.OUT_REG (`TO_OUT_BUF_REG(REQ_OUT_BUF)),
.LUTRAM (`TO_OUT_BUF_LUTRAM(REQ_OUT_BUF))
) w_buf (
.clk (clk),
.reset (reset),
.valid_in (m_axi_wvalid_w),
.ready_in (m_axi_wready_w),
.data_in ({arb_byteen_out, arb_data_out}),
.data_out ({m_axi_wstrb[i], m_axi_wdata[i]}),
.valid_out (m_axi_wvalid[i]),
.ready_out (m_axi_wready[i])
);
assign m_axi_wlast[i] = 1'b1;
assign m_axi_wvalid[i] = req_xbar_valid_out[i] && xbar_rw_out && ~m_axi_w_ack;
assign m_axi_wstrb[i] = xbar_byteen_out;
assign m_axi_wdata[i] = xbar_data_out;
assign m_axi_wlast[i] = 1'b1;
// AXI read address channel
if (NUM_PORTS_IN > 1) begin : g_input_sel
assign arb_tag_r_out = READ_FULL_TAG_WIDTH'({arb_tag_out, arb_sel_out});
wire [READ_FULL_TAG_WIDTH-1:0] xbar_tag_r_out;
if (NUM_PORTS_IN > 1) begin : g_xbar_tag_r_out
assign xbar_tag_r_out = READ_FULL_TAG_WIDTH'({xbar_tag_out, req_xbar_sel_out});
end else begin : g_no_input_sel
`UNUSED_VAR (arb_sel_out)
assign arb_tag_r_out = READ_TAG_WIDTH'(arb_tag_out);
`UNUSED_VAR (req_xbar_sel_out)
assign xbar_tag_r_out = READ_TAG_WIDTH'(xbar_tag_out);
end
VX_elastic_buffer #(
.DATAW (BANK_ADDR_WIDTH + READ_FULL_TAG_WIDTH),
.SIZE (`TO_OUT_BUF_SIZE(REQ_OUT_BUF)),
.OUT_REG (`TO_OUT_BUF_REG(REQ_OUT_BUF)),
.LUTRAM (`TO_OUT_BUF_LUTRAM(REQ_OUT_BUF))
) ar_buf (
.clk (clk),
.reset (reset),
.valid_in (m_axi_arvalid_w),
.ready_in (m_axi_arready_w),
.data_in ({arb_addr_out, arb_tag_r_out}),
.data_out ({buf_addr_r_out, buf_tag_r_out}),
.valid_out (m_axi_arvalid[i]),
.ready_out (m_axi_arready[i])
);
assign m_axi_araddr[i] = ADDR_WIDTH_OUT'(buf_addr_r_out) << LOG2_DATA_SIZE;
assign m_axi_arid[i] = TAG_WIDTH_OUT'(buf_tag_r_out);
assign m_axi_arvalid[i] = req_xbar_valid_out[i] && ~xbar_rw_out;
assign m_axi_araddr[i] = ADDR_WIDTH_OUT'(xbar_addr_out) << LOG2_DATA_SIZE;
assign m_axi_arid[i] = TAG_WIDTH_OUT'(xbar_tag_r_out);
assign m_axi_arlen[i] = 8'b00000000;
assign m_axi_arsize[i] = 3'(LOG2_DATA_SIZE);
assign m_axi_arburst[i] = 2'b00;

30
hw/rtl/libs/VX_mem_bank_adapter.sv
View file

@ -179,25 +179,31 @@ module VX_mem_bank_adapter #(
for (genvar i = 0; i < NUM_BANKS_OUT; ++i) begin : g_req_xbar_data_out
wire rw_out;
wire [BANK_ADDR_WIDTH-1:0] addr_out;
wire [XBAR_TAG_WIDTH-1:0] tag_out;
wire [DATA_WIDTH-1:0] data_out;
wire [DATA_SIZE-1:0] byteen_out;
wire xbar_rw_out;
wire [BANK_ADDR_WIDTH-1:0] xbar_addr_out;
wire [XBAR_TAG_WIDTH-1:0] xbar_tag_out;
wire [DATA_WIDTH-1:0] xbar_data_out;
wire [DATA_SIZE-1:0] xbar_byteen_out;
assign {rw_out, addr_out, byteen_out, data_out, tag_out} = req_xbar_data_out[i];
assign {
xbar_rw_out,
xbar_addr_out,
xbar_byteen_out,
xbar_data_out,
xbar_tag_out
} = req_xbar_data_out[i];
assign mem_req_valid_out[i] = req_xbar_valid_out[i];
assign mem_req_rw_out[i] = rw_out;
assign mem_req_addr_out[i] = ADDR_WIDTH_OUT'(addr_out);
assign mem_req_byteen_out[i] = byteen_out;
assign mem_req_data_out[i] = data_out;
assign mem_req_rw_out[i] = xbar_rw_out;
assign mem_req_addr_out[i] = ADDR_WIDTH_OUT'(xbar_addr_out);
assign mem_req_byteen_out[i] = xbar_byteen_out;
assign mem_req_data_out[i] = xbar_data_out;
if (NUM_PORTS_IN > 1) begin : g_input_sel
assign mem_req_tag_out[i] = TAG_WIDTH_OUT'({tag_out, req_xbar_sel_out[i]});
assign mem_req_tag_out[i] = TAG_WIDTH_OUT'({xbar_tag_out, req_xbar_sel_out[i]});
end else begin : g_no_input_sel
`UNUSED_VAR (req_xbar_sel_out[i])
assign mem_req_tag_out[i] = TAG_WIDTH_OUT'(tag_out);
assign mem_req_tag_out[i] = TAG_WIDTH_OUT'(xbar_tag_out);
end
assign req_xbar_ready_out[i] = mem_req_ready_out[i];