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https://github.com/vortexgpgpu/vortex.git
synced 2025-04-23 21:39:10 -04:00
xrt afu bug fixes
This commit is contained in:
Blaise Tine
parent
9a6dbdf1a9
commit
2cf483ddf5
7 changed files with 116 additions and 110 deletions
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@ -236,8 +236,9 @@ module VX_afu_wrap #(
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wire [M_AXI_MEM_ADDR_WIDTH-1:0] m_axi_mem_araddr_u [C_M_AXI_MEM_NUM_BANKS];
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for (genvar i = 0; i < C_M_AXI_MEM_NUM_BANKS; ++i) begin : g_addressing
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assign m_axi_mem_awaddr_a[i] = C_M_AXI_MEM_ADDR_WIDTH'(m_axi_mem_awaddr_u[i]) + C_M_AXI_MEM_ADDR_WIDTH'(`PLATFORM_MEMORY_OFFSET);
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assign m_axi_mem_araddr_a[i] = C_M_AXI_MEM_ADDR_WIDTH'(m_axi_mem_araddr_u[i]) + C_M_AXI_MEM_ADDR_WIDTH'(`PLATFORM_MEMORY_OFFSET);
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localparam [C_M_AXI_MEM_ADDR_WIDTH-1:0] BANK_OFFSET = C_M_AXI_MEM_ADDR_WIDTH'(`PLATFORM_MEMORY_OFFSET) + C_M_AXI_MEM_ADDR_WIDTH'(i) << M_AXI_MEM_ADDR_WIDTH;
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assign m_axi_mem_awaddr_a[i] = C_M_AXI_MEM_ADDR_WIDTH'(m_axi_mem_awaddr_u[i]) + BANK_OFFSET;
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assign m_axi_mem_araddr_a[i] = C_M_AXI_MEM_ADDR_WIDTH'(m_axi_mem_araddr_u[i]) + BANK_OFFSET;
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end
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`SCOPE_IO_SWITCH (2)
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@ -164,12 +164,8 @@ scope-json: $(BUILD_DIR)/scope.json
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$(BUILD_DIR)/scope.json: $(BUILD_DIR)/vortex.xml
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mkdir -p $(BUILD_DIR); cd $(BUILD_DIR); $(SCRIPT_DIR)/scope.py vortex.xml -o scope.json
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gen-xml:
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$(BUILD_DIR)/kernel.xml:
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mkdir -p $(BUILD_DIR); cd $(BUILD_DIR); $(SRC_DIR)/gen_xml.py -n $(M_AXI_NUM_BANKS) -d $(M_AXI_DATA_WIDTH) -a $(M_AXI_ADDRESS_WIDTH) -o kernel.xml
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gen-xo: $(XO_CONTAINER)
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$(XO_CONTAINER): $(BUILD_DIR)/sources.txt $(BUILD_DIR)/kernel.xml
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$(XO_CONTAINER): $(BUILD_DIR)/sources.txt
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mkdir -p $(BUILD_DIR); cd $(BUILD_DIR); $(VIVADO) -mode batch -source $(SRC_DIR)/gen_xo.tcl -tclargs ../$(XO_CONTAINER) vortex_afu sources.txt $(SCRIPT_DIR) ../$(BUILD_DIR)
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gen-bin: $(XCLBIN_CONTAINER)
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@ -1,75 +0,0 @@
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#!/usr/bin/env python3
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# Copyright © 2019-2023
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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import argparse
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import xml.etree.ElementTree as ET
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from xml.dom import minidom
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def prettify(elem):
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"""Return a pretty-printed XML string for the Element."""
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rough_string = ET.tostring(elem, 'utf-8')
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reparsed = minidom.parseString(rough_string)
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return reparsed.toprettyxml(indent=" ")
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def generate_xml(numbanks, datawidth, addresswidth, offset, output_file):
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root = ET.Element("root", versionMajor="1", versionMinor="6")
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kernel = ET.SubElement(root, "kernel", name="vortex_afu", language="ip_c",
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vlnv="mycompany.com:kernel:vortex_afu:1.0",
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attributes="", preferredWorkGroupSizeMultiple="0",
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workGroupSize="1", interrupt="true")
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ports = ET.SubElement(kernel, "ports")
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# control ports
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ET.SubElement(ports, "port", name="s_axi_ctrl", mode="slave", range="0x1000", dataWidth="32", portType="addressable", base="0x0")
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# memory ports
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for i in range(numbanks):
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port_name = f"m_axi_mem_{i}"
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ET.SubElement(ports, "port", name=port_name, mode="master", range=f"0x{(1 << addresswidth) - 1:X}", dataWidth=str(datawidth), portType="addressable", base=f"0x0")
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args = ET.SubElement(kernel, "args")
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# control args
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ET.SubElement(args, "arg", name="dev", addressQualifier="0", id="0", port="s_axi_ctrl", size="0x4", offset="0x010", type="uint", hostOffset="0x0", hostSize="0x4")
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ET.SubElement(args, "arg", name="isa", addressQualifier="0", id="1", port="s_axi_ctrl", size="0x4", offset="0x018", type="uint", hostOffset="0x0", hostSize="0x4")
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ET.SubElement(args, "arg", name="dcr", addressQualifier="0", id="2", port="s_axi_ctrl", size="0x4", offset="0x020", type="uint", hostOffset="0x0", hostSize="0x4")
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ET.SubElement(args, "arg", name="scp", addressQualifier="0", id="3", port="s_axi_ctrl", size="0x4", offset="0x028", type="uint", hostOffset="0x0", hostSize="0x4")
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# memory args
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for i in range(numbanks):
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arg_name = f"mem_{i}"
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ET.SubElement(args, "arg", name=arg_name, addressQualifier="1", id=str(4 + i),
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port=f"m_axi_mem_{i}", size="0x8", offset=f"0x{offset + (i * 8):X}",
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type="int*", hostOffset="0x0", hostSize="0x8")
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# Pretty-print and write the XML to file
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with open(output_file, "w") as f:
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f.write(prettify(root))
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def main():
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parser = argparse.ArgumentParser(description="Kernel Configuration File Generator")
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parser.add_argument("-n", "--numbanks", type=int, default=1, help="Number of AXI memory banks")
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parser.add_argument("-d", "--datawidth", type=int, default=512, help="Data width of the AXI memory ports")
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parser.add_argument("-a", "--addresswidth", type=int, default=28, help="Address width of the AXI memory ports")
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parser.add_argument("-x", "--offset", type=lambda x: int(x, 0), default=0x30, help="Starting offset for kernel args (hex)")
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parser.add_argument("-o", "--output", type=str, default="kernel.xml", help="Output XML file name")
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args = parser.parse_args()
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# Call the generate function
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generate_xml(args.numbanks, args.datawidth, args.addresswidth, args.offset, args.output)
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if __name__ == "__main__":
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main()
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@ -37,4 +37,4 @@ set argv [list ${krnl_name} ${vcs_file} ${tool_dir} ${build_dir}]
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set argc 4
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source ${script_path}/package_kernel.tcl
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package_xo -xo_path ${xoname} -kernel_name ${krnl_name} -ip_directory "${build_dir}/xo/packaged_kernel" -kernel_xml ${build_dir}/kernel.xml
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package_xo -xo_path ${xoname} -kernel_name ${krnl_name} -ip_directory "${build_dir}/xo/packaged_kernel"
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@ -160,6 +160,106 @@ for {set i 0} {$i < $num_banks} {incr i} {
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ipx::associate_bus_interfaces -busif m_axi_mem_$i -clock ap_clk $core
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}
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set mem_map [::ipx::add_memory_map -quiet "s_axi_ctrl" $core]
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set addr_block [::ipx::add_address_block -quiet "reg0" $mem_map]
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set reg [::ipx::add_register "CTRL" $addr_block]
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set_property description "Control signals" $reg
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set_property address_offset 0x000 $reg
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set_property size 32 $reg
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set field [ipx::add_field AP_START $reg]
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set_property ACCESS {read-write} $field
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set_property BIT_OFFSET {0} $field
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set_property BIT_WIDTH {1} $field
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set_property DESCRIPTION {Control signal Register for 'ap_start'.} $field
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set_property MODIFIED_WRITE_VALUE {modify} $field
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set field [ipx::add_field AP_DONE $reg]
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set_property ACCESS {read-only} $field
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set_property BIT_OFFSET {1} $field
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set_property BIT_WIDTH {1} $field
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set_property DESCRIPTION {Control signal Register for 'ap_done'.} $field
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set_property READ_ACTION {modify} $field
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set field [ipx::add_field AP_IDLE $reg]
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set_property ACCESS {read-only} $field
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set_property BIT_OFFSET {2} $field
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set_property BIT_WIDTH {1} $field
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set_property DESCRIPTION {Control signal Register for 'ap_idle'.} $field
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set_property READ_ACTION {modify} $field
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set field [ipx::add_field AP_READY $reg]
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set_property ACCESS {read-only} $field
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set_property BIT_OFFSET {3} $field
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set_property BIT_WIDTH {1} $field
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set_property DESCRIPTION {Control signal Register for 'ap_ready'.} $field
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set_property READ_ACTION {modify} $field
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set field [ipx::add_field RESERVED_1 $reg]
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set_property ACCESS {read-only} $field
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set_property BIT_OFFSET {4} $field
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set_property BIT_WIDTH {3} $field
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set_property DESCRIPTION {Reserved. 0s on read.} $field
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set_property READ_ACTION {modify} $field
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set field [ipx::add_field AUTO_RESTART $reg]
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set_property ACCESS {read-write} $field
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set_property BIT_OFFSET {7} $field
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set_property BIT_WIDTH {1} $field
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set_property DESCRIPTION {Control signal Register for 'auto_restart'.} $field
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set_property MODIFIED_WRITE_VALUE {modify} $field
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set field [ipx::add_field RESERVED_2 $reg]
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set_property ACCESS {read-only} $field
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set_property BIT_OFFSET {8} $field
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set_property BIT_WIDTH {24} $field
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set_property DESCRIPTION {Reserved. 0s on read.} $field
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set_property READ_ACTION {modify} $field
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set reg [::ipx::add_register "GIER" $addr_block]
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set_property description "Global Interrupt Enable Register" $reg
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set_property address_offset 0x004 $reg
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set_property size 32 $reg
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set reg [::ipx::add_register "IP_IER" $addr_block]
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set_property description "IP Interrupt Enable Register" $reg
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set_property address_offset 0x008 $reg
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set_property size 32 $reg
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set reg [::ipx::add_register "IP_ISR" $addr_block]
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set_property description "IP Interrupt Status Register" $reg
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set_property address_offset 0x00C $reg
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set_property size 32 $reg
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set reg [::ipx::add_register -quiet "DEV" $addr_block]
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set_property address_offset 0x010 $reg
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set_property size [expr {8*8}] $reg
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set reg [::ipx::add_register -quiet "ISA" $addr_block]
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set_property address_offset 0x018 $reg
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set_property size [expr {8*8}] $reg
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set reg [::ipx::add_register -quiet "DCR" $addr_block]
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set_property address_offset 0x020 $reg
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set_property size [expr {8*8}] $reg
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set reg [::ipx::add_register -quiet "SCP" $addr_block]
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set_property address_offset 0x028 $reg
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set_property size [expr {8*8}] $reg
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for {set i 0} {$i < $num_banks} {incr i} {
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# Add register for each memory bank
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set reg [::ipx::add_register -quiet "MEM_$i" $addr_block]
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set_property address_offset [expr {0x30 + $i * 8}] $reg
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set_property size [expr {8*8}] $reg
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# Associate the bus interface
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set regparam [::ipx::add_register_parameter ASSOCIATED_BUSIF $reg]
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set_property value m_axi_mem_$i $regparam
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}
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set_property slave_memory_map_ref "s_axi_ctrl" [::ipx::get_bus_interfaces -of $core "s_axi_ctrl"]
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set_property xpm_libraries {XPM_CDC XPM_MEMORY XPM_FIFO} $core
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set_property sdx_kernel true $core
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set_property sdx_kernel_type rtl $core
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@ -1,9 +1,7 @@
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# Platform specific configurations
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# Add your platform specific configurations here
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M_AXI_NUM_BANKS := 1
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M_AXI_DATA_WIDTH := 512
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M_AXI_ADDRESS_WIDTH := 32
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CONFIGS += -DPLATFORM_MEMORY_DATA_WIDTH=512
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ifeq ($(DEV_ARCH), zynquplus)
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# zynquplus
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@ -17,35 +15,21 @@ endif
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else
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# alveo
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ifneq ($(findstring xilinx_u55c,$(XSA)),)
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CONFIGS += -DPLATFORM_MEMORY_BANKS=32 -DPLATFORM_MEMORY_ADDR_WIDTH=28
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#VPP_FLAGS += --connectivity.sp vortex_afu_1.m_axi_mem_0:HBM[0:31]
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#CONFIGS += -DPLATFORM_MERGED_MEMORY_INTERFACE
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VPP_FLAGS += $(foreach i,$(shell seq 0 31), --connectivity.sp vortex_afu_1.m_axi_mem_$(i):HBM[$(i)])
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M_AXI_NUM_BANKS := 32
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M_AXI_ADDRESS_WIDTH := 28
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CONFIGS += -DPLATFORM_MEMORY_BANKS=32 -DPLATFORM_MEMORY_ADDR_WIDTH=29
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CONFIGS += -DPLATFORM_MERGED_MEMORY_INTERFACE
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VPP_FLAGS += --connectivity.sp vortex_afu_1.m_axi_mem_0:HBM[0:31]
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#VPP_FLAGS += $(foreach i,$(shell seq 0 31), --connectivity.sp vortex_afu_1.m_axi_mem_$(i):HBM[$(i)])
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else ifneq ($(findstring xilinx_u50,$(XSA)),)
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CONFIGS += -DPLATFORM_MEMORY_BANKS=16 -DPLATFORM_MEMORY_ADDR_WIDTH=28
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VPP_FLAGS += --connectivity.sp vortex_afu_1.m_axi_mem_0:HBM[0:15]
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M_AXI_NUM_BANKS := 16
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M_AXI_ADDRESS_WIDTH := 28
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CONFIGS += -DPLATFORM_MEMORY_BANKS=32 -DPLATFORM_MEMORY_ADDR_WIDTH=28
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VPP_FLAGS += --connectivity.sp vortex_afu_1.m_axi_mem_0:HBM[0:31]
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else ifneq ($(findstring xilinx_u280,$(XSA)),)
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CONFIGS += -DPLATFORM_MEMORY_BANKS=16 -DPLATFORM_MEMORY_ADDR_WIDTH=28
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VPP_FLAGS += --connectivity.sp vortex_afu_1.m_axi_mem_0:HBM[0:15]
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M_AXI_NUM_BANKS := 16
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M_AXI_ADDRESS_WIDTH := 28
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CONFIGS += -DPLATFORM_MEMORY_BANKS=32 -DPLATFORM_MEMORY_ADDR_WIDTH=28
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VPP_FLAGS += --connectivity.sp vortex_afu_1.m_axi_mem_0:HBM[0:31]
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else ifneq ($(findstring xilinx_u250,$(XSA)),)
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CONFIGS += -DPLATFORM_MEMORY_BANKS=4 -DPLATFORM_MEMORY_ADDR_WIDTH=34
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M_AXI_NUM_BANKS := 4
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M_AXI_ADDRESS_WIDTH := 34
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else ifneq ($(findstring xilinx_u200,$(XSA)),)
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CONFIGS += -DPLATFORM_MEMORY_BANKS=4 -DPLATFORM_MEMORY_ADDR_WIDTH=34
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M_AXI_NUM_BANKS := 4
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M_AXI_ADDRESS_WIDTH := 34
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else
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CONFIGS += -DPLATFORM_MEMORY_BANKS=1 -DPLATFORM_MEMORY_ADDR_WIDTH=32
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M_AXI_NUM_BANKS := 1
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M_AXI_ADDRESS_WIDTH := 32
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endif
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endif
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CONFIGS += -DPLATFORM_MEMORY_DATA_WIDTH=$(M_AXI_DATA_WIDTH)
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@ -476,7 +476,7 @@ private:
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if (*m_axi_mem_[i].arvalid && *m_axi_mem_[i].arready) {
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auto mem_req = new mem_req_t();
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mem_req->tag = *m_axi_mem_[i].arid;
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mem_req->addr = i * mem_bank_size_ + uint64_t(*m_axi_mem_[i].araddr);
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mem_req->addr = uint64_t(*m_axi_mem_[i].araddr);
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ram_->read(mem_req->data.data(), mem_req->addr, PLATFORM_MEMORY_DATA_SIZE);
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mem_req->write = false;
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mem_req->ready = false;
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@ -505,7 +505,7 @@ private:
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auto byteen = *m_axi_mem_[i].wstrb;
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auto data = (uint8_t*)m_axi_mem_[i].wdata->data();
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auto byte_addr = i * mem_bank_size_ + m_axi_states_[i].write_req_addr;
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auto byte_addr = m_axi_states_[i].write_req_addr;
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for (int i = 0; i < PLATFORM_MEMORY_DATA_SIZE; i++) {
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if ((byteen >> i) & 0x1) {
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