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minor update

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This commit is contained in:
Blaise Tine 2024-09-19 04:44:00 -07:00
parent a37309c6b0
commit 2d7f9eae0a
2 changed files with 22 additions and 19 deletions
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25
hw/rtl/libs/VX_axi_adapter.sv
View file

@ -100,26 +100,33 @@ module VX_axi_adapter #(
assign req_bank_sel = '0;
end
wire [NUM_BANKS-1:0] axi_aw_ready, axi_write_ready;
wire [NUM_BANKS-1:0] axi_write_ready;
for (genvar i = 0; i < NUM_BANKS; ++i) begin : g_axi_write_ready
assign axi_aw_ready[i] = m_axi_awready[i] || m_axi_aw_ack[i];
assign axi_write_ready[i] = m_axi_wready[i] && axi_aw_ready[i];
assign axi_write_ready[i] = (m_axi_awready[i] || m_axi_aw_ack[i])
&& (m_axi_wready[i] || m_axi_w_ack[i]);
end
// request ack
assign mem_req_ready = mem_req_rw ? axi_write_ready[req_bank_sel] : m_axi_arready[req_bank_sel];
reg [NUM_BANKS-1:0] m_axi_aw_ack;
wire mem_req_fire = mem_req_valid && mem_req_ready;
// AXi write request synchronization
reg [NUM_BANKS-1:0] m_axi_aw_ack, m_axi_w_ack;
for (genvar i = 0; i < NUM_BANKS; ++i) begin : g_m_axi_w
wire m_axi_aw_fire = m_axi_awvalid[i] && m_axi_awready[i];
wire m_axi_w_fire = m_axi_wvalid[i] && m_axi_wready[i];
always @(posedge clk) begin
if (reset) begin
if (reset || (mem_req_fire && (req_bank_sel == i))) begin
m_axi_aw_ack[i] <= 0;
m_axi_w_ack[i] <= 0;
end else begin
if (m_axi_wvalid[i] && m_axi_wready[i]) begin
m_axi_aw_ack[i] <= 0;
end else if (m_axi_awvalid[i] && m_axi_awready[i]) begin
if (m_axi_aw_fire) begin
m_axi_aw_ack[i] <= 1;
end
if (m_axi_w_fire) begin
m_axi_w_ack[i] <= 1;
end
end
end
end
@ -141,7 +148,7 @@ module VX_axi_adapter #(
// AXI write request data channel
for (genvar i = 0; i < NUM_BANKS; ++i) begin : g_axi_write_data
assign m_axi_wvalid[i] = mem_req_valid && mem_req_rw && (req_bank_sel == i) && axi_aw_ready[i];
assign m_axi_wvalid[i] = mem_req_valid && mem_req_rw && (req_bank_sel == i) && ~m_axi_w_ack[i];
assign m_axi_wdata[i] = mem_req_data;
assign m_axi_wstrb[i] = mem_req_byteen;
assign m_axi_wlast[i] = 1'b1;

16
sim/xrtsim/xrt_sim.cpp
View file

@ -422,11 +422,9 @@ private:
void axi_mem_bus_eval() {
for (int i = 0; i < M_AXI_MEM_NUM_BANKS; ++i) {
// handle read responses
if (m_axi_states_[i].read_rsp_pending
&& (*m_axi_mem_[i].rready)) {
*m_axi_mem_[i].rvalid = 0;
m_axi_states_[i].read_rsp_pending = false;
}
if (m_axi_states_[i].read_rsp_pending && (*m_axi_mem_[i].rready)) {
*m_axi_mem_[i].rvalid = 0;
m_axi_states_[i].read_rsp_pending = false;
}
if (!m_axi_states_[i].read_rsp_pending) {
if (!pending_mem_reqs_[i].empty()
@ -446,11 +444,9 @@ private:
}
// handle write responses
if (m_axi_states_[i].write_rsp_pending) {
if (*m_axi_mem_[i].bready) {
*m_axi_mem_[i].bvalid = 0;
m_axi_states_[i].write_rsp_pending = false;
}
if (m_axi_states_[i].write_rsp_pending && *m_axi_mem_[i].bready) {
*m_axi_mem_[i].bvalid = 0;
m_axi_states_[i].write_rsp_pending = false;
}
if (!m_axi_states_[i].write_rsp_pending) {
if (!pending_mem_reqs_[i].empty()