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scope bug fixes

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This commit is contained in:
Blaise Tine 2020-10-06 03:59:27 -04:00
parent 4e1007e5b2
commit 309dd48fc6
8 changed files with 191 additions and 167 deletions
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10
driver/opae/vlsim/Makefile
View file

@ -20,11 +20,11 @@ DBG_FLAGS += -DDBG_CORE_REQ_INFO
#CONFIGS += -DNUM_CLUSTERS=2 -DNUM_CORES=4 -DL2_ENABLE=1
#CONFIGS += -DNUM_CLUSTERS=1 -DNUM_CORES=4 -DL2_ENABLE=1
CONFIGS += -DNUM_CLUSTERS=1 -DNUM_CORES=2 -DL2_ENABLE=0
#CONFIGS += -DNUM_CLUSTERS=1 -DNUM_CORES=1
#CONFIGS += -DNUM_CLUSTERS=1 -DNUM_CORES=2 -DL2_ENABLE=0
CONFIGS += -DNUM_CLUSTERS=1 -DNUM_CORES=1
DEBUG=1
#SCOPE=1
SCOPE=1
CFLAGS += -fPIC
@ -45,7 +45,7 @@ SRCS += $(RTL_DIR)/fp_cores/svdpi/float_dpi.cpp
FPU_INCLUDE = -I$(RTL_DIR)/fp_cores -I$(RTL_DIR)/fp_cores/svdpi -I$(RTL_DIR)/fp_cores/fpnew/src/common_cells/include -I$(RTL_DIR)/fp_cores/fpnew/src/common_cells/src -I$(RTL_DIR)/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl -I$(RTL_DIR)/fp_cores/fpnew/src
RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/cache $(FPU_INCLUDE)
VL_FLAGS += --language 1800-2009 --assert -Wall -Wpedantic $(CONFIGS)
VL_FLAGS += -O2 --language 1800-2009 --assert -Wall -Wpedantic $(CONFIGS)
VL_FLAGS += -Wno-DECLFILENAME
VL_FLAGS += --x-initial unique --x-assign unique
VL_FLAGS += verilator.vlt
@ -88,4 +88,4 @@ $(PROJECT): $(SRCS) $(SCOPE_CFG)
OPT_FAST="-O0 -g" make -j -C obj_dir -f V$(TOP).mk
clean:
rm -rf $(PROJECT) obj_dir
rm -rf $(PROJECT) obj_dir ../scope-defs.h ../../../hw/rtl/scope-defs.vh

114
driver/opae/vx_scope.cpp
View file

@ -31,6 +31,14 @@
#define MMIO_SCOPE_READ (AFU_IMAGE_MMIO_SCOPE_READ * 4)
#define MMIO_SCOPE_WRITE (AFU_IMAGE_MMIO_SCOPE_WRITE * 4)
#define CMD_GET_VALID 0
#define CMD_GET_DATA 1
#define CMD_GET_WIDTH 2
#define CMD_GET_COUNT 3
#define CMD_SET_DELAY 4
#define CMD_SET_STOP 5
#define CMD_GET_OFFSET 6
static constexpr int num_signals = sizeof(scope_signals) / sizeof(scope_signal_t);
constexpr int calcFrameWidth(int index = 0) {
@ -39,13 +47,24 @@ constexpr int calcFrameWidth(int index = 0) {
static constexpr int fwidth = calcFrameWidth();
uint64_t print_clock(std::ofstream& ofs, uint64_t delta, uint64_t timestamp) {
while (delta != 0) {
ofs << '#' << timestamp++ << std::endl;
ofs << "b0 0" << std::endl;
ofs << '#' << timestamp++ << std::endl;
ofs << "b1 0" << std::endl;
--delta;
}
return timestamp;
}
int vx_scope_start(fpga_handle hfpga, uint64_t delay) {
if (nullptr == hfpga)
return -1;
if (delay != uint64_t(-1)) {
// set start delay
uint64_t cmd_delay = ((delay << 3) | 4);
uint64_t cmd_delay = ((delay << 3) | CMD_SET_DELAY);
CHECK_RES(fpgaWriteMMIO64(hfpga, 0, MMIO_SCOPE_WRITE, cmd_delay));
std::cout << "scope start delay: " << delay << std::endl;
}
@ -59,7 +78,7 @@ int vx_scope_stop(fpga_handle hfpga, uint64_t delay) {
if (delay != uint64_t(-1)) {
// stop recording
uint64_t cmd_stop = ((delay << 3) | 5);
uint64_t cmd_stop = ((delay << 3) | CMD_SET_STOP);
CHECK_RES(fpgaWriteMMIO64(hfpga, 0, MMIO_SCOPE_WRITE, cmd_stop));
std::cout << "scope stop delay: " << delay << std::endl;
}
@ -68,18 +87,25 @@ int vx_scope_stop(fpga_handle hfpga, uint64_t delay) {
ofs << "$version Generated by Vortex Scope $end" << std::endl;
ofs << "$timescale 1 ns $end" << std::endl;
ofs << "$scope module TOP $end" << std::endl;
ofs << "$var reg 1 0 clk $end" << std::endl;
for (int i = 0; i < num_signals; ++i) {
ofs << "$var reg " << scope_signals[i].width << " " << (i+1) << " " << scope_signals[i].name << " $end" << std::endl;
}
ofs << "$upscope $end" << std::endl;
ofs << "enddefinitions $end" << std::endl;
uint64_t frame_width, max_frames, data_valid;
uint64_t frame_width, max_frames, data_valid, offset, delta;
uint64_t timestamp = 0;
uint64_t frame_offset = 0;
uint64_t frame_no = 0;
int signal_id = 0;
int signal_offset = 0;
// wait for recording to terminate
CHECK_RES(fpgaWriteMMIO64(hfpga, 0, MMIO_SCOPE_WRITE, 0));
CHECK_RES(fpgaWriteMMIO64(hfpga, 0, MMIO_SCOPE_WRITE, CMD_GET_VALID));
do {
CHECK_RES(fpgaReadMMIO64(hfpga, 0, MMIO_SCOPE_READ, &data_valid));
if (data_valid)
@ -89,60 +115,45 @@ int vx_scope_stop(fpga_handle hfpga, uint64_t delay) {
std::cout << "scope trace dump begin..." << std::endl;
CHECK_RES(fpgaWriteMMIO64(hfpga, 0, MMIO_SCOPE_WRITE, 2));
// get frame width
CHECK_RES(fpgaWriteMMIO64(hfpga, 0, MMIO_SCOPE_WRITE, CMD_GET_WIDTH));
CHECK_RES(fpgaReadMMIO64(hfpga, 0, MMIO_SCOPE_READ, &frame_width));
std::cout << "scope::frame_width=" << std::dec << frame_width << std::endl;
CHECK_RES(fpgaWriteMMIO64(hfpga, 0, MMIO_SCOPE_WRITE, 3));
CHECK_RES(fpgaReadMMIO64(hfpga, 0, MMIO_SCOPE_READ, &max_frames));
std::cout << "scope::max_frames=" << std::dec << max_frames << std::endl;
CHECK_RES(fpgaWriteMMIO64(hfpga, 0, MMIO_SCOPE_WRITE, 1));
std::cout << "scope::frame_width=" << std::dec << frame_width << std::endl;
if (fwidth != (int)frame_width) {
std::cerr << "invalid frame_width: expecting " << std::dec << fwidth << "!" << std::endl;
std::abort();
}
// get max frames
CHECK_RES(fpgaWriteMMIO64(hfpga, 0, MMIO_SCOPE_WRITE, CMD_GET_COUNT));
CHECK_RES(fpgaReadMMIO64(hfpga, 0, MMIO_SCOPE_READ, &max_frames));
std::cout << "scope::max_frames=" << std::dec << max_frames << std::endl;
// get offset
CHECK_RES(fpgaWriteMMIO64(hfpga, 0, MMIO_SCOPE_WRITE, CMD_GET_OFFSET));
CHECK_RES(fpgaReadMMIO64(hfpga, 0, MMIO_SCOPE_READ, &offset));
// get data
CHECK_RES(fpgaWriteMMIO64(hfpga, 0, MMIO_SCOPE_WRITE, CMD_GET_DATA));
// print clock header
CHECK_RES(fpgaReadMMIO64(hfpga, 0, MMIO_SCOPE_READ, &delta));
timestamp = print_clock(ofs, offset + delta + 2, timestamp);
signal_id = num_signals;
std::vector<char> signal_data(frame_width+1);
uint64_t frame_offset = 0;
uint64_t frame_no = 0;
uint64_t timestamp = 0;
int signal_id = 0;
int signal_offset = 0;
auto print_header = [&] () {
ofs << '#' << timestamp++ << std::endl;
ofs << "b0 0" << std::endl;
ofs << '#' << timestamp++ << std::endl;
ofs << "b1 0" << std::endl;
uint64_t delta;
auto res = fpgaReadMMIO64(hfpga, 0, MMIO_SCOPE_READ, &delta);
assert(res == FPGA_OK);
while (delta != 0) {
ofs << '#' << timestamp++ << std::endl;
ofs << "b0 0" << std::endl;
ofs << '#' << timestamp++ << std::endl;
ofs << "b1 0" << std::endl;
--delta;
}
signal_id = num_signals;
};
print_header();
do {
if (frame_no == (max_frames-1)) {
// verify last frame is valid
CHECK_RES(fpgaWriteMMIO64(hfpga, 0, MMIO_SCOPE_WRITE, 0));
CHECK_RES(fpgaWriteMMIO64(hfpga, 0, MMIO_SCOPE_WRITE, CMD_GET_VALID));
CHECK_RES(fpgaReadMMIO64(hfpga, 0, MMIO_SCOPE_READ, &data_valid));
assert(data_valid == 1);
CHECK_RES(fpgaWriteMMIO64(hfpga, 0, MMIO_SCOPE_WRITE, 1));
CHECK_RES(fpgaWriteMMIO64(hfpga, 0, MMIO_SCOPE_WRITE, CMD_GET_DATA));
}
// read next data words
uint64_t word;
CHECK_RES(fpgaReadMMIO64(hfpga, 0, MMIO_SCOPE_READ, &word));
@ -166,17 +177,24 @@ int vx_scope_stop(fpga_handle hfpga, uint64_t delay) {
assert(0 == signal_offset);
frame_offset = 0;
++frame_no;
if (frame_no != max_frames) {
print_header();
}
if (frame_no != max_frames) {
// print clock header
CHECK_RES(fpgaReadMMIO64(hfpga, 0, MMIO_SCOPE_READ, &delta));
timestamp = print_clock(ofs, delta + 1, timestamp);
signal_id = num_signals;
//std::cout << "*** " << frame_no << " frames, timestamp=" << timestamp << std::endl;
}
}
} while ((frame_offset % 64) != 0);
} while (frame_no != max_frames);
std::cout << "scope trace dump done! - " << (timestamp/2) << " cycles" << std::endl;
// verify data not valid
CHECK_RES(fpgaWriteMMIO64(hfpga, 0, MMIO_SCOPE_WRITE, 0));
CHECK_RES(fpgaWriteMMIO64(hfpga, 0, MMIO_SCOPE_WRITE, CMD_GET_VALID));
CHECK_RES(fpgaReadMMIO64(hfpga, 0, MMIO_SCOPE_READ, &data_valid));
assert(data_valid == 0);

18
hw/opae/vortex_afu.sv
View file

@ -200,6 +200,10 @@ wire[$bits(cp2af_sRxPort.c0.hdr.mdata)-1:0] cp2af_sRxPort_c0_hdr_mdata = cp2af_s
wire [2:0] cmd_type = (cp2af_sRxPort.c0.mmioWrValid && (MMIO_CMD_TYPE == mmio_hdr.address)) ? 3'(cp2af_sRxPort.c0.data) : 3'h0;
`ifdef SCOPE
reg scope_start;
`endif
always_ff @(posedge clk)
begin
if (reset) begin
@ -209,14 +213,18 @@ begin
cmd_io_addr <= 0;
cmd_mem_addr <= 0;
cmd_data_size <= 0;
`ifdef SCOPE
scope_start <= 0;
`endif
end
else begin
mmio_tx.mmioRdValid <= 0;
// serve MMIO write request
if (cp2af_sRxPort.c0.mmioWrValid)
begin
`ifdef SCOPE
scope_start <= 1;
`endif
case (mmio_hdr.address)
MMIO_IO_ADDR: begin
cmd_io_addr <= t_ccip_clAddr'(cp2af_sRxPort.c0.data);
@ -1030,7 +1038,7 @@ end
`ifdef SCOPE
localparam SCOPE_DATAW = $bits({`SCOPE_SIGNALS_DATA_LIST,`SCOPE_SIGNALS_UPD_LIST});
`SCOPE_ASSIGN (scope_reset, vx_reset);
`SCOPE_ASSIGN (scope_dram_req_valid, vx_dram_req_valid);
`SCOPE_ASSIGN (scope_dram_req_addr, {vx_dram_req_addr, 4'b0});
@ -1063,10 +1071,8 @@ localparam SCOPE_DATAW = $bits({`SCOPE_SIGNALS_DATA_LIST,`SCOPE_SIGNALS_UPD_LIST
wire scope_changed = `SCOPE_TRIGGERS;
wire scope_start = vx_reset;
VX_scope #(
.DATAW (SCOPE_DATAW),
.DATAW ($bits({`SCOPE_SIGNALS_DATA_LIST,`SCOPE_SIGNALS_UPD_LIST})),
.BUSW (64),
.SIZE (4096),
.UPDW ($bits({`SCOPE_SIGNALS_UPD_LIST}))

6
hw/rtl/VX_platform.vh
View file

@ -22,14 +22,16 @@
/* verilator lint_off WIDTH */ \
/* verilator lint_off UNOPTFLAT */ \
/* verilator lint_off UNDRIVEN */ \
/* verilator lint_off DECLFILENAME */
/* verilator lint_off DECLFILENAME */ \
/* verilator lint_off IMPLICIT */
`define IGNORE_WARNINGS_END /* verilator lint_on UNUSED */ \
/* verilator lint_on PINCONNECTEMPTY */ \
/* verilator lint_on WIDTH */ \
/* verilator lint_on UNOPTFLAT */ \
/* verilator lint_on UNDRIVEN */ \
/* verilator lint_on DECLFILENAME */
/* verilator lint_on DECLFILENAME */ \
/* verilator lint_on IMPLICIT */
`define UNUSED_VAR(x) always @(x) begin end

5
hw/rtl/VX_scope.vh
View file

@ -6,7 +6,10 @@
`include "scope-defs.vh"
`define SCOPE_ASSIGN(d,s) assign d = s
`define SCOPE_ASSIGN(d,s) \
`IGNORE_WARNINGS_BEGIN \
assign d = s \
`IGNORE_WARNINGS_END
`else

56
hw/rtl/libs/VX_scope.v
View file

@ -18,7 +18,7 @@ module VX_scope #(
input wire bus_write,
input wire bus_read
);
localparam DELTA_ENABLE = (UPDW != 0);
localparam UPDW_ENABLE = (UPDW != 0);
localparam MAX_DELTA = (2 ** DELTAW) - 1;
localparam CMD_GET_VALID = 3'd0;
@ -27,19 +27,21 @@ module VX_scope #(
localparam CMD_GET_COUNT = 3'd3;
localparam CMD_SET_DELAY = 3'd4;
localparam CMD_SET_STOP = 3'd5;
localparam CMD_RESERVED1 = 3'd6;
localparam CMD_GET_OFFSET= 3'd6;
localparam CMD_RESERVED2 = 3'd7;
localparam GET_VALID = 2'd0;
localparam GET_DATA = 2'd1;
localparam GET_WIDTH = 2'd2;
localparam GET_COUNT = 2'd3;
localparam GET_VALID = 3'd0;
localparam GET_DATA = 3'd1;
localparam GET_WIDTH = 3'd2;
localparam GET_COUNT = 3'd3;
localparam GET_OFFSET = 3'd6;
reg [DATAW-1:0] data_store [SIZE-1:0];
reg [DELTAW-1:0] delta_store [SIZE-1:0];
reg [UPDW-1:0] prev_trigger_id;
reg [DELTAW-1:0] delta;
reg [BUSW-1:0] bus_out_r;
reg [63:0] timestamp, start_time;
reg [`CLOG2(SIZE)-1:0] raddr, waddr, waddr_end;
@ -49,8 +51,7 @@ module VX_scope #(
reg [BUSW-3:0] delay_val, delay_cntr;
reg [1:0] out_cmd;
reg [2:0] get_cmd;
wire [2:0] cmd_type;
wire [BUSW-4:0] cmd_data;
assign {cmd_data, cmd_type} = bus_in;
@ -59,7 +60,7 @@ module VX_scope #(
always @(posedge clk) begin
if (reset) begin
out_cmd <= $bits(out_cmd)'(CMD_GET_VALID);
get_cmd <= $bits(get_cmd)'(CMD_GET_VALID);
raddr <= 0;
waddr <= 0;
waddr_end <= $bits(waddr)'(SIZE-1);
@ -74,13 +75,18 @@ module VX_scope #(
read_offset <= 0;
read_delta <= 0;
data_valid <= 0;
timestamp <= 0;
end else begin
timestamp <= timestamp + 1;
if (bus_write) begin
case (cmd_type)
CMD_GET_VALID,
CMD_GET_DATA,
CMD_GET_WIDTH,
CMD_GET_COUNT: out_cmd <= $bits(out_cmd)'(cmd_type);
CMD_GET_OFFSET,
CMD_GET_COUNT: get_cmd <= $bits(get_cmd)'(cmd_type);
CMD_SET_DELAY: delay_val <= $bits(delay_val)'(cmd_data);
CMD_SET_STOP: waddr_end <= $bits(waddr)'(cmd_data);
default:;
@ -92,8 +98,10 @@ module VX_scope #(
delta_flush <= 1;
if (0 == delay_val) begin
start_wait <= 0;
recording <= 1;
delay_cntr <= 0;
recording <= 1;
delta <= 0;
delay_cntr <= 0;
start_time <= timestamp;
end else begin
start_wait <= 1;
recording <= 0;
@ -106,16 +114,18 @@ module VX_scope #(
if (1 == delay_cntr) begin
start_wait <= 0;
recording <= 1;
delta <= 0;
start_time <= timestamp;
end
end
if (recording) begin
if (DELTA_ENABLE) begin
if (UPDW_ENABLE) begin
if (delta_flush
|| changed
|| (trigger_id != prev_trigger_id)) begin
data_store[waddr] <= data_in;
delta_store[waddr] <= delta;
data_store[waddr] <= data_in;
waddr <= waddr + 1;
delta <= 0;
delta_flush <= 0;
@ -125,7 +135,8 @@ module VX_scope #(
end
prev_trigger_id <= trigger_id;
end else begin
data_store[waddr] <= data_in;
delta_store[waddr] <= 0;
data_store[waddr] <= data_in;
waddr <= waddr + 1;
end
@ -134,12 +145,12 @@ module VX_scope #(
waddr <= waddr; // keep last address
recording <= 0;
data_valid <= 1;
read_delta <= DELTA_ENABLE;
read_delta <= 1;
end
end
if (bus_read
&& (out_cmd == GET_DATA)
&& (get_cmd == GET_DATA)
&& data_valid) begin
if (read_delta) begin
read_delta <= 0;
@ -150,14 +161,14 @@ module VX_scope #(
end else begin
raddr <= raddr + 1;
read_offset <= 0;
read_delta <= DELTA_ENABLE;
read_delta <= 1;
if (raddr == waddr) begin
data_valid <= 0;
end
end
end else begin
raddr <= raddr + 1;
read_delta <= DELTA_ENABLE;
read_delta <= 1;
if (raddr == waddr) begin
data_valid <= 0;
end
@ -168,11 +179,14 @@ module VX_scope #(
end
always @(*) begin
case (out_cmd)
case (get_cmd)
GET_VALID : bus_out_r = BUSW'(data_valid);
GET_WIDTH : bus_out_r = BUSW'(DATAW);
GET_COUNT : bus_out_r = BUSW'(waddr) + BUSW'(1);
GET_OFFSET: bus_out_r = BUSW'(start_time);
/* verilator lint_off WIDTH */
GET_DATA : bus_out_r = read_delta ? BUSW'(delta_store[raddr]) : BUSW'(data_store[raddr] >> read_offset);
/* verilator lint_on WIDTH */
default : bus_out_r = 0;
endcase
end
@ -182,7 +196,7 @@ module VX_scope #(
`ifdef DBG_PRINT_SCOPE
always @(posedge clk) begin
if (bus_read) begin
$display("%t: scope-read: cmd=%0d, out=%0h, addr=%0d", $time, out_cmd, bus_out, raddr);
$display("%t: scope-read: cmd=%0d, addr=%0d, value=%0h", $time, get_cmd, raddr, bus_out);
end
if (bus_write) begin
$display("%t: scope-write: cmd=%0d, value=%0d", $time, cmd_type, cmd_data);

37
hw/scripts/scope.json
View file

@ -27,7 +27,7 @@
"scope_dram_req_tag": "`VX_DRAM_TAG_WIDTH",
"!scope_dram_req_ready": 1,
"!scope_dram_rsp_valid": 1,
"scope_dram_rsp_data": 128,
"scope_dram_rsp_data": "`VX_DRAM_LINE_WIDTH",
"scope_dram_rsp_tag": "`VX_DRAM_TAG_WIDTH",
"!scope_dram_rsp_ready": 1,
"!scope_snp_req_valid": 1,
@ -83,7 +83,6 @@
"scope_issue_rs1_is_pc": 1,
"scope_issue_rs2_is_imm": 1,
"!scope_issue_ready": 1,
"!scope_gpr_rsp_valid": 1,
"scope_gpr_rsp_wid": "`NW_BITS",
"scope_gpr_rsp_pc": 32,
"scope_gpr_rsp_a": "`NUM_THREADS * 32",
@ -121,41 +120,11 @@
["scope_icache_req_valid_top", "scope_icache_req_ready_top"],
["scope_icache_rsp_valid_top", "scope_icache_rsp_ready_top"],
["scope_dcache_req_valid_top", "scope_dcache_req_ready_top"],
["scope_dcache_rsp_valid_top", "scope_dcache_rsp_ready_top"],
["scope_bank_valid_st0_l3_top"],
["scope_bank_valid_st1_l3_top"],
["scope_bank_valid_st2_l3_top"],
["scope_bank_stall_pipe_l3_top"],
["scope_bank_valid_st0_l2_top"],
["scope_bank_valid_st1_l2_top"],
["scope_bank_valid_st2_l2_top"],
["scope_bank_stall_pipe_l2_top"],
["scope_bank_valid_st0_l1d_top"],
["scope_bank_valid_st1_l1d_top"],
["scope_bank_valid_st2_l1d_top"],
["scope_bank_stall_pipe_l1d_top"],
["scope_bank_valid_st0_l1i_top"],
["scope_bank_valid_st1_l1i_top"],
["scope_bank_valid_st2_l1i_top"],
["scope_bank_stall_pipe_l1i_top"],
["scope_bank_valid_st0_l1s_top"],
["scope_bank_valid_st1_l1s_top"],
["scope_bank_valid_st2_l1s_top"],
["scope_bank_stall_pipe_l1s_top"],
["scope_issue_valid_top", "scope_issue_ready_top"],
["scope_gpr_rsp_valid_top"],
["scope_scoreboard_delay_top"],
["scope_gpr_delay_top"],
["scope_execute_delay_top"],
["scope_busy"]
["scope_issue_valid_top", "scope_issue_ready_top"]
]
}

112
hw/scripts/scope.py
View file

@ -291,56 +291,6 @@ def load_config(filename):
print("condfig=", config)
return config
def gen_cc_header(file, ports):
header = '''
#pragma once\n
struct scope_signal_t {
int width;
const char* name;
};\n
inline constexpr int __clog2(int n) { return (n > 1) ? 1 + __clog2((n + 1) >> 1) : 0; }\n
static constexpr scope_signal_t scope_signals[] = {'''
footer = "};"
def eval_macro(text):
expanded = expand_text(text)
if expanded:
text = expanded
text = text.replace('$clog2', '__clog2')
return text
def asize_name(asize):
def Q(arr, ss, asize, idx, N):
for i in range(asize[idx]):
tmp = ss + "_" + str(i)
if (idx + 1) < N:
Q(arr, tmp, asize, idx + 1, N)
else:
arr.append(tmp)
l = len(asize)
if l == 0:
return [""]
arr = []
Q(arr, "", asize, 0, l)
return arr
with open(file, 'w') as f:
print(header, file=f)
i = 0
for port in ports:
name = port[0]
size = eval_macro(str(port[1]))
for ss in asize_name(port[2]):
if i > 0:
print(",", file=f)
print("\t{" + size + ", \"" + name + ss + "\"}", file=f, end='')
i += 1
print("", file=f)
print(footer, file=f)
def gen_vl_header(file, taps, triggers):
header = '''
@ -590,6 +540,68 @@ def gen_vl_header(file, taps, triggers):
return all_ports
def gen_cc_header(file, ports):
header = '''
#pragma once\n
struct scope_signal_t {
int width;
const char* name;
};\n
inline constexpr int __clog2(int n) { return (n > 1) ? 1 + __clog2((n + 1) >> 1) : 0; }\n
static constexpr scope_signal_t scope_signals[] = {'''
footer = "};"
def eval_macro(text):
expanded = expand_text(text)
if expanded:
text = expanded
text = text.replace('$clog2', '__clog2')
return text
def asize_name(asize):
def Q(arr, ss, asize, idx, N):
for i in range(asize[idx]):
tmp = ss + "_" + str(i)
if (idx + 1) < N:
Q(arr, tmp, asize, idx + 1, N)
else:
arr.append(tmp)
l = len(asize)
if l == 0:
return [""]
arr = []
Q(arr, "", asize, 0, l)
return arr
with open(file, 'w') as f:
print(header, file=f)
i = 0
for port in ports:
if port[3]:
continue
name = port[0]
size = eval_macro(str(port[1]))
for ss in asize_name(port[2]):
if i > 0:
print(",", file=f)
print("\t{" + size + ", \"" + name + ss + "\"}", file=f, end='')
i += 1
for port in ports:
if not port[3]:
continue
name = port[0]
size = eval_macro(str(port[1]))
for ss in asize_name(port[2]):
if i > 0:
print(",", file=f)
print("\t{" + size + ", \"" + name + ss + "\"}", file=f, end='')
i += 1
print("", file=f)
print(footer, file=f)
def main():
parser = argparse.ArgumentParser(description='Scope headers generator.')
parser.add_argument('-vl', nargs='?', default='scope-defs.vh', metavar='file', help='Output Verilog header')