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minor update

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This commit is contained in:
Blaise Tine 2024-08-06 23:36:37 -07:00
parent 0d7012e69e
commit 30ebb65fc3
4 changed files with 39 additions and 103 deletions
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3
hw/rtl/core/VX_dispatch.sv
View file

@ -61,8 +61,7 @@ module VX_dispatch import VX_gpu_pkg::*; #(
.DATAW (DATAW),
.SIZE (2),
.OUT_REG (2), // 2-cycle EB for area reduction
.LUTRAM (1),
.MAX_FANOUT (`MAX_FANOUT * 64)
.LUTRAM (1)
) buffer (
.clk (clk),
.reset (buffer_reset),

6
hw/rtl/core/VX_operands.sv
View file

@ -183,8 +183,7 @@ module VX_operands import VX_gpu_pkg::*; #(
VX_pipe_register #(
.DATAW (1 + NUM_SRC_REGS * REGS_DATAW + NUM_BANKS + NUM_BANKS * REGS_DATAW + META_DATAW + NUM_BANKS * REQ_SEL_WIDTH),
.RESETW (1 + NUM_SRC_REGS * REGS_DATAW),
.MAX_FANOUT (`MAX_FANOUT * 64)
.RESETW (1 + NUM_SRC_REGS * REGS_DATAW)
) pipe_reg2 (
.clk (clk),
.reset (pipe2_reset),
@ -206,8 +205,7 @@ module VX_operands import VX_gpu_pkg::*; #(
.DATAW (DATAW),
.SIZE (`TO_OUT_BUF_SIZE(OUT_BUF)),
.OUT_REG (`TO_OUT_BUF_REG(OUT_BUF)),
.LUTRAM (1),
.MAX_FANOUT (`MAX_FANOUT * 64)
.LUTRAM (1)
) out_buf (
.clk (clk),
.reset (reset),

40
hw/rtl/libs/VX_elastic_buffer.sv
View file

@ -18,8 +18,7 @@ module VX_elastic_buffer #(
parameter DATAW = 1,
parameter SIZE = 1,
parameter OUT_REG = 0,
parameter LUTRAM = 0,
parameter MAX_FANOUT = 0
parameter LUTRAM = 0
) (
input wire clk,
input wire reset,
@ -41,43 +40,6 @@ module VX_elastic_buffer #(
assign data_out = data_in;
assign ready_in = ready_out;
end else if (MAX_FANOUT != 0 && (DATAW > (MAX_FANOUT + MAX_FANOUT/2))) begin
localparam NUM_SLICES = `CDIV(DATAW, MAX_FANOUT);
localparam N_DATAW = DATAW / NUM_SLICES;
for (genvar i = 0; i < NUM_SLICES; ++i) begin
localparam S_DATAW = (i == NUM_SLICES-1) ? (DATAW - i * N_DATAW) : N_DATAW;
wire valid_out_t, ready_in_t;
`UNUSED_VAR (valid_out_t)
`UNUSED_VAR (ready_in_t)
`RESET_RELAY (slice_reset, reset);
VX_elastic_buffer #(
.DATAW (S_DATAW),
.SIZE (SIZE),
.OUT_REG (OUT_REG),
.LUTRAM (LUTRAM)
) buffer_slice (
.clk (clk),
.reset (slice_reset),
.valid_in (valid_in),
.data_in (data_in[i * N_DATAW +: S_DATAW]),
.ready_in (ready_in_t),
.valid_out (valid_out_t),
.data_out (data_out[i * N_DATAW +: S_DATAW]),
.ready_out (ready_out)
);
if (i == 0) begin
assign ready_in = ready_in_t;
assign valid_out = valid_out_t;
end
end
end else if (SIZE == 1) begin
VX_pipe_buffer #(

93
hw/rtl/libs/VX_pipe_register.sv
View file

@ -17,8 +17,7 @@
module VX_pipe_register #(
parameter DATAW = 1,
parameter RESETW = 0,
parameter DEPTH = 1,
parameter MAX_FANOUT = 0
parameter DEPTH = 1
) (
input wire clk,
input wire reset,
@ -32,67 +31,45 @@ module VX_pipe_register #(
`UNUSED_VAR (enable)
assign data_out = data_in;
end else if (DEPTH == 1) begin
if (MAX_FANOUT != 0 && (DATAW > (MAX_FANOUT + MAX_FANOUT/2))) begin
localparam NUM_SLICES = `CDIV(DATAW, MAX_FANOUT);
localparam N_DATAW = DATAW / NUM_SLICES;
for (genvar i = 0; i < NUM_SLICES; ++i) begin
localparam SLICE_START = i * N_DATAW;
localparam SLICE_END = SLICE_START + S_DATAW - 1;
localparam S_DATAW = (i == NUM_SLICES-1) ? (DATAW - SLICE_START) : N_DATAW;
localparam S_RESETW = (SLICE_END >= (DATAW - RESETW)) ?
((SLICE_START >= (DATAW - RESETW)) ? S_DATAW : (SLICE_END - (DATAW - RESETW) + 1)) : 0;
VX_pipe_register #(
.DATAW (S_DATAW),
.RESETW (S_RESETW)
) pipe_register_slice (
.clk (clk),
.reset (reset),
.enable (enable),
.data_in (data_in[i * N_DATAW +: S_DATAW]),
.data_out (data_out[i * N_DATAW +: S_DATAW])
);
if (RESETW == 0) begin
`UNUSED_VAR (reset)
reg [DATAW-1:0] value;
always @(posedge clk) begin
if (enable) begin
value <= data_in;
end
end
assign data_out = value;
end else if (RESETW == DATAW) begin
reg [DATAW-1:0] value;
always @(posedge clk) begin
if (reset) begin
value <= RESETW'(0);
end else if (enable) begin
value <= data_in;
end
end
assign data_out = value;
end else begin
if (RESETW == 0) begin
`UNUSED_VAR (reset)
reg [DATAW-1:0] value;
reg [DATAW-RESETW-1:0] value_d;
reg [RESETW-1:0] value_r;
always @(posedge clk) begin
if (enable) begin
value <= data_in;
end
always @(posedge clk) begin
if (reset) begin
value_r <= RESETW'(0);
end else if (enable) begin
value_r <= data_in[DATAW-1:DATAW-RESETW];
end
assign data_out = value;
end else if (RESETW == DATAW) begin
reg [DATAW-1:0] value;
always @(posedge clk) begin
if (reset) begin
value <= RESETW'(0);
end else if (enable) begin
value <= data_in;
end
end
assign data_out = value;
end else begin
reg [DATAW-RESETW-1:0] value_d;
reg [RESETW-1:0] value_r;
always @(posedge clk) begin
if (reset) begin
value_r <= RESETW'(0);
end else if (enable) begin
value_r <= data_in[DATAW-1:DATAW-RESETW];
end
end
always @(posedge clk) begin
if (enable) begin
value_d <= data_in[DATAW-RESETW-1:0];
end
end
assign data_out = {value_r, value_d};
end
always @(posedge clk) begin
if (enable) begin
value_d <= data_in[DATAW-RESETW-1:0];
end
end
assign data_out = {value_r, value_d};
end
end else begin
wire [DEPTH:0][DATAW-1:0] data_delayed;