arbiters optimization

This commit is contained in:
Blaise Tine 2024-08-10 18:41:10 -07:00
parent eaa7ed7fe2
commit 32a882e26f
5 changed files with 87 additions and 20 deletions

View file

@ -38,17 +38,17 @@ module VX_fair_arbiter #(
end else begin
reg [NUM_REQS-1:0] grant_hist;
reg [NUM_REQS-1:0] reqs_mask;
wire [NUM_REQS-1:0] requests_sel = requests & ~grant_hist;
wire rem_valid = (| requests_sel);
wire [NUM_REQS-1:0] requests_qual = rem_valid ? requests_sel : requests;
wire [NUM_REQS-1:0] requests_rem = requests & reqs_mask;
wire rem_valid = (| requests_rem);
wire [NUM_REQS-1:0] requests_qual = rem_valid ? requests_rem : requests;
always @(posedge clk) begin
if (reset) begin
grant_hist <= '0;
reqs_mask <= '1;
end else if (grant_valid && grant_ready) begin
grant_hist <= rem_valid ? (grant_hist | grant_onehot) : grant_onehot;
reqs_mask <= rem_valid ? (reqs_mask & ~grant_onehot) : ~grant_onehot;
end
end

View file

@ -124,6 +124,16 @@ module VX_onehot_mux #(
assign data_out[i] = (| gather);
end
end else if (MODEL == 2) begin
VX_find_first #(
.N (N),
.DATAW (DATAW)
) find_first (
.valid_in (sel_in),
.data_in (data_in),
.data_out (data_out),
`UNUSED_PIN (valid_out)
);
end else if (MODEL == 3) begin
reg [DATAW-1:0] data_out_r;
always @(*) begin
data_out_r = 'x;

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@ -0,0 +1,30 @@
// Copyright © 2019-2023
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
`include "VX_platform.vh"
module VX_onehot_shift #(
parameter N = 1,
parameter M = 1
) (
input wire [N-1:0] data_in0,
input wire [M-1:0] data_in1,
output wire [N*M-1:0] data_out
);
for (genvar i = 0; i < M; ++i) begin
for (genvar j = 0; j < N; ++j) begin
assign data_out[i*N + j] = data_in1[i] & data_in0[j];
end
end
endmodule

View file

@ -426,32 +426,30 @@ module VX_rr_arbiter #(
reg grant_valid_r;
reg [LOG_NUM_REQS-1:0] grant_index_r;
reg [NUM_REQS-1:0] grant_onehot_r;
reg [LOG_NUM_REQS-1:0] next_grant_index;
wire [NUM_REQS-1:0][LOG_NUM_REQS-1:0] next_grant_index_qual;
for (genvar i = 0; i < NUM_REQS; ++i) begin
assign next_grant_index_qual[i] = LOG_NUM_REQS'(i) + next_grant_index;
end
reg [NUM_REQS-1:0][LOG_NUM_REQS-1:0] next_grant_index;
always @(*) begin
grant_index_r = 'x;
grant_onehot_r = 'x;
grant_valid_r = 0;
for (integer i = 0; i < NUM_REQS; ++i) begin
if (requests[next_grant_index_qual[i]]) begin
grant_valid_r = 1;
grant_index_r = next_grant_index_qual[i];
grant_onehot_r = NUM_REQS'(1) << next_grant_index_qual[i];
break;
for (integer i = NUM_REQS-1; i >= 0; --i) begin
if (requests[next_grant_index[i]]) begin
grant_valid_r = 1;
grant_index_r = next_grant_index[i];
grant_onehot_r = NUM_REQS'(1) << next_grant_index[i];
end
end
end
always @(posedge clk) begin
if (reset) begin
next_grant_index <= '0;
for (integer i = 0; i < NUM_REQS; ++i) begin
next_grant_index[i] <= LOG_NUM_REQS'(i);
end
end else if (grant_valid && grant_ready) begin
next_grant_index <= grant_index_r + LOG_NUM_REQS'(1);
for (integer i = 0; i < NUM_REQS; ++i) begin
next_grant_index[i] <= grant_index_r + LOG_NUM_REQS'(i + 1);
end
end
end

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@ -0,0 +1,29 @@
// Copyright © 2019-2023
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
`include "VX_platform.vh"
module VX_transpose #(
parameter N = 1,
parameter M = 1
) (
input wire [N-1:0][M-1:0] data_in,
output wire [M-1:0][N-1:0] data_out
);
for (genvar i = 0; i < N; ++i) begin
for (genvar j = 0; j < M; ++j) begin
assign data_out[j][i] = data_in[i][j];
end
end
endmodule