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reset network optimization

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This commit is contained in:
Blaise Tine 2021-07-01 18:05:59 -07:00
parent 65c1078158
commit 360f8e4e37
6 changed files with 74 additions and 71 deletions
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22
hw/rtl/VX_cluster.v
View file

@ -44,24 +44,24 @@ module VX_cluster #(
wire [`NUM_CORES-1:0] per_core_busy;
for (genvar i = 0; i < `NUM_CORES; i++) begin
wire core_reset;
VX_reset_relay #(
.DEPTH (`NUM_CORES > 1)
) reset_relay (
.clk (clk),
.reset (reset),
.reset_o (core_reset)
);
wire [`NUM_CORES-1:0] core_reset;
VX_reset_relay #(
.DEPTH (`NUM_CORES > 1),
.NUM_NODES (`NUM_CORES)
) reset_relay (
.clk (clk),
.reset (reset),
.reset_o (core_reset)
);
for (genvar i = 0; i < `NUM_CORES; i++) begin
VX_core #(
.CORE_ID(i + (CLUSTER_ID * `NUM_CORES))
) core (
`SCOPE_BIND_VX_cluster_core(i)
.clk (clk),
.reset (core_reset),
.reset (core_reset[i]),
.mem_req_valid (per_core_mem_req_valid[i]),
.mem_req_rw (per_core_mem_req_rw [i]),

32
hw/rtl/VX_execute.v
View file

@ -42,23 +42,32 @@ module VX_execute #(
VX_fpu_to_csr_if fpu_to_csr_if();
wire[`NUM_WARPS-1:0] csr_pending;
wire[`NUM_WARPS-1:0] fpu_pending;
wire alu_reset, lsu_reset, csr_reset, fpu_reset, gpu_reset;
VX_reset_relay #(
.NUM_NODES (5)
) reset_relay (
.clk (clk),
.reset (reset),
.reset_o ({alu_reset, lsu_reset, csr_reset, fpu_reset, gpu_reset})
);
VX_alu_unit #(
.CORE_ID(CORE_ID)
.CORE_ID (CORE_ID)
) alu_unit (
.clk (clk),
.reset (reset),
.reset (alu_reset),
.alu_req_if (alu_req_if),
.branch_ctl_if (branch_ctl_if),
.alu_commit_if (alu_commit_if)
);
VX_lsu_unit #(
.CORE_ID(CORE_ID)
.CORE_ID (CORE_ID)
) lsu_unit (
`SCOPE_BIND_VX_execute_lsu_unit
.clk (clk),
.reset (reset),
.reset (lsu_reset),
.dcache_req_if (dcache_req_if),
.dcache_rsp_if (dcache_rsp_if),
.lsu_req_if (lsu_req_if),
@ -67,12 +76,12 @@ module VX_execute #(
);
VX_csr_unit #(
.CORE_ID(CORE_ID)
.CORE_ID (CORE_ID)
) csr_unit (
.clk (clk),
.reset (reset),
.reset (csr_reset),
`ifdef PERF_ENABLE
.perf_memsys_if (perf_memsys_if),
.perf_memsys_if (perf_memsys_if),
.perf_pipeline_if (perf_pipeline_if),
`endif
.cmt_to_csr_if (cmt_to_csr_if),
@ -86,10 +95,10 @@ module VX_execute #(
`ifdef EXT_F_ENABLE
VX_fpu_unit #(
.CORE_ID(CORE_ID)
.CORE_ID (CORE_ID)
) fpu_unit (
.clk (clk),
.reset (reset),
.reset (fpu_reset),
.fpu_req_if (fpu_req_if),
.fpu_to_csr_if (fpu_to_csr_if),
.fpu_commit_if (fpu_commit_if),
@ -97,6 +106,7 @@ module VX_execute #(
.pending (fpu_pending)
);
`else
`UNUSED_VAR (fpu_reset)
`UNUSED_VAR (csr_pending)
`UNUSED_VAR (fpu_to_csr_if.read_frm)
assign fpu_req_if.ready = 0;
@ -115,11 +125,11 @@ module VX_execute #(
`endif
VX_gpu_unit #(
.CORE_ID(CORE_ID)
.CORE_ID (CORE_ID)
) gpu_unit (
`SCOPE_BIND_VX_execute_gpu_unit
.clk (clk),
.reset (reset),
.reset (gpu_reset),
.gpu_req_if (gpu_req_if),
.warp_ctl_if (warp_ctl_if),
.gpu_commit_if (gpu_commit_if)

19
hw/rtl/VX_mem_unit.v
View file

@ -63,14 +63,13 @@ module VX_mem_unit # (
.CORE_TAG_WIDTH (`DCORE_TAG_WIDTH-`SM_ENABLE)
) dcache_rsp_if();
wire icache_reset, dcache_reset;
wire icache_reset, dcache_reset, smem_reset;
VX_reset_relay #(
.NUM_NODES (2)
.NUM_NODES (3)
) reset_relay (
.clk (clk),
.reset (reset),
.reset_o ({dcache_reset, icache_reset})
.reset_o ({icache_reset, dcache_reset, smem_reset})
);
VX_cache #(
@ -213,14 +212,6 @@ module VX_mem_unit # (
.core_rsp_if (dcache_core_rsp_if)
);
wire scache_reset;
VX_reset_relay reset_relay (
.clk (clk),
.reset (reset),
.reset_o (scache_reset)
);
VX_shared_mem #(
.CACHE_ID (`SCACHE_ID),
.CACHE_SIZE (`SMEM_SIZE),
@ -233,7 +224,7 @@ module VX_mem_unit # (
.BANK_ADDR_OFFSET (`SBANK_ADDR_OFFSET)
) smem (
.clk (clk),
.reset (scache_reset),
.reset (smem_reset),
`ifdef PERF_ENABLE
.perf_cache_if (perf_smem_if),
@ -255,6 +246,8 @@ module VX_mem_unit # (
.core_rsp_ready (smem_rsp_if.ready)
);
end else begin
`UNUSED_VAR (smem_reset)
// core to D-cache request
assign dcache_req_if.valid = dcache_core_req_if.valid;
assign dcache_req_if.addr = dcache_core_req_if.addr;

22
hw/rtl/Vortex.v
View file

@ -42,24 +42,24 @@ module Vortex (
wire [`NUM_CLUSTERS-1:0] per_cluster_busy;
wire [`NUM_CLUSTERS-1:0] cluster_reset;
VX_reset_relay #(
.DEPTH (`NUM_CLUSTERS > 1),
.NUM_NODES (`NUM_CLUSTERS)
) reset_relay (
.clk (clk),
.reset (reset),
.reset_o (cluster_reset)
);
for (genvar i = 0; i < `NUM_CLUSTERS; i++) begin
wire cluster_reset;
VX_reset_relay #(
.DEPTH (`NUM_CLUSTERS > 1)
) reset_relay (
.clk (clk),
.reset (reset),
.reset_o (cluster_reset)
);
VX_cluster #(
.CLUSTER_ID(i)
) cluster (
`SCOPE_BIND_Vortex_cluster(i)
.clk (clk),
.reset (cluster_reset),
.reset (cluster_reset[i]),
.mem_req_valid (per_cluster_mem_req_valid [i]),
.mem_req_rw (per_cluster_mem_req_rw [i]),

24
hw/rtl/fp_cores/VX_fp_div.v
View file

@ -33,17 +33,17 @@ module VX_fp_div #(
wire stall = ~ready_out && valid_out;
wire enable = ~stall;
for (genvar i = 0; i < LANES; i++) begin
wire [LANES-1:0] fdiv_reset;
VX_reset_relay #(
.DEPTH (LANES > 1),
.NUM_NODES (LANES)
) reset_relay (
.clk (clk),
.reset (reset),
.reset_o (fdiv_reset)
);
wire fdiv_reset;
VX_reset_relay #(
.NUM_NODES(1)
) reset_relay (
.clk (clk),
.reset (reset),
.reset_o (fdiv_reset)
);
for (genvar i = 0; i < LANES; i++) begin
`ifdef VERILATOR
reg [31:0] r;
fflags_t f;
@ -59,7 +59,7 @@ module VX_fp_div #(
.RESETW (1)
) shift_req_dpi (
.clk (clk),
.reset (fdiv_reset),
.reset (fdiv_reset[i]),
.enable (enable),
.data_in (r),
.data_out (result[i])
@ -67,7 +67,7 @@ module VX_fp_div #(
`else
acl_fdiv fdiv (
.clk (clk),
.areset (fdiv_reset),
.areset (fdiv_reset[i]),
.en (enable),
.a (dataa[i]),
.b (datab[i]),

26
hw/rtl/fp_cores/VX_fp_sqrt.v
View file

@ -31,18 +31,18 @@ module VX_fp_sqrt #(
);
wire stall = ~ready_out && valid_out;
wire enable = ~stall;
wire [LANES-1:0] fsqrt_reset;
VX_reset_relay #(
.DEPTH (LANES > 1),
.NUM_NODES (LANES)
) reset_relay (
.clk (clk),
.reset (reset),
.reset_o (fsqrt_reset)
);
for (genvar i = 0; i < LANES; i++) begin
wire fsqrt_reset;
VX_reset_relay #(
.NUM_NODES(1)
) reset_relay (
.clk (clk),
.reset (reset),
.reset_o (fsqrt_reset)
);
for (genvar i = 0; i < LANES; i++) begin
`ifdef VERILATOR
reg [31:0] r;
fflags_t f;
@ -58,7 +58,7 @@ module VX_fp_sqrt #(
.RESETW (1)
) shift_req_dpi (
.clk (clk),
.reset (fsqrt_reset),
.reset (fsqrt_reset[i]),
.enable (enable),
.data_in (r),
.data_out (result[i])
@ -66,7 +66,7 @@ module VX_fp_sqrt #(
`else
acl_fsqrt fsqrt (
.clk (clk),
.areset (fsqrt_reset),
.areset (fsqrt_reset[i]),
.en (enable),
.a (dataa[i]),
.q (result[i])